1; RUN: llc -mtriple=thumbv7-netbsd-eabi -o - %s | FileCheck %s 2declare void @bar() 3 4; ARM's frame lowering attempts to tack another callee-saved register onto the 5; list when it detects a potential misaligned VFP store. However, if there are 6; none available it used to just vpush anyway and misreport the location of the 7; registers in unwind info. Since there are benefits to aligned stores, it's 8; better to correct the code than the .cfi_offset directive. 9 10define void @test_dpr_align(i8 %l, i8 %r) { 11; CHECK-LABEL: test_dpr_align: 12; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 13; CHECK: sub sp, #4 14; CHECK: vpush {d8} 15; CHECK: .cfi_offset d8, -48 16; CHECK-NOT: sub sp 17; [...] 18; CHECK: bl bar 19; CHECK-NOT: add sp 20; CHECK: vpop {d8} 21; CHECK: add sp, #4 22; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 23 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"() 24 call void @bar() 25 ret void 26} 27 28; The prologue (but not the epilogue) can be made more space efficient by 29; chucking an argument register into the list. Not worth it in general though, 30; "sub sp, #4" is likely faster. 31define void @test_dpr_align_tiny(i8 %l, i8 %r) minsize { 32; CHECK-LABEL: test_dpr_align_tiny: 33; CHECK: push.w {r3, r4, r5, r6, r7, r8, r9, r10, r11, lr} 34; CHECK-NOT: sub sp 35; CHECK: vpush {d8} 36; CHECK: .cfi_offset d8, -48 37; CHECK-NOT: sub sp 38; [...] 39; CHECK: bl bar 40; CHECK-NOT: add sp 41; CHECK: vpop {d8} 42; CHECK: add sp, #4 43; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 44 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"() 45 call void @bar() 46 ret void 47} 48 49 50; However, we shouldn't do a 2-step align/adjust if there are no DPRs to be 51; saved. 52define void @test_nodpr_noalign(i8 %l, i8 %r) { 53; CHECK-LABEL: test_nodpr_noalign: 54; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 55; CHECK-NOT: sub sp 56; CHECK: sub sp, #12 57; CHECK-NOT: sub sp 58; [...] 59; CHECK: bl bar 60; CHECK-NOT: add sp 61; CHECK: add sp, #12 62; CHECK-NOT: add sp 63; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 64 alloca i64 65 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"() 66 call void @bar() 67 ret void 68} 69