1; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 2 3; <rdar://problem/8529919> 4%struct.foo = type { i32, i32 } 5 6define void @func() nounwind { 7entry: 8 %tmp = load i32* undef, align 4 9 br label %bb1 10 11bb1: 12 %tmp1 = and i32 %tmp, 16 13 %tmp2 = icmp eq i32 %tmp1, 0 14 %invok.1.i = select i1 %tmp2, i32 undef, i32 0 15 %tmp119 = add i32 %invok.1.i, 0 16 br i1 undef, label %bb2, label %exit 17 18bb2: 19 %tmp120 = add i32 %tmp119, 0 20 %scevgep810.i = getelementptr %struct.foo* null, i32 %tmp120, i32 1 21 store i32 undef, i32* %scevgep810.i, align 4 22 br i1 undef, label %bb2, label %bb3 23 24bb3: 25 br i1 %tmp2, label %bb2, label %bb2 26 27exit: 28 ret void 29} 30 31; PR10520 - REG_SEQUENCE with implicit-def operands. 32define arm_aapcs_vfpcc void @foo() nounwind align 2 { 33bb: 34 %tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> <i32 1> 35 %tmp8 = bitcast <1 x i64> %tmp to <2 x float> 36 %tmp9 = shufflevector <2 x float> %tmp8, <2 x float> %tmp8, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 37 %tmp10 = fmul <4 x float> undef, %tmp9 38 %tmp11 = fadd <4 x float> %tmp10, undef 39 %tmp12 = fadd <4 x float> undef, %tmp11 40 %tmp13 = bitcast <4 x float> %tmp12 to i128 41 %tmp14 = bitcast i128 %tmp13 to <4 x float> 42 %tmp15 = bitcast <4 x float> %tmp14 to i128 43 %tmp16 = bitcast i128 %tmp15 to <4 x float> 44 %tmp17 = bitcast <4 x float> %tmp16 to i128 45 %tmp18 = bitcast i128 %tmp17 to <4 x float> 46 %tmp19 = bitcast <4 x float> %tmp18 to i128 47 %tmp20 = bitcast i128 %tmp19 to <4 x float> 48 store <4 x float> %tmp20, <4 x float>* undef, align 16 49 ret void 50} 51