14ae7e812SJaved Absar; REQUIRES: asserts 24ae7e812SJaved Absar; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 327b226fbSEugene Leviant; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=+use-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=POST-MISCHED 44ae7e812SJaved Absar 54ae7e812SJaved Absar; Check the latency for ALU shifted operand variants. 64ae7e812SJaved Absar; 74ae7e812SJaved Absar; CHECK: ********** MI Scheduling ********** 8*25528d6dSFrancis Visoiu Mistrih; CHECK: foo:%bb.0 entry 94ae7e812SJaved Absar 104ae7e812SJaved Absar; ALU, basic - 1 cyc I0/I1 114ae7e812SJaved Absar; CHECK: EORrr 124ae7e812SJaved Absar; CHECK: rdefs left 134ae7e812SJaved Absar; CHECK-NEXT: Latency : 1 144ae7e812SJaved Absar 154ae7e812SJaved Absar; ALU, shift by immed - 2 cyc M 164ae7e812SJaved Absar; CHECK: ADDrsi 174ae7e812SJaved Absar; CHECK: rdefs left 184ae7e812SJaved Absar; CHECK-NEXT: Latency : 2 194ae7e812SJaved Absar 204ae7e812SJaved Absar; ALU, shift by register, unconditional - 2 cyc M 214ae7e812SJaved Absar; CHECK: RSBrsr 224ae7e812SJaved Absar; CHECK: rdefs left 234ae7e812SJaved Absar; CHECK-NEXT: Latency : 2 244ae7e812SJaved Absar 254ae7e812SJaved Absar; ALU, shift by register, conditional - 2 cyc I0/I1 264ae7e812SJaved Absar; CHECK: ANDrsr 274ae7e812SJaved Absar; CHECK: rdefs left 284ae7e812SJaved Absar; CHECK-NEXT: Latency : 2 294ae7e812SJaved Absar 304ae7e812SJaved Absar; Checking scheduling units 314ae7e812SJaved Absar 324ae7e812SJaved Absar; CHECK: ** ScheduleDAGMILive::schedule picking next node 334ae7e812SJaved Absar; Skipping COPY 344ae7e812SJaved Absar; CHECK: ** ScheduleDAGMILive::schedule picking next node 354ae7e812SJaved Absar; CHECK: Scheduling 364ae7e812SJaved Absar; CHECK-SAME: ANDrsr 374ae7e812SJaved Absar; CHECK: Ready 384ae7e812SJaved Absar; CHECK-NEXT: A57UnitI 394ae7e812SJaved Absar 404ae7e812SJaved Absar; CHECK: ** ScheduleDAGMILive::schedule picking next node 414ae7e812SJaved Absar; CHECK: Scheduling 424ae7e812SJaved Absar; CHECK-SAME: CMPri 434ae7e812SJaved Absar; CHECK: Ready 444ae7e812SJaved Absar; CHECK-NEXT: A57UnitI 454ae7e812SJaved Absar 464ae7e812SJaved Absar; CHECK: ** ScheduleDAGMILive::schedule picking next node 474ae7e812SJaved Absar; CHECK: Scheduling 484ae7e812SJaved Absar; CHECK-SAME: RSBrsr 494ae7e812SJaved Absar; CHECK: Ready 504ae7e812SJaved Absar; CHECK-NEXT: A57UnitM 514ae7e812SJaved Absar 524ae7e812SJaved Absar; CHECK: ** ScheduleDAGMILive::schedule picking next node 534ae7e812SJaved Absar; CHECK: Scheduling 544ae7e812SJaved Absar; CHECK-SAME: ADDrsi 554ae7e812SJaved Absar; CHECK: Ready 564ae7e812SJaved Absar; CHECK-NEXT: A57UnitM 574ae7e812SJaved Absar 584ae7e812SJaved Absar; CHECK: ** ScheduleDAGMILive::schedule picking next node 594ae7e812SJaved Absar; CHECK: Scheduling 604ae7e812SJaved Absar; CHECK-SAME: EORrr 614ae7e812SJaved Absar; CHECK: Ready 624ae7e812SJaved Absar; CHECK-NEXT: A57UnitI 634ae7e812SJaved Absar 6427b226fbSEugene Leviant; Check that post RA MI scheduler is invoked with +use-misched 6527b226fbSEugene Leviant; POST-MISCHED: Before post-MI-sched 664ae7e812SJaved Absar 674ae7e812SJaved Absartarget datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 684ae7e812SJaved Absartarget triple = "armv8r-arm-none-eabi" 694ae7e812SJaved Absar 704ae7e812SJaved Absar; Function Attrs: norecurse nounwind readnone 714ae7e812SJaved Absardefine hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 { 724ae7e812SJaved Absarentry: 734ae7e812SJaved Absar %xor = xor i32 %a, %b 744ae7e812SJaved Absar %xor_shl = shl i32 %xor, 2 754ae7e812SJaved Absar %add = add i32 %xor_shl, %d 764ae7e812SJaved Absar %add_ashr = ashr i32 %add, %a 774ae7e812SJaved Absar %sub = sub i32 %add_ashr, %a 784ae7e812SJaved Absar %sub_lshr_pred = lshr i32 %sub, %c 794ae7e812SJaved Absar %pred = icmp sgt i32 %a, 4 804ae7e812SJaved Absar %and = and i32 %sub_lshr_pred, %b 814ae7e812SJaved Absar %rv = select i1 %pred, i32 %and, i32 %d 824ae7e812SJaved Absar ret i32 %rv 834ae7e812SJaved Absar} 844ae7e812SJaved Absar 85