xref: /llvm-project/llvm/test/CodeGen/ARM/build-attributes.ll (revision e26f7994222ab7113990d23b11a5fd4db733498f) 
1; This tests that MC/asm header conversion is smooth and that the
2; build attributes are correct
3
4; RUN: llc < %s -mtriple=thumbv5-linux-gnueabi -mcpu=xscale -mattr=+strict-align | FileCheck %s --check-prefix=XSCALE
5; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6
6; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6-FAST
7; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
8; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6M
9; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mattr=+strict-align  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST
10; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6M
11; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST
12; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align | FileCheck %s --check-prefix=ARM1156T2F-S
13; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast  | FileCheck %s --check-prefix=ARM1156T2F-S-FAST
14; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
15; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi | FileCheck %s --check-prefix=V7M
16; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7M-FAST
17; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
18; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7
19; RUN: llc < %s -mtriple=armv7-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
20; RUN: llc < %s -mtriple=armv7-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7-FAST
21; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8
22; RUN: llc < %s -mtriple=armv8-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V8-FAST
23; RUN: llc < %s -mtriple=armv8-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
24; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8
25; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
26; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-neon,-crypto | FileCheck %s --check-prefix=V8-FPARMv8
27; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-fp-armv8,-crypto | FileCheck %s --check-prefix=V8-NEON
28; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON
29; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO
30; RUN: llc < %s -mtriple=thumbv8m.base-linux-gnueabi | FileCheck %s --check-prefix=V8MBASELINE
31; RUN: llc < %s -mtriple=thumbv8m.main-linux-gnueabi | FileCheck %s --check-prefix=V8MMAINLINE
32; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT
33; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT-FAST
34; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
35; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-neon,+d16 | FileCheck %s --check-prefix=CORTEX-A5-NONEON
36; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A5-NOFPU
37; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-NOFPU-FAST
38; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT
39; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A9-SOFT-FAST
40; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A9-HARD
41; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A9-HARD-FAST
42; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
43; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 | FileCheck %s --check-prefix=CORTEX-A12-DEFAULT
44; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT
45; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A12-DEFAULT-FAST
46; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A12-NOFPU
47; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A12-NOFPU-FAST
48; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
49; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15
50; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A15-FAST
51; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
52; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 | FileCheck %s --check-prefix=CORTEX-A17-DEFAULT
53; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-FAST
54; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A17-NOFPU
55; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-NOFPU-FAST
56
57; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-FP16
58; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-D16-FP16
59; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp-only-sp,+d16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD
60; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp-only-sp,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD-FP16
61; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=+neon,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-NEON-FP16
62
63; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
64; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align | FileCheck %s --check-prefix=CORTEX-M0
65; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST
66; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
67; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -mattr=+strict-align | FileCheck %s --check-prefix=CORTEX-M0PLUS
68; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -mattr=+strict-align  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0PLUS-FAST
69; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
70; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -mattr=+strict-align | FileCheck %s --check-prefix=CORTEX-M1
71; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -mattr=+strict-align  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M1-FAST
72; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
73; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -mattr=+strict-align | FileCheck %s --check-prefix=SC000
74; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -mattr=+strict-align  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC000-FAST
75; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
76; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3
77; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M3-FAST
78; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
79; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 | FileCheck %s --check-prefix=SC300
80; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC300-FAST
81; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
82; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT
83; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-SOFT-FAST
84; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD
85; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-HARD-FAST
86; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
87; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SOFT
88; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-NOFPU-FAST
89; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SINGLE
90; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-FAST
91; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7-DOUBLE
92; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
93; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4 | FileCheck %s --check-prefix=CORTEX-R4
94; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4f | FileCheck %s --check-prefix=CORTEX-R4F
95; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5
96; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R5-FAST
97; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
98; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 | FileCheck %s --check-prefix=CORTEX-R7
99; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R7-FAST
100; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
101; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a35 | FileCheck %s --check-prefix=CORTEX-A35
102; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a35  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A35-FAST
103; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a35 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
104; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53
105; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A53-FAST
106; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
107; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
108; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A57-FAST
109; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
110; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=CORTEX-A72
111; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A72-FAST
112; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
113; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A
114; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1 | FileCheck %s --check-prefix=EXYNOS-M1
115; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-M1-FAST
116; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
117; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A-FAST
118; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
119; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s  --check-prefix=CORTEX-A7-CHECK
120; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s  --check-prefix=CORTEX-A7-CHECK-FAST
121; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon,-fp16 | FileCheck %s --check-prefix=CORTEX-A7-NOFPU
122; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon,-fp16  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-NOFPU-FAST
123; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4
124; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
125; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-FPUV4-FAST
126; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,,+d16,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4
127; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=pic | FileCheck %s --check-prefix=RELOC-PIC
128; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=static | FileCheck %s --check-prefix=RELOC-OTHER
129; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=default | FileCheck %s --check-prefix=RELOC-OTHER
130; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=dynamic-no-pic | FileCheck %s --check-prefix=RELOC-OTHER
131; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=RELOC-OTHER
132; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=PCS-R9-USE
133; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+reserve-r9,+strict-align | FileCheck %s --check-prefix=PCS-R9-RESERVE
134
135; ARMv8.1a (AArch32)
136; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi | FileCheck %s --check-prefix=NO-STRICT-ALIGN
137; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
138; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi | FileCheck %s --check-prefix=NO-STRICT-ALIGN
139; ARMv8a (AArch32)
140; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a35 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
141; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a35 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
142; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
143; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
144; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
145; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
146; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m1 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
147; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m1 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
148
149; ARMv7a
150; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
151; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
152; ARMv7r
153; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
154; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
155; ARMv7m
156; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
157; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
158; ARMv6
159; RUN: llc < %s -mtriple=armv6-none-netbsd-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN
160; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
161; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN
162; ARMv6k
163; RUN: llc < %s -mtriple=armv6k-none-netbsd-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN
164; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
165; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN
166; ARMv6m
167; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
168; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mattr=+strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN
169; RUN: llc < %s -mtriple=thumbv6m-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
170; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
171; ARMv5
172; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e | FileCheck %s --check-prefix=NO-STRICT-ALIGN
173; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
174
175; XSCALE:      .eabi_attribute 6, 5
176; XSCALE:      .eabi_attribute 8, 1
177; XSCALE:      .eabi_attribute 9, 1
178
179; DYN-ROUNDING: .eabi_attribute 19, 1
180
181; V6:   .eabi_attribute 6, 6
182; V6:   .eabi_attribute 8, 1
183;; We assume round-to-nearest by default (matches GCC)
184; V6-NOT:   .eabi_attribute 19
185;; The default choice made by llc is for a V6 CPU without an FPU.
186;; This is not an interesting detail, but for such CPUs, the default intention is to use
187;; software floating-point support. The choice is not important for targets without
188;; FPU support!
189; V6:   .eabi_attribute 20, 1
190; V6:   .eabi_attribute 21, 1
191; V6-NOT:   .eabi_attribute 22
192; V6:   .eabi_attribute 23, 3
193; V6:   .eabi_attribute 24, 1
194; V6:   .eabi_attribute 25, 1
195; V6-NOT:   .eabi_attribute 27
196; V6-NOT:   .eabi_attribute 28
197; V6-NOT:    .eabi_attribute 36
198; V6:    .eabi_attribute 38, 1
199; V6-NOT:    .eabi_attribute 42
200; V6-NOT:  .eabi_attribute 44
201; V6-NOT:    .eabi_attribute 68
202
203; V6-FAST-NOT:   .eabi_attribute 19
204;; Despite the V6 CPU having no FPU by default, we chose to flush to
205;; positive zero here. There's no hardware support doing this, but the
206;; fast maths software library might.
207; V6-FAST-NOT:   .eabi_attribute 20
208; V6-FAST-NOT:   .eabi_attribute 21
209; V6-FAST-NOT:   .eabi_attribute 22
210; V6-FAST:   .eabi_attribute 23, 1
211
212;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for
213;; V6-M, however we don't model the OS extension so this is fine.
214; V6M:  .eabi_attribute 6, 12
215; V6M-NOT:  .eabi_attribute 7
216; V6M:  .eabi_attribute 8, 0
217; V6M:  .eabi_attribute 9, 1
218; V6M-NOT:   .eabi_attribute 19
219;; The default choice made by llc is for a V6M CPU without an FPU.
220;; This is not an interesting detail, but for such CPUs, the default intention is to use
221;; software floating-point support. The choice is not important for targets without
222;; FPU support!
223; V6M:  .eabi_attribute 20, 1
224; V6M:   .eabi_attribute 21, 1
225; V6M-NOT:   .eabi_attribute 22
226; V6M:   .eabi_attribute 23, 3
227; V6M:  .eabi_attribute 24, 1
228; V6M:  .eabi_attribute 25, 1
229; V6M-NOT:  .eabi_attribute 27
230; V6M-NOT:  .eabi_attribute 28
231; V6M-NOT:  .eabi_attribute 36
232; V6M:  .eabi_attribute 38, 1
233; V6M-NOT:  .eabi_attribute 42
234; V6M-NOT:  .eabi_attribute 44
235; V6M-NOT:  .eabi_attribute 68
236
237; V6M-FAST-NOT:   .eabi_attribute 19
238;; Despite the V6M CPU having no FPU by default, we chose to flush to
239;; positive zero here. There's no hardware support doing this, but the
240;; fast maths software library might.
241; V6M-FAST-NOT:  .eabi_attribute 20
242; V6M-FAST-NOT:   .eabi_attribute 21
243; V6M-FAST-NOT:   .eabi_attribute 22
244; V6M-FAST:   .eabi_attribute 23, 1
245
246; ARM1156T2F-S: .cpu arm1156t2f-s
247; ARM1156T2F-S: .eabi_attribute 6, 8
248; ARM1156T2F-S: .eabi_attribute 8, 1
249; ARM1156T2F-S: .eabi_attribute 9, 2
250; ARM1156T2F-S: .fpu vfpv2
251; ARM1156T2F-S-NOT:   .eabi_attribute 19
252;; We default to IEEE 754 compliance
253; ARM1156T2F-S: .eabi_attribute 20, 1
254; ARM1156T2F-S: .eabi_attribute 21, 1
255; ARM1156T2F-S-NOT: .eabi_attribute 22
256; ARM1156T2F-S: .eabi_attribute 23, 3
257; ARM1156T2F-S: .eabi_attribute 24, 1
258; ARM1156T2F-S: .eabi_attribute 25, 1
259; ARM1156T2F-S-NOT: .eabi_attribute 27
260; ARM1156T2F-S-NOT: .eabi_attribute 28
261; ARM1156T2F-S-NOT: .eabi_attribute 36
262; ARM1156T2F-S: .eabi_attribute 38, 1
263; ARM1156T2F-S-NOT:    .eabi_attribute 42
264; ARM1156T2F-S-NOT:    .eabi_attribute 44
265; ARM1156T2F-S-NOT:    .eabi_attribute 68
266
267; ARM1156T2F-S-FAST-NOT:   .eabi_attribute 19
268;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally
269;; valid for this core, it's an implementation defined question as to which of 0 and 2 you
270;; select. LLVM historically picks 0.
271; ARM1156T2F-S-FAST-NOT: .eabi_attribute 20
272; ARM1156T2F-S-FAST-NOT:   .eabi_attribute 21
273; ARM1156T2F-S-FAST-NOT:   .eabi_attribute 22
274; ARM1156T2F-S-FAST:   .eabi_attribute 23, 1
275
276; V7M:  .eabi_attribute 6, 10
277; V7M:  .eabi_attribute 7, 77
278; V7M:  .eabi_attribute 8, 0
279; V7M:  .eabi_attribute 9, 2
280; V7M-NOT:   .eabi_attribute 19
281;; The default choice made by llc is for a V7M CPU without an FPU.
282;; This is not an interesting detail, but for such CPUs, the default intention is to use
283;; software floating-point support. The choice is not important for targets without
284;; FPU support!
285; V7M:  .eabi_attribute 20, 1
286; V7M: .eabi_attribute 21, 1
287; V7M-NOT: .eabi_attribute 22
288; V7M: .eabi_attribute 23, 3
289; V7M:  .eabi_attribute 24, 1
290; V7M:  .eabi_attribute 25, 1
291; V7M-NOT:  .eabi_attribute 27
292; V7M-NOT:  .eabi_attribute 28
293; V7M-NOT:  .eabi_attribute 36
294; V7M:  .eabi_attribute 38, 1
295; V7M-NOT:  .eabi_attribute 42
296; V7M-NOT:  .eabi_attribute 44
297; V7M-NOT:  .eabi_attribute 68
298
299; V7M-FAST-NOT:   .eabi_attribute 19
300;; Despite the V7M CPU having no FPU by default, we chose to flush
301;; preserving sign. This matches what the hardware would do in the
302;; architecture revision were to exist on the current target.
303; V7M-FAST:  .eabi_attribute 20, 2
304; V7M-FAST-NOT:   .eabi_attribute 21
305; V7M-FAST-NOT:   .eabi_attribute 22
306; V7M-FAST:   .eabi_attribute 23, 1
307
308; V7:      .syntax unified
309; V7: .eabi_attribute 6, 10
310; V7-NOT:   .eabi_attribute 19
311;; In safe-maths mode we default to an IEEE 754 compliant choice.
312; V7: .eabi_attribute 20, 1
313; V7: .eabi_attribute 21, 1
314; V7-NOT: .eabi_attribute 22
315; V7: .eabi_attribute 23, 3
316; V7: .eabi_attribute 24, 1
317; V7: .eabi_attribute 25, 1
318; V7-NOT: .eabi_attribute 27
319; V7-NOT: .eabi_attribute 28
320; V7-NOT: .eabi_attribute 36
321; V7: .eabi_attribute 38, 1
322; V7-NOT:    .eabi_attribute 42
323; V7-NOT:    .eabi_attribute 44
324; V7-NOT:    .eabi_attribute 68
325
326; V7-FAST-NOT:   .eabi_attribute 19
327;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
328;; denormals to zero preserving the sign.
329; V7-FAST: .eabi_attribute 20, 2
330; V7-FAST-NOT:   .eabi_attribute 21
331; V7-FAST-NOT:   .eabi_attribute 22
332; V7-FAST:   .eabi_attribute 23, 1
333
334; V8:      .syntax unified
335; V8: .eabi_attribute 67, "2.09"
336; V8: .eabi_attribute 6, 14
337; V8-NOT:   .eabi_attribute 19
338; V8: .eabi_attribute 20, 1
339; V8: .eabi_attribute 21, 1
340; V8-NOT: .eabi_attribute 22
341; V8: .eabi_attribute 23, 3
342; V8-NOT: .eabi_attribute 44
343
344; V8-FAST-NOT:   .eabi_attribute 19
345;; The default does have an FPU, and for V8-A, it flushes preserving sign.
346; V8-FAST: .eabi_attribute 20, 2
347; V8-FAST-NOT: .eabi_attribute 21
348; V8-FAST-NOT: .eabi_attribute 22
349; V8-FAST: .eabi_attribute 23, 1
350
351; Vt8:     .syntax unified
352; Vt8: .eabi_attribute 6, 14
353; Vt8-NOT:   .eabi_attribute 19
354; Vt8: .eabi_attribute 20, 1
355; Vt8: .eabi_attribute 21, 1
356; Vt8-NOT: .eabi_attribute 22
357; Vt8: .eabi_attribute 23, 3
358
359; V8-FPARMv8:      .syntax unified
360; V8-FPARMv8: .eabi_attribute 6, 14
361; V8-FPARMv8: .fpu fp-armv8
362
363; V8-NEON:      .syntax unified
364; V8-NEON: .eabi_attribute 6, 14
365; V8-NEON: .fpu neon
366; V8-NEON: .eabi_attribute 12, 3
367
368; V8-FPARMv8-NEON:      .syntax unified
369; V8-FPARMv8-NEON: .eabi_attribute 6, 14
370; V8-FPARMv8-NEON: .fpu neon-fp-armv8
371; V8-FPARMv8-NEON: .eabi_attribute 12, 3
372
373; V8-FPARMv8-NEON-CRYPTO:      .syntax unified
374; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 6, 14
375; V8-FPARMv8-NEON-CRYPTO: .fpu crypto-neon-fp-armv8
376; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 12, 3
377
378; V8MBASELINE: .syntax unified
379; '6' is Tag_CPU_arch, '16' is ARM v8-M Baseline
380; V8MBASELINE: .eabi_attribute 6, 16
381; '7' is Tag_CPU_arch_profile, '77' is 'M'
382; V8MBASELINE: .eabi_attribute 7, 77
383; '8' is Tag_ARM_ISA_use
384; V8MBASELINE: .eabi_attribute 8, 0
385; '9' is Tag_Thumb_ISA_use
386; V8MBASELINE: .eabi_attribute 9, 3
387
388; V8MMAINLINE: .syntax unified
389; '6' is Tag_CPU_arch, '17' is ARM v8-M Mainline
390; V8MMAINLINE: .eabi_attribute 6, 17
391; V8MMAINLINE: .eabi_attribute 7, 77
392; V8MMAINLINE: .eabi_attribute 8, 0
393; V8MMAINLINE: .eabi_attribute 9, 3
394
395; Tag_CPU_unaligned_access
396; NO-STRICT-ALIGN: .eabi_attribute 34, 1
397; STRICT-ALIGN: .eabi_attribute 34, 0
398
399; Tag_CPU_arch  'ARMv7'
400; CORTEX-A7-CHECK: .eabi_attribute      6, 10
401; CORTEX-A7-NOFPU: .eabi_attribute      6, 10
402
403; CORTEX-A7-FPUV4: .eabi_attribute      6, 10
404
405; Tag_CPU_arch_profile 'A'
406; CORTEX-A7-CHECK: .eabi_attribute      7, 65
407; CORTEX-A7-NOFPU: .eabi_attribute      7, 65
408; CORTEX-A7-FPUV4: .eabi_attribute      7, 65
409
410; Tag_ARM_ISA_use
411; CORTEX-A7-CHECK: .eabi_attribute      8, 1
412; CORTEX-A7-NOFPU: .eabi_attribute      8, 1
413; CORTEX-A7-FPUV4: .eabi_attribute      8, 1
414
415; Tag_THUMB_ISA_use
416; CORTEX-A7-CHECK: .eabi_attribute      9, 2
417; CORTEX-A7-NOFPU: .eabi_attribute      9, 2
418; CORTEX-A7-FPUV4: .eabi_attribute      9, 2
419
420; CORTEX-A7-CHECK: .fpu neon-vfpv4
421; CORTEX-A7-NOFPU-NOT: .fpu
422; CORTEX-A7-FPUV4: .fpu vfpv4
423
424; CORTEX-A7-CHECK-NOT:   .eabi_attribute 19
425; Tag_ABI_FP_denormal
426;; We default to IEEE 754 compliance
427; CORTEX-A7-CHECK: .eabi_attribute      20, 1
428;; The A7 has VFPv3 support by default, so flush preserving sign.
429; CORTEX-A7-CHECK-FAST: .eabi_attribute 20, 2
430; CORTEX-A7-NOFPU: .eabi_attribute      20, 1
431;; Despite there being no FPU, we chose to flush to zero preserving
432;; sign. This matches what the hardware would do for this architecture
433;; revision.
434; CORTEX-A7-NOFPU-FAST: .eabi_attribute 20, 2
435; CORTEX-A7-FPUV4: .eabi_attribute      20, 1
436;; The VFPv4 FPU flushes preserving sign.
437; CORTEX-A7-FPUV4-FAST: .eabi_attribute 20, 2
438
439; Tag_ABI_FP_exceptions
440; CORTEX-A7-CHECK: .eabi_attribute      21, 1
441; CORTEX-A7-NOFPU: .eabi_attribute      21, 1
442; CORTEX-A7-FPUV4: .eabi_attribute      21, 1
443
444; Tag_ABI_FP_user_exceptions
445; CORTEX-A7-CHECK-NOT: .eabi_attribute      22
446; CORTEX-A7-NOFPU-NOT: .eabi_attribute      22
447; CORTEX-A7-FPUV4-NOT: .eabi_attribute      22
448
449; Tag_ABI_FP_number_model
450; CORTEX-A7-CHECK: .eabi_attribute      23, 3
451; CORTEX-A7-NOFPU: .eabi_attribute      23, 3
452; CORTEX-A7-FPUV4: .eabi_attribute      23, 3
453
454; Tag_ABI_align_needed
455; CORTEX-A7-CHECK: .eabi_attribute      24, 1
456; CORTEX-A7-NOFPU: .eabi_attribute      24, 1
457; CORTEX-A7-FPUV4: .eabi_attribute      24, 1
458
459; Tag_ABI_align_preserved
460; CORTEX-A7-CHECK: .eabi_attribute      25, 1
461; CORTEX-A7-NOFPU: .eabi_attribute      25, 1
462; CORTEX-A7-FPUV4: .eabi_attribute      25, 1
463
464; Tag_FP_HP_extension
465; CORTEX-A7-CHECK: .eabi_attribute      36, 1
466; CORTEX-A7-NOFPU-NOT: .eabi_attribute  36
467; CORTEX-A7-FPUV4: .eabi_attribute      36, 1
468
469; Tag_FP_16bit_format
470; CORTEX-A7-CHECK: .eabi_attribute      38, 1
471; CORTEX-A7-NOFPU: .eabi_attribute      38, 1
472; CORTEX-A7-FPUV4: .eabi_attribute      38, 1
473
474; Tag_MPextension_use
475; CORTEX-A7-CHECK: .eabi_attribute      42, 1
476; CORTEX-A7-NOFPU: .eabi_attribute      42, 1
477; CORTEX-A7-FPUV4: .eabi_attribute      42, 1
478
479; Tag_DIV_use
480; CORTEX-A7-CHECK: .eabi_attribute      44, 2
481; CORTEX-A7-NOFPU: .eabi_attribute      44, 2
482; CORTEX-A7-FPUV4: .eabi_attribute      44, 2
483
484; Tag_Virtualization_use
485; CORTEX-A7-CHECK: .eabi_attribute      68, 3
486; CORTEX-A7-NOFPU: .eabi_attribute      68, 3
487; CORTEX-A7-FPUV4: .eabi_attribute      68, 3
488
489; CORTEX-A5-DEFAULT:        .cpu    cortex-a5
490; CORTEX-A5-DEFAULT:        .eabi_attribute 6, 10
491; CORTEX-A5-DEFAULT:        .eabi_attribute 7, 65
492; CORTEX-A5-DEFAULT:        .eabi_attribute 8, 1
493; CORTEX-A5-DEFAULT:        .eabi_attribute 9, 2
494; CORTEX-A5-DEFAULT:        .fpu    neon-vfpv4
495; CORTEX-A5-NOT:   .eabi_attribute 19
496;; We default to IEEE 754 compliance
497; CORTEX-A5-DEFAULT:        .eabi_attribute 20, 1
498; CORTEX-A5-DEFAULT:        .eabi_attribute 21, 1
499; CORTEX-A5-DEFAULT-NOT:        .eabi_attribute 22
500; CORTEX-A5-DEFAULT:        .eabi_attribute 23, 3
501; CORTEX-A5-DEFAULT:        .eabi_attribute 24, 1
502; CORTEX-A5-DEFAULT:        .eabi_attribute 25, 1
503; CORTEX-A5-DEFAULT:        .eabi_attribute 42, 1
504; CORTEX-A5-DEFAULT-NOT:        .eabi_attribute 44
505; CORTEX-A5-DEFAULT:        .eabi_attribute 68, 1
506
507; CORTEX-A5-DEFAULT-FAST-NOT:   .eabi_attribute 19
508;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
509;; is given.
510; CORTEX-A5-DEFAULT-FAST:        .eabi_attribute 20, 2
511; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 21
512; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 22
513; CORTEX-A5-DEFAULT-FAST: .eabi_attribute 23, 1
514
515; CORTEX-A5-NONEON:        .cpu    cortex-a5
516; CORTEX-A5-NONEON:        .eabi_attribute 6, 10
517; CORTEX-A5-NONEON:        .eabi_attribute 7, 65
518; CORTEX-A5-NONEON:        .eabi_attribute 8, 1
519; CORTEX-A5-NONEON:        .eabi_attribute 9, 2
520; CORTEX-A5-NONEON:        .fpu    vfpv4-d16
521;; We default to IEEE 754 compliance
522; CORTEX-A5-NONEON:        .eabi_attribute 20, 1
523; CORTEX-A5-NONEON:        .eabi_attribute 21, 1
524; CORTEX-A5-NONEON-NOT:    .eabi_attribute 22
525; CORTEX-A5-NONEON:        .eabi_attribute 23, 3
526; CORTEX-A5-NONEON:        .eabi_attribute 24, 1
527; CORTEX-A5-NONEON:        .eabi_attribute 25, 1
528; CORTEX-A5-NONEON:        .eabi_attribute 42, 1
529; CORTEX-A5-NONEON:        .eabi_attribute 68, 1
530
531; CORTEX-A5-NONEON-FAST-NOT:   .eabi_attribute 19
532;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
533;; is given.
534; CORTEX-A5-NONEON-FAST:        .eabi_attribute 20, 2
535; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 21
536; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 22
537; CORTEX-A5-NONEON-FAST: .eabi_attribute 23, 1
538
539; CORTEX-A5-NOFPU:        .cpu    cortex-a5
540; CORTEX-A5-NOFPU:        .eabi_attribute 6, 10
541; CORTEX-A5-NOFPU:        .eabi_attribute 7, 65
542; CORTEX-A5-NOFPU:        .eabi_attribute 8, 1
543; CORTEX-A5-NOFPU:        .eabi_attribute 9, 2
544; CORTEX-A5-NOFPU-NOT:    .fpu
545; CORTEX-A5-NOFPU-NOT:   .eabi_attribute 19
546;; We default to IEEE 754 compliance
547; CORTEX-A5-NOFPU:        .eabi_attribute 20, 1
548; CORTEX-A5-NOFPU:        .eabi_attribute 21, 1
549; CORTEX-A5-NOFPU-NOT:    .eabi_attribute 22
550; CORTEX-A5-NOFPU:        .eabi_attribute 23, 3
551; CORTEX-A5-NOFPU:        .eabi_attribute 24, 1
552; CORTEX-A5-NOFPU:        .eabi_attribute 25, 1
553; CORTEX-A5-NOFPU:        .eabi_attribute 42, 1
554; CORTEX-A5-NOFPU:        .eabi_attribute 68, 1
555
556; CORTEX-A5-NOFPU-FAST-NOT:   .eabi_attribute 19
557;; Despite there being no FPU, we chose to flush to zero preserving
558;; sign. This matches what the hardware would do for this architecture
559;; revision.
560; CORTEX-A5-NOFPU-FAST: .eabi_attribute 20, 2
561; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 21
562; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 22
563; CORTEX-A5-NOFPU-FAST: .eabi_attribute 23, 1
564
565; CORTEX-A9-SOFT:  .cpu cortex-a9
566; CORTEX-A9-SOFT:  .eabi_attribute 6, 10
567; CORTEX-A9-SOFT:  .eabi_attribute 7, 65
568; CORTEX-A9-SOFT:  .eabi_attribute 8, 1
569; CORTEX-A9-SOFT:  .eabi_attribute 9, 2
570; CORTEX-A9-SOFT:  .fpu neon
571; CORTEX-A9-SOFT-NOT:   .eabi_attribute 19
572;; We default to IEEE 754 compliance
573; CORTEX-A9-SOFT:  .eabi_attribute 20, 1
574; CORTEX-A9-SOFT:  .eabi_attribute 21, 1
575; CORTEX-A9-SOFT-NOT:  .eabi_attribute 22
576; CORTEX-A9-SOFT:  .eabi_attribute 23, 3
577; CORTEX-A9-SOFT:  .eabi_attribute 24, 1
578; CORTEX-A9-SOFT:  .eabi_attribute 25, 1
579; CORTEX-A9-SOFT-NOT:  .eabi_attribute 27
580; CORTEX-A9-SOFT-NOT:  .eabi_attribute 28
581; CORTEX-A9-SOFT:  .eabi_attribute 36, 1
582; CORTEX-A9-SOFT:  .eabi_attribute 38, 1
583; CORTEX-A9-SOFT:  .eabi_attribute 42, 1
584; CORTEX-A9-SOFT-NOT:  .eabi_attribute 44
585; CORTEX-A9-SOFT:  .eabi_attribute 68, 1
586
587; CORTEX-A9-SOFT-FAST-NOT:   .eabi_attribute 19
588;; The A9 defaults to a VFPv3 FPU, so it flushes preseving sign when
589;; -ffast-math is specified.
590; CORTEX-A9-SOFT-FAST:  .eabi_attribute 20, 2
591; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 21
592; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 22
593; CORTEX-A5-SOFT-FAST: .eabi_attribute 23, 1
594
595; CORTEX-A9-HARD:  .cpu cortex-a9
596; CORTEX-A9-HARD:  .eabi_attribute 6, 10
597; CORTEX-A9-HARD:  .eabi_attribute 7, 65
598; CORTEX-A9-HARD:  .eabi_attribute 8, 1
599; CORTEX-A9-HARD:  .eabi_attribute 9, 2
600; CORTEX-A9-HARD:  .fpu neon
601; CORTEX-A9-HARD-NOT:   .eabi_attribute 19
602;; We default to IEEE 754 compliance
603; CORTEX-A9-HARD:  .eabi_attribute 20, 1
604; CORTEX-A9-HARD:  .eabi_attribute 21, 1
605; CORTEX-A9-HARD-NOT:  .eabi_attribute 22
606; CORTEX-A9-HARD:  .eabi_attribute 23, 3
607; CORTEX-A9-HARD:  .eabi_attribute 24, 1
608; CORTEX-A9-HARD:  .eabi_attribute 25, 1
609; CORTEX-A9-HARD-NOT:  .eabi_attribute 27
610; CORTEX-A9-HARD:  .eabi_attribute 28, 1
611; CORTEX-A9-HARD:  .eabi_attribute 36, 1
612; CORTEX-A9-HARD:  .eabi_attribute 38, 1
613; CORTEX-A9-HARD:  .eabi_attribute 42, 1
614; CORTEX-A9-HARD:  .eabi_attribute 68, 1
615
616; CORTEX-A9-HARD-FAST-NOT:   .eabi_attribute 19
617;; The A9 defaults to a VFPv3 FPU, so it flushes preseving sign when
618;; -ffast-math is specified.
619; CORTEX-A9-HARD-FAST:  .eabi_attribute 20, 2
620; CORTEX-A9-HARD-FAST-NOT:  .eabi_attribute 21
621; CORTEX-A9-HARD-FAST-NOT:  .eabi_attribute 22
622; CORTEX-A9-HARD-FAST:  .eabi_attribute 23, 1
623
624; CORTEX-A12-DEFAULT:  .cpu cortex-a12
625; CORTEX-A12-DEFAULT:  .eabi_attribute 6, 10
626; CORTEX-A12-DEFAULT:  .eabi_attribute 7, 65
627; CORTEX-A12-DEFAULT:  .eabi_attribute 8, 1
628; CORTEX-A12-DEFAULT:  .eabi_attribute 9, 2
629; CORTEX-A12-DEFAULT:  .fpu neon-vfpv4
630; CORTEX-A12-DEFAULT-NOT:   .eabi_attribute 19
631;; We default to IEEE 754 compliance
632; CORTEX-A12-DEFAULT:  .eabi_attribute 20, 1
633; CORTEX-A12-DEFAULT:  .eabi_attribute 21, 1
634; CORTEX-A12-DEFAULT-NOT:  .eabi_attribute 22
635; CORTEX-A12-DEFAULT:  .eabi_attribute 23, 3
636; CORTEX-A12-DEFAULT:  .eabi_attribute 24, 1
637; CORTEX-A12-DEFAULT:  .eabi_attribute 25, 1
638; CORTEX-A12-DEFAULT:  .eabi_attribute 42, 1
639; CORTEX-A12-DEFAULT:  .eabi_attribute 44, 2
640; CORTEX-A12-DEFAULT:  .eabi_attribute 68, 3
641
642; CORTEX-A12-DEFAULT-FAST-NOT:   .eabi_attribute 19
643;; The A12 defaults to a VFPv3 FPU, so it flushes preseving sign when
644;; -ffast-math is specified.
645; CORTEX-A12-DEFAULT-FAST:  .eabi_attribute 20, 2
646; CORTEX-A12-HARD-FAST-NOT:  .eabi_attribute 21
647; CORTEX-A12-HARD-FAST-NOT:  .eabi_attribute 22
648; CORTEX-A12-HARD-FAST:  .eabi_attribute 23, 1
649
650; CORTEX-A12-NOFPU:  .cpu cortex-a12
651; CORTEX-A12-NOFPU:  .eabi_attribute 6, 10
652; CORTEX-A12-NOFPU:  .eabi_attribute 7, 65
653; CORTEX-A12-NOFPU:  .eabi_attribute 8, 1
654; CORTEX-A12-NOFPU:  .eabi_attribute 9, 2
655; CORTEX-A12-NOFPU-NOT:  .fpu
656; CORTEX-A12-NOFPU-NOT:   .eabi_attribute 19
657;; We default to IEEE 754 compliance
658; CORTEX-A12-NOFPU:  .eabi_attribute 20, 1
659; CORTEX-A12-NOFPU:  .eabi_attribute 21, 1
660; CORTEX-A12-NOFPU-NOT:  .eabi_attribute 22
661; CORTEX-A12-NOFPU:  .eabi_attribute 23, 3
662; CORTEX-A12-NOFPU:  .eabi_attribute 24, 1
663; CORTEX-A12-NOFPU:  .eabi_attribute 25, 1
664; CORTEX-A12-NOFPU:  .eabi_attribute 42, 1
665; CORTEX-A12-NOFPU:  .eabi_attribute 44, 2
666; CORTEX-A12-NOFPU:  .eabi_attribute 68, 3
667
668; CORTEX-A12-NOFPU-FAST-NOT:   .eabi_attribute 19
669;; Despite there being no FPU, we chose to flush to zero preserving
670;; sign. This matches what the hardware would do for this architecture
671;; revision.
672; CORTEX-A12-NOFPU-FAST:  .eabi_attribute 20, 2
673; CORTEX-A12-NOFPU-FAST-NOT:  .eabi_attribute 21
674; CORTEX-A12-NOFPU-FAST-NOT:  .eabi_attribute 22
675; CORTEX-A12-NOFPU-FAST:  .eabi_attribute 23, 1
676
677; CORTEX-A15: .cpu cortex-a15
678; CORTEX-A15: .eabi_attribute 6, 10
679; CORTEX-A15: .eabi_attribute 7, 65
680; CORTEX-A15: .eabi_attribute 8, 1
681; CORTEX-A15: .eabi_attribute 9, 2
682; CORTEX-A15: .fpu neon-vfpv4
683; CORTEX-A15-NOT:   .eabi_attribute 19
684;; We default to IEEE 754 compliance
685; CORTEX-A15: .eabi_attribute 20, 1
686; CORTEX-A15: .eabi_attribute 21, 1
687; CORTEX-A15-NOT: .eabi_attribute 22
688; CORTEX-A15: .eabi_attribute 23, 3
689; CORTEX-A15: .eabi_attribute 24, 1
690; CORTEX-A15: .eabi_attribute 25, 1
691; CORTEX-A15-NOT: .eabi_attribute 27
692; CORTEX-A15-NOT: .eabi_attribute 28
693; CORTEX-A15: .eabi_attribute 36, 1
694; CORTEX-A15: .eabi_attribute 38, 1
695; CORTEX-A15: .eabi_attribute 42, 1
696; CORTEX-A15: .eabi_attribute 44, 2
697; CORTEX-A15: .eabi_attribute 68, 3
698
699; CORTEX-A15-FAST-NOT:   .eabi_attribute 19
700;; The A15 defaults to a VFPv3 FPU, so it flushes preseving sign when
701;; -ffast-math is specified.
702; CORTEX-A15-FAST: .eabi_attribute 20, 2
703; CORTEX-A15-FAST-NOT:  .eabi_attribute 21
704; CORTEX-A15-FAST-NOT:  .eabi_attribute 22
705; CORTEX-A15-FAST:  .eabi_attribute 23, 1
706
707; CORTEX-A17-DEFAULT:  .cpu cortex-a17
708; CORTEX-A17-DEFAULT:  .eabi_attribute 6, 10
709; CORTEX-A17-DEFAULT:  .eabi_attribute 7, 65
710; CORTEX-A17-DEFAULT:  .eabi_attribute 8, 1
711; CORTEX-A17-DEFAULT:  .eabi_attribute 9, 2
712; CORTEX-A17-DEFAULT:  .fpu neon-vfpv4
713; CORTEX-A17-DEFAULT-NOT:   .eabi_attribute 19
714;; We default to IEEE 754 compliance
715; CORTEX-A17-DEFAULT:  .eabi_attribute 20, 1
716; CORTEX-A17-DEFAULT:  .eabi_attribute 21, 1
717; CORTEX-A17-DEFAULT-NOT:  .eabi_attribute 22
718; CORTEX-A17-DEFAULT:  .eabi_attribute 23, 3
719; CORTEX-A17-DEFAULT:  .eabi_attribute 24, 1
720; CORTEX-A17-DEFAULT:  .eabi_attribute 25, 1
721; CORTEX-A17-DEFAULT:  .eabi_attribute 42, 1
722; CORTEX-A17-DEFAULT:  .eabi_attribute 44, 2
723; CORTEX-A17-DEFAULT:  .eabi_attribute 68, 3
724
725; CORTEX-A17-FAST-NOT:   .eabi_attribute 19
726;; The A17 defaults to a VFPv3 FPU, so it flushes preseving sign when
727;; -ffast-math is specified.
728; CORTEX-A17-FAST:  .eabi_attribute 20, 2
729; CORTEX-A17-FAST-NOT:  .eabi_attribute 21
730; CORTEX-A17-FAST-NOT:  .eabi_attribute 22
731; CORTEX-A17-FAST:  .eabi_attribute 23, 1
732
733; CORTEX-A17-NOFPU:  .cpu cortex-a17
734; CORTEX-A17-NOFPU:  .eabi_attribute 6, 10
735; CORTEX-A17-NOFPU:  .eabi_attribute 7, 65
736; CORTEX-A17-NOFPU:  .eabi_attribute 8, 1
737; CORTEX-A17-NOFPU:  .eabi_attribute 9, 2
738; CORTEX-A17-NOFPU-NOT:  .fpu
739; CORTEX-A17-NOFPU-NOT:   .eabi_attribute 19
740;; We default to IEEE 754 compliance
741; CORTEX-A17-NOFPU:  .eabi_attribute 20, 1
742; CORTEX-A17-NOFPU:  .eabi_attribute 21, 1
743; CORTEX-A17-NOFPU-NOT:  .eabi_attribute 22
744; CORTEX-A17-NOFPU:  .eabi_attribute 23, 3
745; CORTEX-A17-NOFPU:  .eabi_attribute 24, 1
746; CORTEX-A17-NOFPU:  .eabi_attribute 25, 1
747; CORTEX-A17-NOFPU:  .eabi_attribute 42, 1
748; CORTEX-A17-NOFPU:  .eabi_attribute 44, 2
749; CORTEX-A17-NOFPU:  .eabi_attribute 68, 3
750
751; CORTEX-A17-NOFPU-NOT:   .eabi_attribute 19
752;; Despite there being no FPU, we chose to flush to zero preserving
753;; sign. This matches what the hardware would do for this architecture
754;; revision.
755; CORTEX-A17-NOFPU-FAST:  .eabi_attribute 20, 2
756; CORTEX-A17-NOFPU-FAST-NOT:  .eabi_attribute 21
757; CORTEX-A17-NOFPU-FAST-NOT:  .eabi_attribute 22
758; CORTEX-A17-NOFPU-FAST:  .eabi_attribute 23, 1
759
760; CORTEX-M0:  .cpu cortex-m0
761; CORTEX-M0:  .eabi_attribute 6, 12
762; CORTEX-M0-NOT:  .eabi_attribute 7
763; CORTEX-M0:  .eabi_attribute 8, 0
764; CORTEX-M0:  .eabi_attribute 9, 1
765; CORTEX-M0-NOT:   .eabi_attribute 19
766;; We default to IEEE 754 compliance
767; CORTEX-M0:  .eabi_attribute 20, 1
768; CORTEX-M0:  .eabi_attribute 21, 1
769; CORTEX-M0-NOT:  .eabi_attribute 22
770; CORTEX-M0:  .eabi_attribute 23, 3
771; CORTEX-M0: .eabi_attribute 34, 0
772; CORTEX-M0:  .eabi_attribute 24, 1
773; CORTEX-M0:  .eabi_attribute 25, 1
774; CORTEX-M0-NOT:  .eabi_attribute 27
775; CORTEX-M0-NOT:  .eabi_attribute 28
776; CORTEX-M0-NOT:  .eabi_attribute 36
777; CORTEX-M0:  .eabi_attribute 38, 1
778; CORTEX-M0-NOT:  .eabi_attribute 42
779; CORTEX-M0-NOT:  .eabi_attribute 44
780; CORTEX-M0-NOT:  .eabi_attribute 68
781
782; CORTEX-M0-FAST-NOT:   .eabi_attribute 19
783;; Despite the M0 CPU having no FPU in this scenario, we chose to
784;; flush to positive zero here. There's no hardware support doing
785;; this, but the fast maths software library might and such behaviour
786;; would match hardware support on this architecture revision if it
787;; existed.
788; CORTEX-M0-FAST-NOT:  .eabi_attribute 20
789; CORTEX-M0-FAST-NOT:  .eabi_attribute 21
790; CORTEX-M0-FAST-NOT:  .eabi_attribute 22
791; CORTEX-M0-FAST:  .eabi_attribute 23, 1
792
793; CORTEX-M0PLUS:  .cpu cortex-m0plus
794; CORTEX-M0PLUS:  .eabi_attribute 6, 12
795; CORTEX-M0PLUS-NOT:  .eabi_attribute 7
796; CORTEX-M0PLUS:  .eabi_attribute 8, 0
797; CORTEX-M0PLUS:  .eabi_attribute 9, 1
798; CORTEX-M0PLUS-NOT:   .eabi_attribute 19
799;; We default to IEEE 754 compliance
800; CORTEX-M0PLUS:  .eabi_attribute 20, 1
801; CORTEX-M0PLUS:  .eabi_attribute 21, 1
802; CORTEX-M0PLUS-NOT:  .eabi_attribute 22
803; CORTEX-M0PLUS:  .eabi_attribute 23, 3
804; CORTEX-M0PLUS:  .eabi_attribute 24, 1
805; CORTEX-M0PLUS:  .eabi_attribute 25, 1
806; CORTEX-M0PLUS-NOT:  .eabi_attribute 27
807; CORTEX-M0PLUS-NOT:  .eabi_attribute 28
808; CORTEX-M0PLUS-NOT:  .eabi_attribute 36
809; CORTEX-M0PLUS:  .eabi_attribute 38, 1
810; CORTEX-M0PLUS-NOT:  .eabi_attribute 42
811; CORTEX-M0PLUS-NOT:  .eabi_attribute 44
812; CORTEX-M0PLUS-NOT:  .eabi_attribute 68
813
814; CORTEX-M0PLUS-FAST-NOT:   .eabi_attribute 19
815;; Despite the M0+ CPU having no FPU in this scenario, we chose to
816;; flush to positive zero here. There's no hardware support doing
817;; this, but the fast maths software library might and such behaviour
818;; would match hardware support on this architecture revision if it
819;; existed.
820; CORTEX-M0PLUS-FAST-NOT:  .eabi_attribute 20
821; CORTEX-M0PLUS-FAST-NOT:  .eabi_attribute 21
822; CORTEX-M0PLUS-FAST-NOT:  .eabi_attribute 22
823; CORTEX-M0PLUS-FAST:  .eabi_attribute 23, 1
824
825; CORTEX-M1:  .cpu cortex-m1
826; CORTEX-M1:  .eabi_attribute 6, 12
827; CORTEX-M1-NOT:  .eabi_attribute 7
828; CORTEX-M1:  .eabi_attribute 8, 0
829; CORTEX-M1:  .eabi_attribute 9, 1
830; CORTEX-M1-NOT:   .eabi_attribute 19
831;; We default to IEEE 754 compliance
832; CORTEX-M1:  .eabi_attribute 20, 1
833; CORTEX-M1:  .eabi_attribute 21, 1
834; CORTEX-M1-NOT:  .eabi_attribute 22
835; CORTEX-M1:  .eabi_attribute 23, 3
836; CORTEX-M1:  .eabi_attribute 24, 1
837; CORTEX-M1:  .eabi_attribute 25, 1
838; CORTEX-M1-NOT:  .eabi_attribute 27
839; CORTEX-M1-NOT:  .eabi_attribute 28
840; CORTEX-M1-NOT:  .eabi_attribute 36
841; CORTEX-M1:  .eabi_attribute 38, 1
842; CORTEX-M1-NOT:  .eabi_attribute 42
843; CORTEX-M1-NOT:  .eabi_attribute 44
844; CORTEX-M1-NOT:  .eabi_attribute 68
845
846; CORTEX-M1-FAST-NOT:   .eabi_attribute 19
847;; Despite the M1 CPU having no FPU in this scenario, we chose to
848;; flush to positive zero here. There's no hardware support doing
849;; this, but the fast maths software library might and such behaviour
850;; would match hardware support on this architecture revision if it
851;; existed.
852; CORTEX-M1-FAST-NOT:  .eabi_attribute 20
853; CORTEX-M1-FAST-NOT:  .eabi_attribute 21
854; CORTEX-M1-FAST-NOT:  .eabi_attribute 22
855; CORTEX-M1-FAST:  .eabi_attribute 23, 1
856
857; SC000:  .cpu sc000
858; SC000:  .eabi_attribute 6, 12
859; SC000-NOT:  .eabi_attribute 7
860; SC000:  .eabi_attribute 8, 0
861; SC000:  .eabi_attribute 9, 1
862; SC000-NOT:   .eabi_attribute 19
863;; We default to IEEE 754 compliance
864; SC000:  .eabi_attribute 20, 1
865; SC000:  .eabi_attribute 21, 1
866; SC000-NOT:  .eabi_attribute 22
867; SC000:  .eabi_attribute 23, 3
868; SC000:  .eabi_attribute 24, 1
869; SC000:  .eabi_attribute 25, 1
870; SC000-NOT:  .eabi_attribute 27
871; SC000-NOT:  .eabi_attribute 28
872; SC000-NOT:  .eabi_attribute 36
873; SC000:  .eabi_attribute 38, 1
874; SC000-NOT:  .eabi_attribute 42
875; SC000-NOT:  .eabi_attribute 44
876; SC000-NOT:  .eabi_attribute 68
877
878; SC000-FAST-NOT:   .eabi_attribute 19
879;; Despite the SC000 CPU having no FPU in this scenario, we chose to
880;; flush to positive zero here. There's no hardware support doing
881;; this, but the fast maths software library might and such behaviour
882;; would match hardware support on this architecture revision if it
883;; existed.
884; SC000-FAST-NOT:  .eabi_attribute 20
885; SC000-FAST-NOT:  .eabi_attribute 21
886; SC000-FAST-NOT:  .eabi_attribute 22
887; SC000-FAST:  .eabi_attribute 23, 1
888
889; CORTEX-M3:  .cpu cortex-m3
890; CORTEX-M3:  .eabi_attribute 6, 10
891; CORTEX-M3:  .eabi_attribute 7, 77
892; CORTEX-M3:  .eabi_attribute 8, 0
893; CORTEX-M3:  .eabi_attribute 9, 2
894; CORTEX-M3-NOT:   .eabi_attribute 19
895;; We default to IEEE 754 compliance
896; CORTEX-M3:  .eabi_attribute 20, 1
897; CORTEX-M3:  .eabi_attribute 21, 1
898; CORTEX-M3-NOT:  .eabi_attribute 22
899; CORTEX-M3:  .eabi_attribute 23, 3
900; CORTEX-M3:  .eabi_attribute 24, 1
901; CORTEX-M3:  .eabi_attribute 25, 1
902; CORTEX-M3-NOT:  .eabi_attribute 27
903; CORTEX-M3-NOT:  .eabi_attribute 28
904; CORTEX-M3-NOT:  .eabi_attribute 36
905; CORTEX-M3:  .eabi_attribute 38, 1
906; CORTEX-M3-NOT:  .eabi_attribute 42
907; CORTEX-M3-NOT:  .eabi_attribute 44
908; CORTEX-M3-NOT:  .eabi_attribute 68
909
910; CORTEX-M3-FAST-NOT:   .eabi_attribute 19
911;; Despite there being no FPU, we chose to flush to zero preserving
912;; sign. This matches what the hardware would do for this architecture
913;; revision.
914; CORTEX-M3-FAST:  .eabi_attribute 20, 2
915; CORTEX-M3-FAST-NOT:  .eabi_attribute 21
916; CORTEX-M3-FAST-NOT:  .eabi_attribute 22
917; CORTEX-M3-FAST:  .eabi_attribute 23, 1
918
919; SC300:  .cpu sc300
920; SC300:  .eabi_attribute 6, 10
921; SC300:  .eabi_attribute 7, 77
922; SC300:  .eabi_attribute 8, 0
923; SC300:  .eabi_attribute 9, 2
924; SC300-NOT:   .eabi_attribute 19
925;; We default to IEEE 754 compliance
926; SC300:  .eabi_attribute 20, 1
927; SC300:  .eabi_attribute 21, 1
928; SC300-NOT:  .eabi_attribute 22
929; SC300:  .eabi_attribute 23, 3
930; SC300:  .eabi_attribute 24, 1
931; SC300:  .eabi_attribute 25, 1
932; SC300-NOT:  .eabi_attribute 27
933; SC300-NOT:  .eabi_attribute 28
934; SC300-NOT:  .eabi_attribute 36
935; SC300:  .eabi_attribute 38, 1
936; SC300-NOT:  .eabi_attribute 42
937; SC300-NOT:  .eabi_attribute 44
938; SC300-NOT:  .eabi_attribute 68
939
940; SC300-FAST-NOT:   .eabi_attribute 19
941;; Despite there being no FPU, we chose to flush to zero preserving
942;; sign. This matches what the hardware would do for this architecture
943;; revision.
944; SC300-FAST:  .eabi_attribute 20, 2
945; SC300-FAST-NOT:  .eabi_attribute 21
946; SC300-FAST-NOT:  .eabi_attribute 22
947; SC300-FAST:  .eabi_attribute 23, 1
948
949; CORTEX-M4-SOFT:  .cpu cortex-m4
950; CORTEX-M4-SOFT:  .eabi_attribute 6, 13
951; CORTEX-M4-SOFT:  .eabi_attribute 7, 77
952; CORTEX-M4-SOFT:  .eabi_attribute 8, 0
953; CORTEX-M4-SOFT:  .eabi_attribute 9, 2
954; CORTEX-M4-SOFT:  .fpu fpv4-sp-d16
955; CORTEX-M4-SOFT-NOT:   .eabi_attribute 19
956;; We default to IEEE 754 compliance
957; CORTEX-M4-SOFT:  .eabi_attribute 20, 1
958; CORTEX-M4-SOFT:  .eabi_attribute 21, 1
959; CORTEX-M4-SOFT-NOT:  .eabi_attribute 22
960; CORTEX-M4-SOFT:  .eabi_attribute 23, 3
961; CORTEX-M4-SOFT:  .eabi_attribute 24, 1
962; CORTEX-M4-SOFT:  .eabi_attribute 25, 1
963; CORTEX-M4-SOFT:  .eabi_attribute 27, 1
964; CORTEX-M4-SOFT-NOT:  .eabi_attribute 28
965; CORTEX-M4-SOFT:  .eabi_attribute 36, 1
966; CORTEX-M4-SOFT:  .eabi_attribute 38, 1
967; CORTEX-M4-SOFT-NOT:  .eabi_attribute 42
968; CORTEX-M4-SOFT-NOT:  .eabi_attribute 44
969; CORTEX-M4-SOFT-NOT:  .eabi_attribute 68
970
971; CORTEX-M4-SOFT-FAST-NOT:   .eabi_attribute 19
972;; The M4 defaults to a VFPv4 FPU, so it flushes preseving sign when
973;; -ffast-math is specified.
974; CORTEX-M4-SOFT-FAST:  .eabi_attribute 20, 2
975; CORTEX-M4-SOFT-FAST-NOT:  .eabi_attribute 21
976; CORTEX-M4-SOFT-FAST-NOT:  .eabi_attribute 22
977; CORTEX-M4-SOFT-FAST:  .eabi_attribute 23, 1
978
979; CORTEX-M4-HARD:  .cpu cortex-m4
980; CORTEX-M4-HARD:  .eabi_attribute 6, 13
981; CORTEX-M4-HARD:  .eabi_attribute 7, 77
982; CORTEX-M4-HARD:  .eabi_attribute 8, 0
983; CORTEX-M4-HARD:  .eabi_attribute 9, 2
984; CORTEX-M4-HARD:  .fpu fpv4-sp-d16
985; CORTEX-M4-HARD-NOT:   .eabi_attribute 19
986;; We default to IEEE 754 compliance
987; CORTEX-M4-HARD:  .eabi_attribute 20, 1
988; CORTEX-M4-HARD:  .eabi_attribute 21, 1
989; CORTEX-M4-HARD-NOT:  .eabi_attribute 22
990; CORTEX-M4-HARD:  .eabi_attribute 23, 3
991; CORTEX-M4-HARD:  .eabi_attribute 24, 1
992; CORTEX-M4-HARD:  .eabi_attribute 25, 1
993; CORTEX-M4-HARD:  .eabi_attribute 27, 1
994; CORTEX-M4-HARD:  .eabi_attribute 28, 1
995; CORTEX-M4-HARD:  .eabi_attribute 36, 1
996; CORTEX-M4-HARD:  .eabi_attribute 38, 1
997; CORTEX-M4-HARD-NOT:  .eabi_attribute 42
998; CORTEX-M4-HARD-NOT:  .eabi_attribute 44
999; CORTEX-M4-HARD-NOT:  .eabi_attribute 68
1000
1001; CORTEX-M4-HARD-FAST-NOT:   .eabi_attribute 19
1002;; The M4 defaults to a VFPv4 FPU, so it flushes preseving sign when
1003;; -ffast-math is specified.
1004; CORTEX-M4-HARD-FAST:  .eabi_attribute 20, 2
1005; CORTEX-M4-HARD-FAST-NOT:  .eabi_attribute 21
1006; CORTEX-M4-HARD-FAST-NOT:  .eabi_attribute 22
1007; CORTEX-M4-HARD-FAST:  .eabi_attribute 23, 1
1008
1009; CORTEX-M7:  .cpu    cortex-m7
1010; CORTEX-M7:  .eabi_attribute 6, 13
1011; CORTEX-M7:  .eabi_attribute 7, 77
1012; CORTEX-M7:  .eabi_attribute 8, 0
1013; CORTEX-M7:  .eabi_attribute 9, 2
1014; CORTEX-M7-SOFT-NOT: .fpu
1015; CORTEX-M7-SINGLE:  .fpu fpv5-sp-d16
1016; CORTEX-M7-DOUBLE:  .fpu fpv5-d16
1017; CORTEX-M7:  .eabi_attribute 17, 1
1018; CORTEX-M7-NOT:   .eabi_attribute 19
1019;; We default to IEEE 754 compliance
1020; CORTEX-M7:  .eabi_attribute 20, 1
1021; CORTEX-M7:  .eabi_attribute 21, 1
1022; CORTEX-M7-NOT:  .eabi_attribute 22
1023; CORTEX-M7:  .eabi_attribute 23, 3
1024; CORTEX-M7:  .eabi_attribute 24, 1
1025; CORTEX-M7:  .eabi_attribute 25, 1
1026; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
1027; CORTEX-M7-SINGLE:  .eabi_attribute 27, 1
1028; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
1029; CORTEX-M7:  .eabi_attribute 36, 1
1030; CORTEX-M7:  .eabi_attribute 38, 1
1031; CORTEX-M7-NOT:  .eabi_attribute 44
1032; CORTEX-M7:  .eabi_attribute 14, 0
1033
1034; CORTEX-M7-NOFPU-FAST-NOT:   .eabi_attribute 19
1035;; The M7 has the ARMv8 FP unit, which always flushes preserving sign.
1036; CORTEX-M7-FAST:  .eabi_attribute 20, 2
1037;; Despite there being no FPU, we chose to flush to zero preserving
1038;; sign. This matches what the hardware would do for this architecture
1039;; revision.
1040; CORTEX-M7-NOFPU-FAST: .eabi_attribute 20, 2
1041; CORTEX-M7-NOFPU-FAST-NOT:  .eabi_attribute 21
1042; CORTEX-M7-NOFPU-FAST-NOT:  .eabi_attribute 22
1043; CORTEX-M7-NOFPU-FAST:  .eabi_attribute 23, 1
1044
1045; CORTEX-R4:  .cpu cortex-r4
1046; CORTEX-R4:  .eabi_attribute 6, 10
1047; CORTEX-R4:  .eabi_attribute 7, 82
1048; CORTEX-R4:  .eabi_attribute 8, 1
1049; CORTEX-R4:  .eabi_attribute 9, 2
1050; CORTEX-R4-NOT:  .fpu vfpv3-d16
1051; CORTEX-R4-NOT:   .eabi_attribute 19
1052;; We default to IEEE 754 compliance
1053; CORTEX-R4:  .eabi_attribute 20, 1
1054; CORTEX-R4:  .eabi_attribute 21, 1
1055; CORTEX-R4-NOT:  .eabi_attribute 22
1056; CORTEX-R4:  .eabi_attribute 23, 3
1057; CORTEX-R4:  .eabi_attribute 24, 1
1058; CORTEX-R4:  .eabi_attribute 25, 1
1059; CORTEX-R4-NOT:  .eabi_attribute 28
1060; CORTEX-R4-NOT:  .eabi_attribute 36
1061; CORTEX-R4:  .eabi_attribute 38, 1
1062; CORTEX-R4-NOT:  .eabi_attribute 42
1063; CORTEX-R4-NOT:  .eabi_attribute 44
1064; CORTEX-R4-NOT:  .eabi_attribute 68
1065
1066; CORTEX-R4F:  .cpu cortex-r4f
1067; CORTEX-R4F:  .eabi_attribute 6, 10
1068; CORTEX-R4F:  .eabi_attribute 7, 82
1069; CORTEX-R4F:  .eabi_attribute 8, 1
1070; CORTEX-R4F:  .eabi_attribute 9, 2
1071; CORTEX-R4F:  .fpu vfpv3-d16
1072; CORTEX-R4F-NOT:   .eabi_attribute 19
1073;; We default to IEEE 754 compliance
1074; CORTEX-R4F:  .eabi_attribute 20, 1
1075; CORTEX-R4F:  .eabi_attribute 21, 1
1076; CORTEX-R4F-NOT:  .eabi_attribute 22
1077; CORTEX-R4F:  .eabi_attribute 23, 3
1078; CORTEX-R4F:  .eabi_attribute 24, 1
1079; CORTEX-R4F:  .eabi_attribute 25, 1
1080; CORTEX-R4F-NOT:  .eabi_attribute 27, 1
1081; CORTEX-R4F-NOT:  .eabi_attribute 28
1082; CORTEX-R4F-NOT:  .eabi_attribute 36
1083; CORTEX-R4F:  .eabi_attribute 38, 1
1084; CORTEX-R4F-NOT:  .eabi_attribute 42
1085; CORTEX-R4F-NOT:  .eabi_attribute 44
1086; CORTEX-R4F-NOT:  .eabi_attribute 68
1087
1088; CORTEX-R5:  .cpu cortex-r5
1089; CORTEX-R5:  .eabi_attribute 6, 10
1090; CORTEX-R5:  .eabi_attribute 7, 82
1091; CORTEX-R5:  .eabi_attribute 8, 1
1092; CORTEX-R5:  .eabi_attribute 9, 2
1093; CORTEX-R5:  .fpu vfpv3-d16
1094; CORTEX-R5-NOT:   .eabi_attribute 19
1095;; We default to IEEE 754 compliance
1096; CORTEX-R5:  .eabi_attribute 20, 1
1097; CORTEX-R5:  .eabi_attribute 21, 1
1098; CORTEX-R5-NOT:  .eabi_attribute 22
1099; CORTEX-R5:  .eabi_attribute 23, 3
1100; CORTEX-R5:  .eabi_attribute 24, 1
1101; CORTEX-R5:  .eabi_attribute 25, 1
1102; CORTEX-R5-NOT:  .eabi_attribute 27, 1
1103; CORTEX-R5-NOT:  .eabi_attribute 28
1104; CORTEX-R5-NOT:  .eabi_attribute 36
1105; CORTEX-R5:  .eabi_attribute 38, 1
1106; CORTEX-R5-NOT:  .eabi_attribute 42
1107; CORTEX-R5:  .eabi_attribute 44, 2
1108; CORTEX-R5-NOT:  .eabi_attribute 68
1109
1110; CORTEX-R5-FAST-NOT:   .eabi_attribute 19
1111;; The R5 has the VFPv3 FP unit, which always flushes preserving sign.
1112; CORTEX-R5-FAST:  .eabi_attribute 20, 2
1113; CORTEX-R5-FAST-NOT:  .eabi_attribute 21
1114; CORTEX-R5-FAST-NOT:  .eabi_attribute 22
1115; CORTEX-R5-FAST:  .eabi_attribute 23, 1
1116
1117; CORTEX-R7:  .cpu cortex-r7
1118; CORTEX-R7:  .eabi_attribute 6, 10
1119; CORTEX-R7:  .eabi_attribute 7, 82
1120; CORTEX-R7:  .eabi_attribute 8, 1
1121; CORTEX-R7:  .eabi_attribute 9, 2
1122; CORTEX-R7:  .fpu vfpv3xd
1123; CORTEX-R7-NOT:   .eabi_attribute 19
1124;; We default to IEEE 754 compliance
1125; CORTEX-R7:  .eabi_attribute 20, 1
1126; CORTEX-R7:  .eabi_attribute 21, 1
1127; CORTEX-R7-NOT:  .eabi_attribute 22
1128; CORTEX-R7:  .eabi_attribute 23, 3
1129; CORTEX-R7:  .eabi_attribute 24, 1
1130; CORTEX-R7:  .eabi_attribute 25, 1
1131; CORTEX-R7:  .eabi_attribute 27, 1
1132; CORTEX-R7-NOT:  .eabi_attribute 28
1133; CORTEX-R7:  .eabi_attribute 36, 1
1134; CORTEX-R7:  .eabi_attribute 38, 1
1135; CORTEX-R7:  .eabi_attribute 42, 1
1136; CORTEX-R7:  .eabi_attribute 44, 2
1137; CORTEX-R7-NOT:  .eabi_attribute 68
1138
1139; CORTEX-R7-FAST-NOT:   .eabi_attribute 19
1140;; The R7 has the VFPv3 FP unit, which always flushes preserving sign.
1141; CORTEX-R7-FAST:  .eabi_attribute 20, 2
1142; CORTEX-R7-FAST-NOT:  .eabi_attribute 21
1143; CORTEX-R7-FAST-NOT:  .eabi_attribute 22
1144; CORTEX-R7-FAST:  .eabi_attribute 23, 1
1145
1146; CORTEX-A35:  .cpu cortex-a35
1147; CORTEX-A35:  .eabi_attribute 6, 14
1148; CORTEX-A35:  .eabi_attribute 7, 65
1149; CORTEX-A35:  .eabi_attribute 8, 1
1150; CORTEX-A35:  .eabi_attribute 9, 2
1151; CORTEX-A35:  .fpu crypto-neon-fp-armv8
1152; CORTEX-A35:  .eabi_attribute 12, 3
1153; CORTEX-A35-NOT:   .eabi_attribute 19
1154;; We default to IEEE 754 compliance
1155; CORTEX-A35:  .eabi_attribute 20, 1
1156; CORTEX-A35:  .eabi_attribute 21, 1
1157; CORTEX-A35-NOT:  .eabi_attribute 22
1158; CORTEX-A35:  .eabi_attribute 23, 3
1159; CORTEX-A35:  .eabi_attribute 24, 1
1160; CORTEX-A35:  .eabi_attribute 25, 1
1161; CORTEX-A35-NOT:  .eabi_attribute 27
1162; CORTEX-A35-NOT:  .eabi_attribute 28
1163; CORTEX-A35:  .eabi_attribute 36, 1
1164; CORTEX-A35:  .eabi_attribute 38, 1
1165; CORTEX-A35:  .eabi_attribute 42, 1
1166; CORTEX-A35-NOT:  .eabi_attribute 44
1167; CORTEX-A35:  .eabi_attribute 68, 3
1168
1169; CORTEX-A35-FAST-NOT:   .eabi_attribute 19
1170;; The A35 has the ARMv8 FP unit, which always flushes preserving sign.
1171; CORTEX-A35-FAST:  .eabi_attribute 20, 2
1172; CORTEX-A35-FAST-NOT:  .eabi_attribute 21
1173; CORTEX-A35-FAST-NOT:  .eabi_attribute 22
1174; CORTEX-A35-FAST:  .eabi_attribute 23, 1
1175
1176; CORTEX-A53:  .cpu cortex-a53
1177; CORTEX-A53:  .eabi_attribute 6, 14
1178; CORTEX-A53:  .eabi_attribute 7, 65
1179; CORTEX-A53:  .eabi_attribute 8, 1
1180; CORTEX-A53:  .eabi_attribute 9, 2
1181; CORTEX-A53:  .fpu crypto-neon-fp-armv8
1182; CORTEX-A53:  .eabi_attribute 12, 3
1183; CORTEX-A53-NOT:   .eabi_attribute 19
1184;; We default to IEEE 754 compliance
1185; CORTEX-A53:  .eabi_attribute 20, 1
1186; CORTEX-A53:  .eabi_attribute 21, 1
1187; CORTEX-A53-NOT:  .eabi_attribute 22
1188; CORTEX-A53:  .eabi_attribute 23, 3
1189; CORTEX-A53:  .eabi_attribute 24, 1
1190; CORTEX-A53:  .eabi_attribute 25, 1
1191; CORTEX-A53-NOT:  .eabi_attribute 27
1192; CORTEX-A53-NOT:  .eabi_attribute 28
1193; CORTEX-A53:  .eabi_attribute 36, 1
1194; CORTEX-A53:  .eabi_attribute 38, 1
1195; CORTEX-A53:  .eabi_attribute 42, 1
1196; CORTEX-A53-NOT:  .eabi_attribute 44
1197; CORTEX-A53:  .eabi_attribute 68, 3
1198
1199; CORTEX-A53-FAST-NOT:   .eabi_attribute 19
1200;; The A53 has the ARMv8 FP unit, which always flushes preserving sign.
1201; CORTEX-A53-FAST:  .eabi_attribute 20, 2
1202; CORTEX-A53-FAST-NOT:  .eabi_attribute 21
1203; CORTEX-A53-FAST-NOT:  .eabi_attribute 22
1204; CORTEX-A53-FAST:  .eabi_attribute 23, 1
1205
1206; CORTEX-A57:  .cpu cortex-a57
1207; CORTEX-A57:  .eabi_attribute 6, 14
1208; CORTEX-A57:  .eabi_attribute 7, 65
1209; CORTEX-A57:  .eabi_attribute 8, 1
1210; CORTEX-A57:  .eabi_attribute 9, 2
1211; CORTEX-A57:  .fpu crypto-neon-fp-armv8
1212; CORTEX-A57:  .eabi_attribute 12, 3
1213; CORTEX-A57-NOT:   .eabi_attribute 19
1214;; We default to IEEE 754 compliance
1215; CORTEX-A57:  .eabi_attribute 20, 1
1216; CORTEX-A57:  .eabi_attribute 21, 1
1217; CORTEX-A57-NOT:  .eabi_attribute 22
1218; CORTEX-A57:  .eabi_attribute 23, 3
1219; CORTEX-A57:  .eabi_attribute 24, 1
1220; CORTEX-A57:  .eabi_attribute 25, 1
1221; CORTEX-A57-NOT:  .eabi_attribute 27
1222; CORTEX-A57-NOT:  .eabi_attribute 28
1223; CORTEX-A57:  .eabi_attribute 36, 1
1224; CORTEX-A57:  .eabi_attribute 38, 1
1225; CORTEX-A57:  .eabi_attribute 42, 1
1226; CORTEX-A57-NOT:  .eabi_attribute 44
1227; CORTEX-A57:  .eabi_attribute 68, 3
1228
1229; CORTEX-A57-FAST-NOT:   .eabi_attribute 19
1230;; The A57 has the ARMv8 FP unit, which always flushes preserving sign.
1231; CORTEX-A57-FAST:  .eabi_attribute 20, 2
1232; CORTEX-A57-FAST-NOT:  .eabi_attribute 21
1233; CORTEX-A57-FAST-NOT:  .eabi_attribute 22
1234; CORTEX-A57-FAST:  .eabi_attribute 23, 1
1235
1236; CORTEX-A72:  .cpu cortex-a72
1237; CORTEX-A72:  .eabi_attribute 6, 14
1238; CORTEX-A72:  .eabi_attribute 7, 65
1239; CORTEX-A72:  .eabi_attribute 8, 1
1240; CORTEX-A72:  .eabi_attribute 9, 2
1241; CORTEX-A72:  .fpu crypto-neon-fp-armv8
1242; CORTEX-A72:  .eabi_attribute 12, 3
1243; CORTEX-A72-NOT:   .eabi_attribute 19
1244;; We default to IEEE 754 compliance
1245; CORTEX-A72:  .eabi_attribute 20, 1
1246; CORTEX-A72:  .eabi_attribute 21, 1
1247; CORTEX-A72-NOT:  .eabi_attribute 22
1248; CORTEX-A72:  .eabi_attribute 23, 3
1249; CORTEX-A72:  .eabi_attribute 24, 1
1250; CORTEX-A72:  .eabi_attribute 25, 1
1251; CORTEX-A72-NOT:  .eabi_attribute 27
1252; CORTEX-A72-NOT:  .eabi_attribute 28
1253; CORTEX-A72:  .eabi_attribute 36, 1
1254; CORTEX-A72:  .eabi_attribute 38, 1
1255; CORTEX-A72:  .eabi_attribute 42, 1
1256; CORTEX-A72-NOT:  .eabi_attribute 44
1257; CORTEX-A72:  .eabi_attribute 68, 3
1258
1259; CORTEX-A72-FAST-NOT:   .eabi_attribute 19
1260;; The A72 has the ARMv8 FP unit, which always flushes preserving sign.
1261; CORTEX-A72-FAST:  .eabi_attribute 20, 2
1262; CORTEX-A72-FAST-NOT:  .eabi_attribute 21
1263; CORTEX-A72-FAST-NOT:  .eabi_attribute 22
1264; CORTEX-A72-FAST:  .eabi_attribute 23, 1
1265
1266; EXYNOS-M1:  .cpu exynos-m1
1267; EXYNOS-M1:  .eabi_attribute 6, 14
1268; EXYNOS-M1:  .eabi_attribute 7, 65
1269; EXYNOS-M1:  .eabi_attribute 8, 1
1270; EXYNOS-M1:  .eabi_attribute 9, 2
1271; EXYNOS-M1:  .fpu crypto-neon-fp-armv8
1272; EXYNOS-M1:  .eabi_attribute 12, 3
1273; EXYNOS-M1-NOT:   .eabi_attribute 19
1274;; We default to IEEE 754 compliance
1275; EXYNOS-M1:  .eabi_attribute 20, 1
1276; EXYNOS-M1:  .eabi_attribute 21, 1
1277; EXYNOS-M1-NOT:  .eabi_attribute 22
1278; EXYNOS-M1:  .eabi_attribute 23, 3
1279; EXYNOS-M1:  .eabi_attribute 24, 1
1280; EXYNOS-M1:  .eabi_attribute 25, 1
1281; EXYNOS-M1-NOT:  .eabi_attribute 27
1282; EXYNOS-M1-NOT:  .eabi_attribute 28
1283; EXYNOS-M1:  .eabi_attribute 36, 1
1284; EXYNOS-M1:  .eabi_attribute 38, 1
1285; EXYNOS-M1:  .eabi_attribute 42, 1
1286; EXYNOS-M1-NOT:  .eabi_attribute 44
1287; EXYNOS-M15:  .eabi_attribute 68, 3
1288
1289; EXYNOS-M1-FAST-NOT:   .eabi_attribute 19
1290;; The exynos-m1 has the ARMv8 FP unit, which always flushes preserving sign.
1291; EXYNOS-M1-FAST:  .eabi_attribute 20, 2
1292; EXYNOS-M1-FAST-NOT:  .eabi_attribute 21
1293; EXYNOS-M1-FAST-NOT:  .eabi_attribute 22
1294; EXYNOS-M1-FAST:  .eabi_attribute 23, 1
1295
1296; GENERIC-FPU-VFPV3-FP16: .fpu vfpv3-fp16
1297; GENERIC-FPU-VFPV3-D16-FP16: .fpu vfpv3-d16-fp16
1298; GENERIC-FPU-VFPV3XD: .fpu vfpv3xd
1299; GENERIC-FPU-VFPV3XD-FP16: .fpu vfpv3xd-fp16
1300; GENERIC-FPU-NEON-FP16: .fpu neon-fp16
1301
1302; GENERIC-ARMV8_1-A:  .eabi_attribute 6, 14
1303; GENERIC-ARMV8_1-A:  .eabi_attribute 7, 65
1304; GENERIC-ARMV8_1-A:  .eabi_attribute 8, 1
1305; GENERIC-ARMV8_1-A:  .eabi_attribute 9, 2
1306; GENERIC-ARMV8_1-A:  .fpu crypto-neon-fp-armv8
1307; GENERIC-ARMV8_1-A:  .eabi_attribute 12, 4
1308; GENERIC-ARMV8_1-A-NOT:   .eabi_attribute 19
1309;; We default to IEEE 754 compliance
1310; GENERIC-ARMV8_1-A:  .eabi_attribute 20, 1
1311; GENERIC-ARMV8_1-A:  .eabi_attribute 21, 1
1312; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 22
1313; GENERIC-ARMV8_1-A:  .eabi_attribute 23, 3
1314; GENERIC-ARMV8_1-A:  .eabi_attribute 24, 1
1315; GENERIC-ARMV8_1-A:  .eabi_attribute 25, 1
1316; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 27
1317; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 28
1318; GENERIC-ARMV8_1-A:  .eabi_attribute 36, 1
1319; GENERIC-ARMV8_1-A:  .eabi_attribute 38, 1
1320; GENERIC-ARMV8_1-A:  .eabi_attribute 42, 1
1321; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 44
1322; GENERIC-ARMV8_1-A:  .eabi_attribute 68, 3
1323
1324; GENERIC-ARMV8_1-A-FAST-NOT:   .eabi_attribute 19
1325;; GENERIC-ARMV8_1-A has the ARMv8 FP unit, which always flushes preserving sign.
1326; GENERIC-ARMV8_1-A-FAST:  .eabi_attribute 20, 2
1327; GENERIC-ARMV8_1-A-FAST-NOT:  .eabi_attribute 21
1328; GENERIC-ARMV8_1-A-FAST-NOT:  .eabi_attribute 22
1329; GENERIC-ARMV8_1-A-FAST:  .eabi_attribute 23, 1
1330
1331; RELOC-PIC:  .eabi_attribute 15, 1
1332; RELOC-PIC:  .eabi_attribute 16, 1
1333; RELOC-PIC:  .eabi_attribute 17, 2
1334; RELOC-OTHER:  .eabi_attribute 17, 1
1335
1336; PCS-R9-USE:  .eabi_attribute 14, 0
1337; PCS-R9-RESERVE:  .eabi_attribute 14, 3
1338
1339define i32 @f(i64 %z) {
1340    ret i32 0
1341}
1342