1; RUN: llvm-as < %s | llc -march=arm && 2; RUN: llvm-as < %s | llc -march=arm | grep and | wc -l | grep 1 && 3; RUN: llvm-as < %s | llc -march=arm | grep orr | wc -l | grep 1 && 4; RUN: llvm-as < %s | llc -march=arm | grep eor | wc -l | grep 1 && 5; RUN: llvm-as < %s | llc -march=arm | grep mov.*lsl | wc -l | grep 1 && 6; RUN: llvm-as < %s | llc -march=arm | grep mov.*asr | wc -l | grep 1 7 8define i32 @f1(i32 %a, i32 %b) { 9entry: 10 %tmp2 = and i32 %b, %a ; <i32> [#uses=1] 11 ret i32 %tmp2 12} 13 14define i32 @f2(i32 %a, i32 %b) { 15entry: 16 %tmp2 = or i32 %b, %a ; <i32> [#uses=1] 17 ret i32 %tmp2 18} 19 20define i32 @f3(i32 %a, i32 %b) { 21entry: 22 %tmp2 = xor i32 %b, %a ; <i32> [#uses=1] 23 ret i32 %tmp2 24} 25 26define i32 @f4(i32 %a, i32 %b) { 27entry: 28 %tmp3 = shl i32 %a, %b ; <i32> [#uses=1] 29 ret i32 %tmp3 30} 31 32define i32 @f5(i32 %a, i32 %b) { 33entry: 34 %tmp3 = ashr i32 %a, %b ; <i32> [#uses=1] 35 ret i32 %tmp3 36} 37