1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc < %s -mtriple armv7-eabi -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE 3; RUN: llc < %s -mtriple armebv7-eabi -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE 4 5define arm_aapcs_vfpcc <8 x i8> @vmov_i8() { 6; CHECK-LE-LABEL: vmov_i8: 7; CHECK-LE: @ %bb.0: 8; CHECK-LE-NEXT: vmov.i64 d0, #0xff00000000000000 9; CHECK-LE-NEXT: bx lr 10; 11; CHECK-BE-LABEL: vmov_i8: 12; CHECK-BE: @ %bb.0: 13; CHECK-BE-NEXT: vmov.i64 d0, #0xff 14; CHECK-BE-NEXT: bx lr 15 ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 -1> 16} 17 18define arm_aapcs_vfpcc <4 x i16> @vmov_i16_a() { 19; CHECK-LE-LABEL: vmov_i16_a: 20; CHECK-LE: @ %bb.0: 21; CHECK-LE-NEXT: vmov.i64 d0, #0xffff000000000000 22; CHECK-LE-NEXT: bx lr 23; 24; CHECK-BE-LABEL: vmov_i16_a: 25; CHECK-BE: @ %bb.0: 26; CHECK-BE-NEXT: vmov.i64 d0, #0xffff 27; CHECK-BE-NEXT: bx lr 28 ret <4 x i16> <i16 0, i16 0, i16 0, i16 -1> 29} 30 31define arm_aapcs_vfpcc <4 x i16> @vmov_i16_b() { 32; CHECK-LE-LABEL: vmov_i16_b: 33; CHECK-LE: @ %bb.0: 34; CHECK-LE-NEXT: vmov.i64 d0, #0xff000000000000 35; CHECK-LE-NEXT: bx lr 36; 37; CHECK-BE-LABEL: vmov_i16_b: 38; CHECK-BE: @ %bb.0: 39; CHECK-BE-NEXT: vmov.i64 d0, #0xff 40; CHECK-BE-NEXT: bx lr 41 ret <4 x i16> <i16 0, i16 0, i16 0, i16 255> 42} 43 44define arm_aapcs_vfpcc <4 x i16> @vmov_i16_c() { 45; CHECK-LE-LABEL: vmov_i16_c: 46; CHECK-LE: @ %bb.0: 47; CHECK-LE-NEXT: vmov.i64 d0, #0xff00000000000000 48; CHECK-LE-NEXT: bx lr 49; 50; CHECK-BE-LABEL: vmov_i16_c: 51; CHECK-BE: @ %bb.0: 52; CHECK-BE-NEXT: vmov.i64 d0, #0xff00 53; CHECK-BE-NEXT: bx lr 54 ret <4 x i16> <i16 0, i16 0, i16 0, i16 65280> 55} 56 57define arm_aapcs_vfpcc <2 x i32> @vmov_i32_a() { 58; CHECK-LE-LABEL: vmov_i32_a: 59; CHECK-LE: @ %bb.0: 60; CHECK-LE-NEXT: vmov.i64 d0, #0xffffffff00000000 61; CHECK-LE-NEXT: bx lr 62; 63; CHECK-BE-LABEL: vmov_i32_a: 64; CHECK-BE: @ %bb.0: 65; CHECK-BE-NEXT: vmov.i64 d0, #0xffffffff 66; CHECK-BE-NEXT: bx lr 67 ret <2 x i32> <i32 0, i32 -1> 68} 69 70define arm_aapcs_vfpcc <2 x i32> @vmov_i32_b() { 71; CHECK-LE-LABEL: vmov_i32_b: 72; CHECK-LE: @ %bb.0: 73; CHECK-LE-NEXT: vmov.i64 d0, #0xff00000000 74; CHECK-LE-NEXT: bx lr 75; 76; CHECK-BE-LABEL: vmov_i32_b: 77; CHECK-BE: @ %bb.0: 78; CHECK-BE-NEXT: vmov.i64 d0, #0xff 79; CHECK-BE-NEXT: bx lr 80 ret <2 x i32> <i32 0, i32 255> 81} 82 83define arm_aapcs_vfpcc <2 x i32> @vmov_i32_c() { 84; CHECK-LE-LABEL: vmov_i32_c: 85; CHECK-LE: @ %bb.0: 86; CHECK-LE-NEXT: vmov.i64 d0, #0xff0000000000 87; CHECK-LE-NEXT: bx lr 88; 89; CHECK-BE-LABEL: vmov_i32_c: 90; CHECK-BE: @ %bb.0: 91; CHECK-BE-NEXT: vmov.i64 d0, #0xff00 92; CHECK-BE-NEXT: bx lr 93 ret <2 x i32> <i32 0, i32 65280> 94} 95 96define arm_aapcs_vfpcc <2 x i32> @vmov_i32_d() { 97; CHECK-LE-LABEL: vmov_i32_d: 98; CHECK-LE: @ %bb.0: 99; CHECK-LE-NEXT: vmov.i64 d0, #0xff000000000000 100; CHECK-LE-NEXT: bx lr 101; 102; CHECK-BE-LABEL: vmov_i32_d: 103; CHECK-BE: @ %bb.0: 104; CHECK-BE-NEXT: vmov.i64 d0, #0xff0000 105; CHECK-BE-NEXT: bx lr 106 ret <2 x i32> <i32 0, i32 16711680> 107} 108 109define arm_aapcs_vfpcc <2 x i32> @vmov_i32_e() { 110; CHECK-LE-LABEL: vmov_i32_e: 111; CHECK-LE: @ %bb.0: 112; CHECK-LE-NEXT: vmov.i64 d0, #0xff00000000000000 113; CHECK-LE-NEXT: bx lr 114; 115; CHECK-BE-LABEL: vmov_i32_e: 116; CHECK-BE: @ %bb.0: 117; CHECK-BE-NEXT: vmov.i64 d0, #0xff000000 118; CHECK-BE-NEXT: bx lr 119 ret <2 x i32> <i32 0, i32 4278190080> 120} 121 122define arm_aapcs_vfpcc <1 x i64> @vmov_i64_a() { 123; CHECK-LABEL: vmov_i64_a: 124; CHECK: @ %bb.0: 125; CHECK-NEXT: vmov.i8 d0, #0xff 126; CHECK-NEXT: bx lr 127 ret <1 x i64> <i64 -1> 128} 129 130define arm_aapcs_vfpcc <1 x i64> @vmov_i64_b() { 131; CHECK-LABEL: vmov_i64_b: 132; CHECK: @ %bb.0: 133; CHECK-NEXT: vmov.i64 d0, #0xffff00ff0000ff 134; CHECK-NEXT: bx lr 135 ret <1 x i64> <i64 72056498804490495> 136} 137