xref: /llvm-project/llvm/test/CodeGen/ARM/atomicrmw-cond-sub-clamp.ll (revision e0ed0333f0fed2e73f805afd58b61176a87aa3ad) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 < %s | FileCheck %s
3
4define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) {
5; CHECK-LABEL: atomicrmw_usub_cond_i8:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    dmb ish
8; CHECK-NEXT:  .LBB0_1: @ %atomicrmw.start
9; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
10; CHECK-NEXT:    ldrexb r12, [r0]
11; CHECK-NEXT:    uxtb r3, r1
12; CHECK-NEXT:    cmp r12, r3
13; CHECK-NEXT:    mov r3, r12
14; CHECK-NEXT:    subhs r3, r3, r1
15; CHECK-NEXT:    strexb r2, r3, [r0]
16; CHECK-NEXT:    cmp r2, #0
17; CHECK-NEXT:    bne .LBB0_1
18; CHECK-NEXT:  @ %bb.2: @ %atomicrmw.end
19; CHECK-NEXT:    mov r0, r12
20; CHECK-NEXT:    dmb ish
21; CHECK-NEXT:    bx lr
22  %result = atomicrmw usub_cond ptr %ptr, i8 %val seq_cst
23  ret i8 %result
24}
25
26define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) {
27; CHECK-LABEL: atomicrmw_usub_cond_i16:
28; CHECK:       @ %bb.0:
29; CHECK-NEXT:    dmb ish
30; CHECK-NEXT:  .LBB1_1: @ %atomicrmw.start
31; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
32; CHECK-NEXT:    ldrexh r12, [r0]
33; CHECK-NEXT:    uxth r3, r1
34; CHECK-NEXT:    cmp r12, r3
35; CHECK-NEXT:    mov r3, r12
36; CHECK-NEXT:    subhs r3, r3, r1
37; CHECK-NEXT:    strexh r2, r3, [r0]
38; CHECK-NEXT:    cmp r2, #0
39; CHECK-NEXT:    bne .LBB1_1
40; CHECK-NEXT:  @ %bb.2: @ %atomicrmw.end
41; CHECK-NEXT:    mov r0, r12
42; CHECK-NEXT:    dmb ish
43; CHECK-NEXT:    bx lr
44  %result = atomicrmw usub_cond ptr %ptr, i16 %val seq_cst
45  ret i16 %result
46}
47
48define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) {
49; CHECK-LABEL: atomicrmw_usub_cond_i32:
50; CHECK:       @ %bb.0:
51; CHECK-NEXT:    dmb ish
52; CHECK-NEXT:  .LBB2_1: @ %atomicrmw.start
53; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
54; CHECK-NEXT:    ldrex r12, [r0]
55; CHECK-NEXT:    subs r3, r12, r1
56; CHECK-NEXT:    movlo r3, r12
57; CHECK-NEXT:    strex r2, r3, [r0]
58; CHECK-NEXT:    cmp r2, #0
59; CHECK-NEXT:    bne .LBB2_1
60; CHECK-NEXT:  @ %bb.2: @ %atomicrmw.end
61; CHECK-NEXT:    mov r0, r12
62; CHECK-NEXT:    dmb ish
63; CHECK-NEXT:    bx lr
64  %result = atomicrmw usub_cond ptr %ptr, i32 %val seq_cst
65  ret i32 %result
66}
67
68define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) {
69; CHECK-LABEL: atomicrmw_usub_cond_i64:
70; CHECK:       @ %bb.0:
71; CHECK-NEXT:    .save {r4, r5, r11, lr}
72; CHECK-NEXT:    push {r4, r5, r11, lr}
73; CHECK-NEXT:    mov r12, r0
74; CHECK-NEXT:    dmb ish
75; CHECK-NEXT:  .LBB3_1: @ %atomicrmw.start
76; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
77; CHECK-NEXT:    ldrexd r0, r1, [r12]
78; CHECK-NEXT:    subs r4, r0, r2
79; CHECK-NEXT:    sbcs r5, r1, r3
80; CHECK-NEXT:    movlo r5, r1
81; CHECK-NEXT:    movlo r4, r0
82; CHECK-NEXT:    strexd lr, r4, r5, [r12]
83; CHECK-NEXT:    cmp lr, #0
84; CHECK-NEXT:    bne .LBB3_1
85; CHECK-NEXT:  @ %bb.2: @ %atomicrmw.end
86; CHECK-NEXT:    dmb ish
87; CHECK-NEXT:    pop {r4, r5, r11, pc}
88  %result = atomicrmw usub_cond ptr %ptr, i64 %val seq_cst
89  ret i64 %result
90}
91
92define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) {
93; CHECK-LABEL: atomicrmw_usub_sat_i8:
94; CHECK:       @ %bb.0:
95; CHECK-NEXT:    dmb ish
96; CHECK-NEXT:  .LBB4_1: @ %atomicrmw.start
97; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
98; CHECK-NEXT:    ldrexb r12, [r0]
99; CHECK-NEXT:    uqsub8 r3, r12, r1
100; CHECK-NEXT:    strexb r2, r3, [r0]
101; CHECK-NEXT:    cmp r2, #0
102; CHECK-NEXT:    bne .LBB4_1
103; CHECK-NEXT:  @ %bb.2: @ %atomicrmw.end
104; CHECK-NEXT:    mov r0, r12
105; CHECK-NEXT:    dmb ish
106; CHECK-NEXT:    bx lr
107  %result = atomicrmw usub_sat ptr %ptr, i8 %val seq_cst
108  ret i8 %result
109}
110
111define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) {
112; CHECK-LABEL: atomicrmw_usub_sat_i16:
113; CHECK:       @ %bb.0:
114; CHECK-NEXT:    dmb ish
115; CHECK-NEXT:  .LBB5_1: @ %atomicrmw.start
116; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
117; CHECK-NEXT:    ldrexh r12, [r0]
118; CHECK-NEXT:    uqsub16 r3, r12, r1
119; CHECK-NEXT:    strexh r2, r3, [r0]
120; CHECK-NEXT:    cmp r2, #0
121; CHECK-NEXT:    bne .LBB5_1
122; CHECK-NEXT:  @ %bb.2: @ %atomicrmw.end
123; CHECK-NEXT:    mov r0, r12
124; CHECK-NEXT:    dmb ish
125; CHECK-NEXT:    bx lr
126  %result = atomicrmw usub_sat ptr %ptr, i16 %val seq_cst
127  ret i16 %result
128}
129
130define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) {
131; CHECK-LABEL: atomicrmw_usub_sat_i32:
132; CHECK:       @ %bb.0:
133; CHECK-NEXT:    dmb ish
134; CHECK-NEXT:  .LBB6_1: @ %atomicrmw.start
135; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
136; CHECK-NEXT:    ldrex r12, [r0]
137; CHECK-NEXT:    subs r3, r12, r1
138; CHECK-NEXT:    movlo r3, #0
139; CHECK-NEXT:    strex r2, r3, [r0]
140; CHECK-NEXT:    cmp r2, #0
141; CHECK-NEXT:    bne .LBB6_1
142; CHECK-NEXT:  @ %bb.2: @ %atomicrmw.end
143; CHECK-NEXT:    mov r0, r12
144; CHECK-NEXT:    dmb ish
145; CHECK-NEXT:    bx lr
146  %result = atomicrmw usub_sat ptr %ptr, i32 %val seq_cst
147  ret i32 %result
148}
149
150define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) {
151; CHECK-LABEL: atomicrmw_usub_sat_i64:
152; CHECK:       @ %bb.0:
153; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
154; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
155; CHECK-NEXT:    mov r12, #0
156; CHECK-NEXT:    dmb ish
157; CHECK-NEXT:  .LBB7_1: @ %atomicrmw.start
158; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
159; CHECK-NEXT:    ldrexd r4, r5, [r0]
160; CHECK-NEXT:    subs r6, r4, r2
161; CHECK-NEXT:    sbcs r7, r5, r3
162; CHECK-NEXT:    adc r1, r12, #0
163; CHECK-NEXT:    teq r1, #1
164; CHECK-NEXT:    movwne r7, #0
165; CHECK-NEXT:    movwne r6, #0
166; CHECK-NEXT:    strexd r1, r6, r7, [r0]
167; CHECK-NEXT:    cmp r1, #0
168; CHECK-NEXT:    bne .LBB7_1
169; CHECK-NEXT:  @ %bb.2: @ %atomicrmw.end
170; CHECK-NEXT:    mov r0, r4
171; CHECK-NEXT:    mov r1, r5
172; CHECK-NEXT:    dmb ish
173; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, pc}
174  %result = atomicrmw usub_sat ptr %ptr, i64 %val seq_cst
175  ret i64 %result
176}
177