xref: /llvm-project/llvm/test/CodeGen/ARM/arm-v8.1m-check-mve-extension.ll (revision 74cdb8e6f8c88b97204f540601a553b412d1cd56) 
1*74cdb8e6Ssimpal01; RUN: llc -mtriple=arm-none-eabi -mcpu=cortex-m85 --float-abi=hard %s -o - | FileCheck %s
2*74cdb8e6Ssimpal01; RUN: llc -mtriple=arm-none-eabi -mcpu=cortex-m55 --float-abi=hard %s -o - | FileCheck %s
3*74cdb8e6Ssimpal01
4*74cdb8e6Ssimpal01; CHECK: .fpu   fpv5-d16
5*74cdb8e6Ssimpal01; CHECK-NEXT:  .arch_extension mve.fp
6*74cdb8e6Ssimpal01
7*74cdb8e6Ssimpal01define <4 x float> @vsubf32(<4 x float> %A, <4 x float> %B) {
8*74cdb8e6Ssimpal01; CHECK-LABEL: vsubf32:
9*74cdb8e6Ssimpal01; CHECK:       @ %bb.0:
10*74cdb8e6Ssimpal01; CHECK-NEXT:    vsub.f32 q0, q0, q1
11*74cdb8e6Ssimpal01; CHECK-NEXT:    bx lr
12*74cdb8e6Ssimpal01  %tmp3 = fsub <4 x float> %A, %B
13*74cdb8e6Ssimpal01  ret <4 x float> %tmp3
14*74cdb8e6Ssimpal01}
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