xref: /llvm-project/llvm/test/CodeGen/ARM/and-load-combine.ll (revision 25528d6de70e98683722e28655d8568d5f09b5c7) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s --check-prefix=ARM
3; RUN: llc -mtriple=armv7eb %s -o - | FileCheck %s --check-prefix=ARMEB
4; RUN: llc -mtriple=armv6m %s -o - | FileCheck %s --check-prefix=THUMB1
5; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=THUMB2
6
7define arm_aapcscc zeroext i1 @cmp_xor8_short_short(i16* nocapture readonly %a,
8; ARM-LABEL: cmp_xor8_short_short:
9; ARM:       @ %bb.0: @ %entry
10; ARM-NEXT:    ldrh r0, [r0]
11; ARM-NEXT:    ldrh r1, [r1]
12; ARM-NEXT:    eor r1, r1, r0
13; ARM-NEXT:    mov r0, #0
14; ARM-NEXT:    tst r1, #255
15; ARM-NEXT:    movweq r0, #1
16; ARM-NEXT:    bx lr
17;
18; ARMEB-LABEL: cmp_xor8_short_short:
19; ARMEB:       @ %bb.0: @ %entry
20; ARMEB-NEXT:    ldrh r0, [r0]
21; ARMEB-NEXT:    ldrh r1, [r1]
22; ARMEB-NEXT:    eor r1, r1, r0
23; ARMEB-NEXT:    mov r0, #0
24; ARMEB-NEXT:    tst r1, #255
25; ARMEB-NEXT:    movweq r0, #1
26; ARMEB-NEXT:    bx lr
27;
28; THUMB1-LABEL: cmp_xor8_short_short:
29; THUMB1:       @ %bb.0: @ %entry
30; THUMB1-NEXT:    ldrh r0, [r0]
31; THUMB1-NEXT:    ldrh r2, [r1]
32; THUMB1-NEXT:    eors r2, r0
33; THUMB1-NEXT:    movs r0, #1
34; THUMB1-NEXT:    movs r1, #0
35; THUMB1-NEXT:    lsls r2, r2, #24
36; THUMB1-NEXT:    beq .LBB0_2
37; THUMB1-NEXT:  @ %bb.1: @ %entry
38; THUMB1-NEXT:    mov r0, r1
39; THUMB1-NEXT:  .LBB0_2: @ %entry
40; THUMB1-NEXT:    bx lr
41;
42; THUMB2-LABEL: cmp_xor8_short_short:
43; THUMB2:       @ %bb.0: @ %entry
44; THUMB2-NEXT:    ldrh r0, [r0]
45; THUMB2-NEXT:    ldrh r1, [r1]
46; THUMB2-NEXT:    eors r0, r1
47; THUMB2-NEXT:    lsls r0, r0, #24
48; THUMB2-NEXT:    mov.w r0, #0
49; THUMB2-NEXT:    it eq
50; THUMB2-NEXT:    moveq r0, #1
51; THUMB2-NEXT:    bx lr
52                                                    i16* nocapture readonly %b) {
53entry:
54  %0 = load i16, i16* %a, align 2
55  %1 = load i16, i16* %b, align 2
56  %xor2 = xor i16 %1, %0
57  %2 = and i16 %xor2, 255
58  %cmp = icmp eq i16 %2, 0
59  ret i1 %cmp
60}
61
62define arm_aapcscc zeroext i1 @cmp_xor8_short_int(i16* nocapture readonly %a,
63; ARM-LABEL: cmp_xor8_short_int:
64; ARM:       @ %bb.0: @ %entry
65; ARM-NEXT:    ldrh r0, [r0]
66; ARM-NEXT:    ldr r1, [r1]
67; ARM-NEXT:    eor r1, r1, r0
68; ARM-NEXT:    mov r0, #0
69; ARM-NEXT:    tst r1, #255
70; ARM-NEXT:    movweq r0, #1
71; ARM-NEXT:    bx lr
72;
73; ARMEB-LABEL: cmp_xor8_short_int:
74; ARMEB:       @ %bb.0: @ %entry
75; ARMEB-NEXT:    ldrh r0, [r0]
76; ARMEB-NEXT:    ldr r1, [r1]
77; ARMEB-NEXT:    eor r1, r1, r0
78; ARMEB-NEXT:    mov r0, #0
79; ARMEB-NEXT:    tst r1, #255
80; ARMEB-NEXT:    movweq r0, #1
81; ARMEB-NEXT:    bx lr
82;
83; THUMB1-LABEL: cmp_xor8_short_int:
84; THUMB1:       @ %bb.0: @ %entry
85; THUMB1-NEXT:    ldrh r0, [r0]
86; THUMB1-NEXT:    ldr r2, [r1]
87; THUMB1-NEXT:    eors r2, r0
88; THUMB1-NEXT:    movs r0, #1
89; THUMB1-NEXT:    movs r1, #0
90; THUMB1-NEXT:    lsls r2, r2, #24
91; THUMB1-NEXT:    beq .LBB1_2
92; THUMB1-NEXT:  @ %bb.1: @ %entry
93; THUMB1-NEXT:    mov r0, r1
94; THUMB1-NEXT:  .LBB1_2: @ %entry
95; THUMB1-NEXT:    bx lr
96;
97; THUMB2-LABEL: cmp_xor8_short_int:
98; THUMB2:       @ %bb.0: @ %entry
99; THUMB2-NEXT:    ldrh r0, [r0]
100; THUMB2-NEXT:    ldr r1, [r1]
101; THUMB2-NEXT:    eors r0, r1
102; THUMB2-NEXT:    lsls r0, r0, #24
103; THUMB2-NEXT:    mov.w r0, #0
104; THUMB2-NEXT:    it eq
105; THUMB2-NEXT:    moveq r0, #1
106; THUMB2-NEXT:    bx lr
107                                                  i32* nocapture readonly %b) {
108entry:
109  %0 = load i16, i16* %a, align 2
110  %conv = zext i16 %0 to i32
111  %1 = load i32, i32* %b, align 4
112  %xor = xor i32 %1, %conv
113  %and = and i32 %xor, 255
114  %cmp = icmp eq i32 %and, 0
115  ret i1 %cmp
116}
117
118define arm_aapcscc zeroext i1 @cmp_xor8_int_int(i32* nocapture readonly %a,
119; ARM-LABEL: cmp_xor8_int_int:
120; ARM:       @ %bb.0: @ %entry
121; ARM-NEXT:    ldr r0, [r0]
122; ARM-NEXT:    ldr r1, [r1]
123; ARM-NEXT:    eor r1, r1, r0
124; ARM-NEXT:    mov r0, #0
125; ARM-NEXT:    tst r1, #255
126; ARM-NEXT:    movweq r0, #1
127; ARM-NEXT:    bx lr
128;
129; ARMEB-LABEL: cmp_xor8_int_int:
130; ARMEB:       @ %bb.0: @ %entry
131; ARMEB-NEXT:    ldr r0, [r0]
132; ARMEB-NEXT:    ldr r1, [r1]
133; ARMEB-NEXT:    eor r1, r1, r0
134; ARMEB-NEXT:    mov r0, #0
135; ARMEB-NEXT:    tst r1, #255
136; ARMEB-NEXT:    movweq r0, #1
137; ARMEB-NEXT:    bx lr
138;
139; THUMB1-LABEL: cmp_xor8_int_int:
140; THUMB1:       @ %bb.0: @ %entry
141; THUMB1-NEXT:    ldr r0, [r0]
142; THUMB1-NEXT:    ldr r2, [r1]
143; THUMB1-NEXT:    eors r2, r0
144; THUMB1-NEXT:    movs r0, #1
145; THUMB1-NEXT:    movs r1, #0
146; THUMB1-NEXT:    lsls r2, r2, #24
147; THUMB1-NEXT:    beq .LBB2_2
148; THUMB1-NEXT:  @ %bb.1: @ %entry
149; THUMB1-NEXT:    mov r0, r1
150; THUMB1-NEXT:  .LBB2_2: @ %entry
151; THUMB1-NEXT:    bx lr
152;
153; THUMB2-LABEL: cmp_xor8_int_int:
154; THUMB2:       @ %bb.0: @ %entry
155; THUMB2-NEXT:    ldr r0, [r0]
156; THUMB2-NEXT:    ldr r1, [r1]
157; THUMB2-NEXT:    eors r0, r1
158; THUMB2-NEXT:    lsls r0, r0, #24
159; THUMB2-NEXT:    mov.w r0, #0
160; THUMB2-NEXT:    it eq
161; THUMB2-NEXT:    moveq r0, #1
162; THUMB2-NEXT:    bx lr
163                                                i32* nocapture readonly %b) {
164entry:
165  %0 = load i32, i32* %a, align 4
166  %1 = load i32, i32* %b, align 4
167  %xor = xor i32 %1, %0
168  %and = and i32 %xor, 255
169  %cmp = icmp eq i32 %and, 0
170  ret i1 %cmp
171}
172
173define arm_aapcscc zeroext i1 @cmp_xor16(i32* nocapture readonly %a,
174; ARM-LABEL: cmp_xor16:
175; ARM:       @ %bb.0: @ %entry
176; ARM-NEXT:    ldr r0, [r0]
177; ARM-NEXT:    movw r2, #65535
178; ARM-NEXT:    ldr r1, [r1]
179; ARM-NEXT:    eor r1, r1, r0
180; ARM-NEXT:    mov r0, #0
181; ARM-NEXT:    tst r1, r2
182; ARM-NEXT:    movweq r0, #1
183; ARM-NEXT:    bx lr
184;
185; ARMEB-LABEL: cmp_xor16:
186; ARMEB:       @ %bb.0: @ %entry
187; ARMEB-NEXT:    ldr r0, [r0]
188; ARMEB-NEXT:    movw r2, #65535
189; ARMEB-NEXT:    ldr r1, [r1]
190; ARMEB-NEXT:    eor r1, r1, r0
191; ARMEB-NEXT:    mov r0, #0
192; ARMEB-NEXT:    tst r1, r2
193; ARMEB-NEXT:    movweq r0, #1
194; ARMEB-NEXT:    bx lr
195;
196; THUMB1-LABEL: cmp_xor16:
197; THUMB1:       @ %bb.0: @ %entry
198; THUMB1-NEXT:    ldr r0, [r0]
199; THUMB1-NEXT:    ldr r2, [r1]
200; THUMB1-NEXT:    eors r2, r0
201; THUMB1-NEXT:    movs r0, #1
202; THUMB1-NEXT:    movs r1, #0
203; THUMB1-NEXT:    lsls r2, r2, #16
204; THUMB1-NEXT:    beq .LBB3_2
205; THUMB1-NEXT:  @ %bb.1: @ %entry
206; THUMB1-NEXT:    mov r0, r1
207; THUMB1-NEXT:  .LBB3_2: @ %entry
208; THUMB1-NEXT:    bx lr
209;
210; THUMB2-LABEL: cmp_xor16:
211; THUMB2:       @ %bb.0: @ %entry
212; THUMB2-NEXT:    ldr r0, [r0]
213; THUMB2-NEXT:    ldr r1, [r1]
214; THUMB2-NEXT:    eors r0, r1
215; THUMB2-NEXT:    lsls r0, r0, #16
216; THUMB2-NEXT:    mov.w r0, #0
217; THUMB2-NEXT:    it eq
218; THUMB2-NEXT:    moveq r0, #1
219; THUMB2-NEXT:    bx lr
220                                         i32* nocapture readonly %b) {
221entry:
222  %0 = load i32, i32* %a, align 4
223  %1 = load i32, i32* %b, align 4
224  %xor = xor i32 %1, %0
225  %and = and i32 %xor, 65535
226  %cmp = icmp eq i32 %and, 0
227  ret i1 %cmp
228}
229
230define arm_aapcscc zeroext i1 @cmp_or8_short_short(i16* nocapture readonly %a,
231; ARM-LABEL: cmp_or8_short_short:
232; ARM:       @ %bb.0: @ %entry
233; ARM-NEXT:    ldrh r0, [r0]
234; ARM-NEXT:    ldrh r1, [r1]
235; ARM-NEXT:    orr r1, r1, r0
236; ARM-NEXT:    mov r0, #0
237; ARM-NEXT:    tst r1, #255
238; ARM-NEXT:    movweq r0, #1
239; ARM-NEXT:    bx lr
240;
241; ARMEB-LABEL: cmp_or8_short_short:
242; ARMEB:       @ %bb.0: @ %entry
243; ARMEB-NEXT:    ldrh r0, [r0]
244; ARMEB-NEXT:    ldrh r1, [r1]
245; ARMEB-NEXT:    orr r1, r1, r0
246; ARMEB-NEXT:    mov r0, #0
247; ARMEB-NEXT:    tst r1, #255
248; ARMEB-NEXT:    movweq r0, #1
249; ARMEB-NEXT:    bx lr
250;
251; THUMB1-LABEL: cmp_or8_short_short:
252; THUMB1:       @ %bb.0: @ %entry
253; THUMB1-NEXT:    ldrh r0, [r0]
254; THUMB1-NEXT:    ldrh r2, [r1]
255; THUMB1-NEXT:    orrs r2, r0
256; THUMB1-NEXT:    movs r0, #1
257; THUMB1-NEXT:    movs r1, #0
258; THUMB1-NEXT:    lsls r2, r2, #24
259; THUMB1-NEXT:    beq .LBB4_2
260; THUMB1-NEXT:  @ %bb.1: @ %entry
261; THUMB1-NEXT:    mov r0, r1
262; THUMB1-NEXT:  .LBB4_2: @ %entry
263; THUMB1-NEXT:    bx lr
264;
265; THUMB2-LABEL: cmp_or8_short_short:
266; THUMB2:       @ %bb.0: @ %entry
267; THUMB2-NEXT:    ldrh r0, [r0]
268; THUMB2-NEXT:    ldrh r1, [r1]
269; THUMB2-NEXT:    orrs r0, r1
270; THUMB2-NEXT:    lsls r0, r0, #24
271; THUMB2-NEXT:    mov.w r0, #0
272; THUMB2-NEXT:    it eq
273; THUMB2-NEXT:    moveq r0, #1
274; THUMB2-NEXT:    bx lr
275                                                   i16* nocapture readonly %b) {
276entry:
277  %0 = load i16, i16* %a, align 2
278  %1 = load i16, i16* %b, align 2
279  %or2 = or i16 %1, %0
280  %2 = and i16 %or2, 255
281  %cmp = icmp eq i16 %2, 0
282  ret i1 %cmp
283}
284
285define arm_aapcscc zeroext i1 @cmp_or8_short_int(i16* nocapture readonly %a,
286; ARM-LABEL: cmp_or8_short_int:
287; ARM:       @ %bb.0: @ %entry
288; ARM-NEXT:    ldrh r0, [r0]
289; ARM-NEXT:    ldr r1, [r1]
290; ARM-NEXT:    orr r1, r1, r0
291; ARM-NEXT:    mov r0, #0
292; ARM-NEXT:    tst r1, #255
293; ARM-NEXT:    movweq r0, #1
294; ARM-NEXT:    bx lr
295;
296; ARMEB-LABEL: cmp_or8_short_int:
297; ARMEB:       @ %bb.0: @ %entry
298; ARMEB-NEXT:    ldrh r0, [r0]
299; ARMEB-NEXT:    ldr r1, [r1]
300; ARMEB-NEXT:    orr r1, r1, r0
301; ARMEB-NEXT:    mov r0, #0
302; ARMEB-NEXT:    tst r1, #255
303; ARMEB-NEXT:    movweq r0, #1
304; ARMEB-NEXT:    bx lr
305;
306; THUMB1-LABEL: cmp_or8_short_int:
307; THUMB1:       @ %bb.0: @ %entry
308; THUMB1-NEXT:    ldrh r0, [r0]
309; THUMB1-NEXT:    ldr r2, [r1]
310; THUMB1-NEXT:    orrs r2, r0
311; THUMB1-NEXT:    movs r0, #1
312; THUMB1-NEXT:    movs r1, #0
313; THUMB1-NEXT:    lsls r2, r2, #24
314; THUMB1-NEXT:    beq .LBB5_2
315; THUMB1-NEXT:  @ %bb.1: @ %entry
316; THUMB1-NEXT:    mov r0, r1
317; THUMB1-NEXT:  .LBB5_2: @ %entry
318; THUMB1-NEXT:    bx lr
319;
320; THUMB2-LABEL: cmp_or8_short_int:
321; THUMB2:       @ %bb.0: @ %entry
322; THUMB2-NEXT:    ldrh r0, [r0]
323; THUMB2-NEXT:    ldr r1, [r1]
324; THUMB2-NEXT:    orrs r0, r1
325; THUMB2-NEXT:    lsls r0, r0, #24
326; THUMB2-NEXT:    mov.w r0, #0
327; THUMB2-NEXT:    it eq
328; THUMB2-NEXT:    moveq r0, #1
329; THUMB2-NEXT:    bx lr
330                                                 i32* nocapture readonly %b) {
331entry:
332  %0 = load i16, i16* %a, align 2
333  %conv = zext i16 %0 to i32
334  %1 = load i32, i32* %b, align 4
335  %or = or i32 %1, %conv
336  %and = and i32 %or, 255
337  %cmp = icmp eq i32 %and, 0
338  ret i1 %cmp
339}
340
341define arm_aapcscc zeroext i1 @cmp_or8_int_int(i32* nocapture readonly %a,
342; ARM-LABEL: cmp_or8_int_int:
343; ARM:       @ %bb.0: @ %entry
344; ARM-NEXT:    ldr r0, [r0]
345; ARM-NEXT:    ldr r1, [r1]
346; ARM-NEXT:    orr r1, r1, r0
347; ARM-NEXT:    mov r0, #0
348; ARM-NEXT:    tst r1, #255
349; ARM-NEXT:    movweq r0, #1
350; ARM-NEXT:    bx lr
351;
352; ARMEB-LABEL: cmp_or8_int_int:
353; ARMEB:       @ %bb.0: @ %entry
354; ARMEB-NEXT:    ldr r0, [r0]
355; ARMEB-NEXT:    ldr r1, [r1]
356; ARMEB-NEXT:    orr r1, r1, r0
357; ARMEB-NEXT:    mov r0, #0
358; ARMEB-NEXT:    tst r1, #255
359; ARMEB-NEXT:    movweq r0, #1
360; ARMEB-NEXT:    bx lr
361;
362; THUMB1-LABEL: cmp_or8_int_int:
363; THUMB1:       @ %bb.0: @ %entry
364; THUMB1-NEXT:    ldr r0, [r0]
365; THUMB1-NEXT:    ldr r2, [r1]
366; THUMB1-NEXT:    orrs r2, r0
367; THUMB1-NEXT:    movs r0, #1
368; THUMB1-NEXT:    movs r1, #0
369; THUMB1-NEXT:    lsls r2, r2, #24
370; THUMB1-NEXT:    beq .LBB6_2
371; THUMB1-NEXT:  @ %bb.1: @ %entry
372; THUMB1-NEXT:    mov r0, r1
373; THUMB1-NEXT:  .LBB6_2: @ %entry
374; THUMB1-NEXT:    bx lr
375;
376; THUMB2-LABEL: cmp_or8_int_int:
377; THUMB2:       @ %bb.0: @ %entry
378; THUMB2-NEXT:    ldr r0, [r0]
379; THUMB2-NEXT:    ldr r1, [r1]
380; THUMB2-NEXT:    orrs r0, r1
381; THUMB2-NEXT:    lsls r0, r0, #24
382; THUMB2-NEXT:    mov.w r0, #0
383; THUMB2-NEXT:    it eq
384; THUMB2-NEXT:    moveq r0, #1
385; THUMB2-NEXT:    bx lr
386                                               i32* nocapture readonly %b) {
387entry:
388  %0 = load i32, i32* %a, align 4
389  %1 = load i32, i32* %b, align 4
390  %or = or i32 %1, %0
391  %and = and i32 %or, 255
392  %cmp = icmp eq i32 %and, 0
393  ret i1 %cmp
394}
395
396define arm_aapcscc zeroext i1 @cmp_or16(i32* nocapture readonly %a,
397; ARM-LABEL: cmp_or16:
398; ARM:       @ %bb.0: @ %entry
399; ARM-NEXT:    ldr r0, [r0]
400; ARM-NEXT:    movw r2, #65535
401; ARM-NEXT:    ldr r1, [r1]
402; ARM-NEXT:    orr r1, r1, r0
403; ARM-NEXT:    mov r0, #0
404; ARM-NEXT:    tst r1, r2
405; ARM-NEXT:    movweq r0, #1
406; ARM-NEXT:    bx lr
407;
408; ARMEB-LABEL: cmp_or16:
409; ARMEB:       @ %bb.0: @ %entry
410; ARMEB-NEXT:    ldr r0, [r0]
411; ARMEB-NEXT:    movw r2, #65535
412; ARMEB-NEXT:    ldr r1, [r1]
413; ARMEB-NEXT:    orr r1, r1, r0
414; ARMEB-NEXT:    mov r0, #0
415; ARMEB-NEXT:    tst r1, r2
416; ARMEB-NEXT:    movweq r0, #1
417; ARMEB-NEXT:    bx lr
418;
419; THUMB1-LABEL: cmp_or16:
420; THUMB1:       @ %bb.0: @ %entry
421; THUMB1-NEXT:    ldr r0, [r0]
422; THUMB1-NEXT:    ldr r2, [r1]
423; THUMB1-NEXT:    orrs r2, r0
424; THUMB1-NEXT:    movs r0, #1
425; THUMB1-NEXT:    movs r1, #0
426; THUMB1-NEXT:    lsls r2, r2, #16
427; THUMB1-NEXT:    beq .LBB7_2
428; THUMB1-NEXT:  @ %bb.1: @ %entry
429; THUMB1-NEXT:    mov r0, r1
430; THUMB1-NEXT:  .LBB7_2: @ %entry
431; THUMB1-NEXT:    bx lr
432;
433; THUMB2-LABEL: cmp_or16:
434; THUMB2:       @ %bb.0: @ %entry
435; THUMB2-NEXT:    ldr r0, [r0]
436; THUMB2-NEXT:    ldr r1, [r1]
437; THUMB2-NEXT:    orrs r0, r1
438; THUMB2-NEXT:    lsls r0, r0, #16
439; THUMB2-NEXT:    mov.w r0, #0
440; THUMB2-NEXT:    it eq
441; THUMB2-NEXT:    moveq r0, #1
442; THUMB2-NEXT:    bx lr
443                                        i32* nocapture readonly %b) {
444entry:
445  %0 = load i32, i32* %a, align 4
446  %1 = load i32, i32* %b, align 4
447  %or = or i32 %1, %0
448  %and = and i32 %or, 65535
449  %cmp = icmp eq i32 %and, 0
450  ret i1 %cmp
451}
452
453define arm_aapcscc zeroext i1 @cmp_and8_short_short(i16* nocapture readonly %a,
454; ARM-LABEL: cmp_and8_short_short:
455; ARM:       @ %bb.0: @ %entry
456; ARM-NEXT:    ldrh r1, [r1]
457; ARM-NEXT:    ldrh r0, [r0]
458; ARM-NEXT:    and r1, r0, r1
459; ARM-NEXT:    mov r0, #0
460; ARM-NEXT:    tst r1, #255
461; ARM-NEXT:    movweq r0, #1
462; ARM-NEXT:    bx lr
463;
464; ARMEB-LABEL: cmp_and8_short_short:
465; ARMEB:       @ %bb.0: @ %entry
466; ARMEB-NEXT:    ldrh r1, [r1]
467; ARMEB-NEXT:    ldrh r0, [r0]
468; ARMEB-NEXT:    and r1, r0, r1
469; ARMEB-NEXT:    mov r0, #0
470; ARMEB-NEXT:    tst r1, #255
471; ARMEB-NEXT:    movweq r0, #1
472; ARMEB-NEXT:    bx lr
473;
474; THUMB1-LABEL: cmp_and8_short_short:
475; THUMB1:       @ %bb.0: @ %entry
476; THUMB1-NEXT:    ldrh r1, [r1]
477; THUMB1-NEXT:    ldrh r2, [r0]
478; THUMB1-NEXT:    ands r2, r1
479; THUMB1-NEXT:    movs r0, #1
480; THUMB1-NEXT:    movs r1, #0
481; THUMB1-NEXT:    lsls r2, r2, #24
482; THUMB1-NEXT:    beq .LBB8_2
483; THUMB1-NEXT:  @ %bb.1: @ %entry
484; THUMB1-NEXT:    mov r0, r1
485; THUMB1-NEXT:  .LBB8_2: @ %entry
486; THUMB1-NEXT:    bx lr
487;
488; THUMB2-LABEL: cmp_and8_short_short:
489; THUMB2:       @ %bb.0: @ %entry
490; THUMB2-NEXT:    ldrh r1, [r1]
491; THUMB2-NEXT:    ldrh r0, [r0]
492; THUMB2-NEXT:    ands r0, r1
493; THUMB2-NEXT:    lsls r0, r0, #24
494; THUMB2-NEXT:    mov.w r0, #0
495; THUMB2-NEXT:    it eq
496; THUMB2-NEXT:    moveq r0, #1
497; THUMB2-NEXT:    bx lr
498                                                    i16* nocapture readonly %b) {
499entry:
500  %0 = load i16, i16* %a, align 2
501  %1 = load i16, i16* %b, align 2
502  %and3 = and i16 %0, 255
503  %2 = and i16 %and3, %1
504  %cmp = icmp eq i16 %2, 0
505  ret i1 %cmp
506}
507
508define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a,
509; ARM-LABEL: cmp_and8_short_int:
510; ARM:       @ %bb.0: @ %entry
511; ARM-NEXT:    ldrh r0, [r0]
512; ARM-NEXT:    ldr r1, [r1]
513; ARM-NEXT:    and r1, r1, r0
514; ARM-NEXT:    mov r0, #0
515; ARM-NEXT:    tst r1, #255
516; ARM-NEXT:    movweq r0, #1
517; ARM-NEXT:    bx lr
518;
519; ARMEB-LABEL: cmp_and8_short_int:
520; ARMEB:       @ %bb.0: @ %entry
521; ARMEB-NEXT:    ldrh r0, [r0]
522; ARMEB-NEXT:    ldr r1, [r1]
523; ARMEB-NEXT:    and r1, r1, r0
524; ARMEB-NEXT:    mov r0, #0
525; ARMEB-NEXT:    tst r1, #255
526; ARMEB-NEXT:    movweq r0, #1
527; ARMEB-NEXT:    bx lr
528;
529; THUMB1-LABEL: cmp_and8_short_int:
530; THUMB1:       @ %bb.0: @ %entry
531; THUMB1-NEXT:    ldrh r0, [r0]
532; THUMB1-NEXT:    ldr r2, [r1]
533; THUMB1-NEXT:    ands r2, r0
534; THUMB1-NEXT:    movs r0, #1
535; THUMB1-NEXT:    movs r1, #0
536; THUMB1-NEXT:    lsls r2, r2, #24
537; THUMB1-NEXT:    beq .LBB9_2
538; THUMB1-NEXT:  @ %bb.1: @ %entry
539; THUMB1-NEXT:    mov r0, r1
540; THUMB1-NEXT:  .LBB9_2: @ %entry
541; THUMB1-NEXT:    bx lr
542;
543; THUMB2-LABEL: cmp_and8_short_int:
544; THUMB2:       @ %bb.0: @ %entry
545; THUMB2-NEXT:    ldrh r0, [r0]
546; THUMB2-NEXT:    ldr r1, [r1]
547; THUMB2-NEXT:    ands r0, r1
548; THUMB2-NEXT:    lsls r0, r0, #24
549; THUMB2-NEXT:    mov.w r0, #0
550; THUMB2-NEXT:    it eq
551; THUMB2-NEXT:    moveq r0, #1
552; THUMB2-NEXT:    bx lr
553                                                  i32* nocapture readonly %b) {
554entry:
555  %0 = load i16, i16* %a, align 2
556  %1 = load i32, i32* %b, align 4
557  %2 = and i16 %0, 255
558  %and = zext i16 %2 to i32
559  %and1 = and i32 %1, %and
560  %cmp = icmp eq i32 %and1, 0
561  ret i1 %cmp
562}
563
564define arm_aapcscc zeroext i1 @cmp_and8_int_int(i32* nocapture readonly %a,
565; ARM-LABEL: cmp_and8_int_int:
566; ARM:       @ %bb.0: @ %entry
567; ARM-NEXT:    ldr r1, [r1]
568; ARM-NEXT:    ldr r0, [r0]
569; ARM-NEXT:    and r1, r0, r1
570; ARM-NEXT:    mov r0, #0
571; ARM-NEXT:    tst r1, #255
572; ARM-NEXT:    movweq r0, #1
573; ARM-NEXT:    bx lr
574;
575; ARMEB-LABEL: cmp_and8_int_int:
576; ARMEB:       @ %bb.0: @ %entry
577; ARMEB-NEXT:    ldr r1, [r1]
578; ARMEB-NEXT:    ldr r0, [r0]
579; ARMEB-NEXT:    and r1, r0, r1
580; ARMEB-NEXT:    mov r0, #0
581; ARMEB-NEXT:    tst r1, #255
582; ARMEB-NEXT:    movweq r0, #1
583; ARMEB-NEXT:    bx lr
584;
585; THUMB1-LABEL: cmp_and8_int_int:
586; THUMB1:       @ %bb.0: @ %entry
587; THUMB1-NEXT:    ldr r1, [r1]
588; THUMB1-NEXT:    ldr r2, [r0]
589; THUMB1-NEXT:    ands r2, r1
590; THUMB1-NEXT:    movs r0, #1
591; THUMB1-NEXT:    movs r1, #0
592; THUMB1-NEXT:    lsls r2, r2, #24
593; THUMB1-NEXT:    beq .LBB10_2
594; THUMB1-NEXT:  @ %bb.1: @ %entry
595; THUMB1-NEXT:    mov r0, r1
596; THUMB1-NEXT:  .LBB10_2: @ %entry
597; THUMB1-NEXT:    bx lr
598;
599; THUMB2-LABEL: cmp_and8_int_int:
600; THUMB2:       @ %bb.0: @ %entry
601; THUMB2-NEXT:    ldr r1, [r1]
602; THUMB2-NEXT:    ldr r0, [r0]
603; THUMB2-NEXT:    ands r0, r1
604; THUMB2-NEXT:    lsls r0, r0, #24
605; THUMB2-NEXT:    mov.w r0, #0
606; THUMB2-NEXT:    it eq
607; THUMB2-NEXT:    moveq r0, #1
608; THUMB2-NEXT:    bx lr
609                                                i32* nocapture readonly %b) {
610entry:
611  %0 = load i32, i32* %a, align 4
612  %1 = load i32, i32* %b, align 4
613  %and = and i32 %0, 255
614  %and1 = and i32 %and, %1
615  %cmp = icmp eq i32 %and1, 0
616  ret i1 %cmp
617}
618
619define arm_aapcscc zeroext i1 @cmp_and16(i32* nocapture readonly %a,
620; ARM-LABEL: cmp_and16:
621; ARM:       @ %bb.0: @ %entry
622; ARM-NEXT:    ldr r1, [r1]
623; ARM-NEXT:    movw r2, #65535
624; ARM-NEXT:    ldr r0, [r0]
625; ARM-NEXT:    and r1, r0, r1
626; ARM-NEXT:    mov r0, #0
627; ARM-NEXT:    tst r1, r2
628; ARM-NEXT:    movweq r0, #1
629; ARM-NEXT:    bx lr
630;
631; ARMEB-LABEL: cmp_and16:
632; ARMEB:       @ %bb.0: @ %entry
633; ARMEB-NEXT:    ldr r1, [r1]
634; ARMEB-NEXT:    movw r2, #65535
635; ARMEB-NEXT:    ldr r0, [r0]
636; ARMEB-NEXT:    and r1, r0, r1
637; ARMEB-NEXT:    mov r0, #0
638; ARMEB-NEXT:    tst r1, r2
639; ARMEB-NEXT:    movweq r0, #1
640; ARMEB-NEXT:    bx lr
641;
642; THUMB1-LABEL: cmp_and16:
643; THUMB1:       @ %bb.0: @ %entry
644; THUMB1-NEXT:    ldr r1, [r1]
645; THUMB1-NEXT:    ldr r2, [r0]
646; THUMB1-NEXT:    ands r2, r1
647; THUMB1-NEXT:    movs r0, #1
648; THUMB1-NEXT:    movs r1, #0
649; THUMB1-NEXT:    lsls r2, r2, #16
650; THUMB1-NEXT:    beq .LBB11_2
651; THUMB1-NEXT:  @ %bb.1: @ %entry
652; THUMB1-NEXT:    mov r0, r1
653; THUMB1-NEXT:  .LBB11_2: @ %entry
654; THUMB1-NEXT:    bx lr
655;
656; THUMB2-LABEL: cmp_and16:
657; THUMB2:       @ %bb.0: @ %entry
658; THUMB2-NEXT:    ldr r1, [r1]
659; THUMB2-NEXT:    ldr r0, [r0]
660; THUMB2-NEXT:    ands r0, r1
661; THUMB2-NEXT:    lsls r0, r0, #16
662; THUMB2-NEXT:    mov.w r0, #0
663; THUMB2-NEXT:    it eq
664; THUMB2-NEXT:    moveq r0, #1
665; THUMB2-NEXT:    bx lr
666                                         i32* nocapture readonly %b) {
667entry:
668  %0 = load i32, i32* %a, align 4
669  %1 = load i32, i32* %b, align 4
670  %and = and i32 %0, 65535
671  %and1 = and i32 %and, %1
672  %cmp = icmp eq i32 %and1, 0
673  ret i1 %cmp
674}
675
676define arm_aapcscc i32 @add_and16(i32* nocapture readonly %a, i32 %y, i32 %z) {
677; ARM-LABEL: add_and16:
678; ARM:       @ %bb.0: @ %entry
679; ARM-NEXT:    ldr r0, [r0]
680; ARM-NEXT:    add r1, r1, r2
681; ARM-NEXT:    orr r0, r0, r1
682; ARM-NEXT:    uxth r0, r0
683; ARM-NEXT:    bx lr
684;
685; ARMEB-LABEL: add_and16:
686; ARMEB:       @ %bb.0: @ %entry
687; ARMEB-NEXT:    ldr r0, [r0]
688; ARMEB-NEXT:    add r1, r1, r2
689; ARMEB-NEXT:    orr r0, r0, r1
690; ARMEB-NEXT:    uxth r0, r0
691; ARMEB-NEXT:    bx lr
692;
693; THUMB1-LABEL: add_and16:
694; THUMB1:       @ %bb.0: @ %entry
695; THUMB1-NEXT:    adds r1, r1, r2
696; THUMB1-NEXT:    ldr r0, [r0]
697; THUMB1-NEXT:    orrs r0, r1
698; THUMB1-NEXT:    uxth r0, r0
699; THUMB1-NEXT:    bx lr
700;
701; THUMB2-LABEL: add_and16:
702; THUMB2:       @ %bb.0: @ %entry
703; THUMB2-NEXT:    ldr r0, [r0]
704; THUMB2-NEXT:    add r1, r2
705; THUMB2-NEXT:    orrs r0, r1
706; THUMB2-NEXT:    uxth r0, r0
707; THUMB2-NEXT:    bx lr
708entry:
709  %x = load i32, i32* %a, align 4
710  %add = add i32 %y, %z
711  %or = or i32 %x, %add
712  %and = and i32 %or, 65535
713  ret i32 %and
714}
715
716define arm_aapcscc i32 @test1(i32* %a, i32* %b, i32 %x, i32 %y) {
717; ARM-LABEL: test1:
718; ARM:       @ %bb.0: @ %entry
719; ARM-NEXT:    mul r2, r2, r3
720; ARM-NEXT:    ldr r1, [r1]
721; ARM-NEXT:    ldr r0, [r0]
722; ARM-NEXT:    eor r0, r0, r1
723; ARM-NEXT:    orr r0, r0, r2
724; ARM-NEXT:    uxth r0, r0
725; ARM-NEXT:    bx lr
726;
727; ARMEB-LABEL: test1:
728; ARMEB:       @ %bb.0: @ %entry
729; ARMEB-NEXT:    mul r2, r2, r3
730; ARMEB-NEXT:    ldr r1, [r1]
731; ARMEB-NEXT:    ldr r0, [r0]
732; ARMEB-NEXT:    eor r0, r0, r1
733; ARMEB-NEXT:    orr r0, r0, r2
734; ARMEB-NEXT:    uxth r0, r0
735; ARMEB-NEXT:    bx lr
736;
737; THUMB1-LABEL: test1:
738; THUMB1:       @ %bb.0: @ %entry
739; THUMB1-NEXT:    muls r2, r3, r2
740; THUMB1-NEXT:    ldr r1, [r1]
741; THUMB1-NEXT:    ldr r0, [r0]
742; THUMB1-NEXT:    eors r0, r1
743; THUMB1-NEXT:    orrs r0, r2
744; THUMB1-NEXT:    uxth r0, r0
745; THUMB1-NEXT:    bx lr
746;
747; THUMB2-LABEL: test1:
748; THUMB2:       @ %bb.0: @ %entry
749; THUMB2-NEXT:    muls r2, r3, r2
750; THUMB2-NEXT:    ldr r1, [r1]
751; THUMB2-NEXT:    ldr r0, [r0]
752; THUMB2-NEXT:    eors r0, r1
753; THUMB2-NEXT:    orrs r0, r2
754; THUMB2-NEXT:    uxth r0, r0
755; THUMB2-NEXT:    bx lr
756entry:
757  %0 = load i32, i32* %a, align 4
758  %1 = load i32, i32* %b, align 4
759  %mul = mul i32 %x, %y
760  %xor = xor i32 %0, %1
761  %or = or i32 %xor, %mul
762  %and = and i32 %or, 65535
763  ret i32 %and
764}
765
766define arm_aapcscc i32 @test2(i32* %a, i32* %b, i32 %x, i32 %y) {
767; ARM-LABEL: test2:
768; ARM:       @ %bb.0: @ %entry
769; ARM-NEXT:    ldr r1, [r1]
770; ARM-NEXT:    ldr r0, [r0]
771; ARM-NEXT:    mul r1, r2, r1
772; ARM-NEXT:    eor r0, r0, r3
773; ARM-NEXT:    orr r0, r0, r1
774; ARM-NEXT:    uxth r0, r0
775; ARM-NEXT:    bx lr
776;
777; ARMEB-LABEL: test2:
778; ARMEB:       @ %bb.0: @ %entry
779; ARMEB-NEXT:    ldr r1, [r1]
780; ARMEB-NEXT:    ldr r0, [r0]
781; ARMEB-NEXT:    mul r1, r2, r1
782; ARMEB-NEXT:    eor r0, r0, r3
783; ARMEB-NEXT:    orr r0, r0, r1
784; ARMEB-NEXT:    uxth r0, r0
785; ARMEB-NEXT:    bx lr
786;
787; THUMB1-LABEL: test2:
788; THUMB1:       @ %bb.0: @ %entry
789; THUMB1-NEXT:    ldr r1, [r1]
790; THUMB1-NEXT:    muls r1, r2, r1
791; THUMB1-NEXT:    ldr r0, [r0]
792; THUMB1-NEXT:    eors r0, r3
793; THUMB1-NEXT:    orrs r0, r1
794; THUMB1-NEXT:    uxth r0, r0
795; THUMB1-NEXT:    bx lr
796;
797; THUMB2-LABEL: test2:
798; THUMB2:       @ %bb.0: @ %entry
799; THUMB2-NEXT:    ldr r1, [r1]
800; THUMB2-NEXT:    ldr r0, [r0]
801; THUMB2-NEXT:    muls r1, r2, r1
802; THUMB2-NEXT:    eors r0, r3
803; THUMB2-NEXT:    orrs r0, r1
804; THUMB2-NEXT:    uxth r0, r0
805; THUMB2-NEXT:    bx lr
806entry:
807  %0 = load i32, i32* %a, align 4
808  %1 = load i32, i32* %b, align 4
809  %mul = mul i32 %x, %1
810  %xor = xor i32 %0, %y
811  %or = or i32 %xor, %mul
812  %and = and i32 %or, 65535
813  ret i32 %and
814}
815
816define arm_aapcscc i32 @test3(i32* %a, i32* %b, i32 %x, i16* %y) {
817; ARM-LABEL: test3:
818; ARM:       @ %bb.0: @ %entry
819; ARM-NEXT:    ldr r0, [r0]
820; ARM-NEXT:    mul r1, r2, r0
821; ARM-NEXT:    ldrh r2, [r3]
822; ARM-NEXT:    eor r0, r0, r2
823; ARM-NEXT:    orr r0, r0, r1
824; ARM-NEXT:    uxth r0, r0
825; ARM-NEXT:    bx lr
826;
827; ARMEB-LABEL: test3:
828; ARMEB:       @ %bb.0: @ %entry
829; ARMEB-NEXT:    ldr r0, [r0]
830; ARMEB-NEXT:    mul r1, r2, r0
831; ARMEB-NEXT:    ldrh r2, [r3]
832; ARMEB-NEXT:    eor r0, r0, r2
833; ARMEB-NEXT:    orr r0, r0, r1
834; ARMEB-NEXT:    uxth r0, r0
835; ARMEB-NEXT:    bx lr
836;
837; THUMB1-LABEL: test3:
838; THUMB1:       @ %bb.0: @ %entry
839; THUMB1-NEXT:    ldr r0, [r0]
840; THUMB1-NEXT:    muls r2, r0, r2
841; THUMB1-NEXT:    ldrh r1, [r3]
842; THUMB1-NEXT:    eors r1, r0
843; THUMB1-NEXT:    orrs r1, r2
844; THUMB1-NEXT:    uxth r0, r1
845; THUMB1-NEXT:    bx lr
846;
847; THUMB2-LABEL: test3:
848; THUMB2:       @ %bb.0: @ %entry
849; THUMB2-NEXT:    ldr r0, [r0]
850; THUMB2-NEXT:    mul r1, r2, r0
851; THUMB2-NEXT:    ldrh r2, [r3]
852; THUMB2-NEXT:    eors r0, r2
853; THUMB2-NEXT:    orrs r0, r1
854; THUMB2-NEXT:    uxth r0, r0
855; THUMB2-NEXT:    bx lr
856entry:
857  %0 = load i32, i32* %a, align 4
858  %1 = load i16, i16* %y, align 4
859  %2 = zext i16 %1 to i32
860  %mul = mul i32 %x, %0
861  %xor = xor i32 %0, %2
862  %or = or i32 %xor, %mul
863  %and = and i32 %or, 65535
864  ret i32 %and
865}
866
867define arm_aapcscc i32 @test4(i32* %a, i32* %b, i32 %x, i32 %y) {
868; ARM-LABEL: test4:
869; ARM:       @ %bb.0: @ %entry
870; ARM-NEXT:    mul r2, r2, r3
871; ARM-NEXT:    ldr r1, [r1]
872; ARM-NEXT:    ldr r0, [r0]
873; ARM-NEXT:    eor r0, r0, r1
874; ARM-NEXT:    orr r0, r0, r2
875; ARM-NEXT:    uxth r0, r0
876; ARM-NEXT:    bx lr
877;
878; ARMEB-LABEL: test4:
879; ARMEB:       @ %bb.0: @ %entry
880; ARMEB-NEXT:    mul r2, r2, r3
881; ARMEB-NEXT:    ldr r1, [r1]
882; ARMEB-NEXT:    ldr r0, [r0]
883; ARMEB-NEXT:    eor r0, r0, r1
884; ARMEB-NEXT:    orr r0, r0, r2
885; ARMEB-NEXT:    uxth r0, r0
886; ARMEB-NEXT:    bx lr
887;
888; THUMB1-LABEL: test4:
889; THUMB1:       @ %bb.0: @ %entry
890; THUMB1-NEXT:    muls r2, r3, r2
891; THUMB1-NEXT:    ldr r1, [r1]
892; THUMB1-NEXT:    ldr r0, [r0]
893; THUMB1-NEXT:    eors r0, r1
894; THUMB1-NEXT:    orrs r0, r2
895; THUMB1-NEXT:    uxth r0, r0
896; THUMB1-NEXT:    bx lr
897;
898; THUMB2-LABEL: test4:
899; THUMB2:       @ %bb.0: @ %entry
900; THUMB2-NEXT:    muls r2, r3, r2
901; THUMB2-NEXT:    ldr r1, [r1]
902; THUMB2-NEXT:    ldr r0, [r0]
903; THUMB2-NEXT:    eors r0, r1
904; THUMB2-NEXT:    orrs r0, r2
905; THUMB2-NEXT:    uxth r0, r0
906; THUMB2-NEXT:    bx lr
907entry:
908  %0 = load i32, i32* %a, align 4
909  %1 = load i32, i32* %b, align 4
910  %mul = mul i32 %x, %y
911  %xor = xor i32 %0, %1
912  %or = or i32 %xor, %mul
913  %and = and i32 %or, 65535
914  ret i32 %and
915}
916
917define arm_aapcscc i32 @test5(i32* %a, i32* %b, i32 %x, i16 zeroext %y) {
918; ARM-LABEL: test5:
919; ARM:       @ %bb.0: @ %entry
920; ARM-NEXT:    ldr r1, [r1]
921; ARM-NEXT:    ldr r0, [r0]
922; ARM-NEXT:    mul r1, r2, r1
923; ARM-NEXT:    eor r0, r0, r3
924; ARM-NEXT:    orr r0, r0, r1
925; ARM-NEXT:    uxth r0, r0
926; ARM-NEXT:    bx lr
927;
928; ARMEB-LABEL: test5:
929; ARMEB:       @ %bb.0: @ %entry
930; ARMEB-NEXT:    ldr r1, [r1]
931; ARMEB-NEXT:    ldr r0, [r0]
932; ARMEB-NEXT:    mul r1, r2, r1
933; ARMEB-NEXT:    eor r0, r0, r3
934; ARMEB-NEXT:    orr r0, r0, r1
935; ARMEB-NEXT:    uxth r0, r0
936; ARMEB-NEXT:    bx lr
937;
938; THUMB1-LABEL: test5:
939; THUMB1:       @ %bb.0: @ %entry
940; THUMB1-NEXT:    ldr r1, [r1]
941; THUMB1-NEXT:    muls r1, r2, r1
942; THUMB1-NEXT:    ldr r0, [r0]
943; THUMB1-NEXT:    eors r0, r3
944; THUMB1-NEXT:    orrs r0, r1
945; THUMB1-NEXT:    uxth r0, r0
946; THUMB1-NEXT:    bx lr
947;
948; THUMB2-LABEL: test5:
949; THUMB2:       @ %bb.0: @ %entry
950; THUMB2-NEXT:    ldr r1, [r1]
951; THUMB2-NEXT:    ldr r0, [r0]
952; THUMB2-NEXT:    muls r1, r2, r1
953; THUMB2-NEXT:    eors r0, r3
954; THUMB2-NEXT:    orrs r0, r1
955; THUMB2-NEXT:    uxth r0, r0
956; THUMB2-NEXT:    bx lr
957entry:
958  %0 = load i32, i32* %a, align 4
959  %1 = load i32, i32* %b, align 4
960  %mul = mul i32 %x, %1
961  %ext = zext i16 %y to i32
962  %xor = xor i32 %0, %ext
963  %or = or i32 %xor, %mul
964  %and = and i32 %or, 65535
965  ret i32 %and
966}
967