xref: /llvm-project/llvm/test/CodeGen/ARM/and-load-combine.ll (revision 1ad085b8081e270e6038bf39dfc84eb50c14d3af) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s --check-prefix=ARM
3; RUN: llc -mtriple=armv7eb %s -o - | FileCheck %s --check-prefix=ARMEB
4; RUN: llc -mtriple=armv6m %s -o - | FileCheck %s --check-prefix=THUMB1
5; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=THUMB2
6
7define arm_aapcscc zeroext i1 @cmp_xor8_short_short(i16* nocapture readonly %a,
8                                                    i16* nocapture readonly %b) {
9; ARM-LABEL: cmp_xor8_short_short:
10; ARM:         ldrb r2, [r0]
11; ARM-NEXT:    mov r0, #0
12; ARM-NEXT:    ldrb r1, [r1]
13; ARM-NEXT:    teq r1, r2
14; ARM-NEXT:    movweq r0, #1
15; ARM-NEXT:    bx lr
16;
17; ARMEB-LABEL: cmp_xor8_short_short:
18; ARMEB:        ldrb r2, [r0, #1]
19; ARMEB-NEXT:    mov r0, #0
20; ARMEB-NEXT:    ldrb r1, [r1, #1]
21; ARMEB-NEXT:    teq r1, r2
22; ARMEB-NEXT:    movweq r0, #1
23; ARMEB-NEXT:    bx lr
24;
25; THUMB1-LABEL: cmp_xor8_short_short:
26; THUMB1:         ldrb r0, [r0]
27; THUMB1-NEXT:    ldrb r2, [r1]
28; THUMB1-NEXT:    eors r2, r0
29; THUMB1-NEXT:    movs r0, #1
30; THUMB1-NEXT:    movs r1, #0
31; THUMB1-NEXT:    cmp r2, #0
32; THUMB1-NEXT:    beq .LBB0_2
33; THUMB1-NEXT:  @ %bb.1: @ %entry
34; THUMB1-NEXT:    mov r0, r1
35; THUMB1-NEXT:  .LBB0_2: @ %entry
36; THUMB1-NEXT:    bx lr
37;
38; THUMB2-LABEL: cmp_xor8_short_short:
39; THUMB2:         ldrb r2, [r0]
40; THUMB2-NEXT:    movs r0, #0
41; THUMB2-NEXT:    ldrb r1, [r1]
42; THUMB2-NEXT:    teq.w r1, r2
43; THUMB2-NEXT:    it eq
44; THUMB2-NEXT:    moveq r0, #1
45; THUMB2-NEXT:    bx lr
46entry:
47  %0 = load i16, i16* %a, align 2
48  %1 = load i16, i16* %b, align 2
49  %xor2 = xor i16 %1, %0
50  %2 = and i16 %xor2, 255
51  %cmp = icmp eq i16 %2, 0
52  ret i1 %cmp
53}
54
55define arm_aapcscc zeroext i1 @cmp_xor8_short_int(i16* nocapture readonly %a,
56                                                  i32* nocapture readonly %b) {
57; ARM-LABEL: cmp_xor8_short_int:
58; ARM:         ldrb r2, [r0]
59; ARM-NEXT:    mov r0, #0
60; ARM-NEXT:    ldrb r1, [r1]
61; ARM-NEXT:    teq r1, r2
62; ARM-NEXT:    movweq r0, #1
63; ARM-NEXT:    bx lr
64;
65; ARMEB-LABEL: cmp_xor8_short_int:
66; ARMEB:         ldrb r2, [r0, #1]
67; ARMEB-NEXT:    mov r0, #0
68; ARMEB-NEXT:    ldrb r1, [r1, #3]
69; ARMEB-NEXT:    teq r1, r2
70; ARMEB-NEXT:    movweq r0, #1
71; ARMEB-NEXT:    bx lr
72;
73; THUMB1-LABEL: cmp_xor8_short_int:
74; THUMB1:         ldrb r0, [r0]
75; THUMB1-NEXT:    ldrb r2, [r1]
76; THUMB1-NEXT:    eors r2, r0
77; THUMB1-NEXT:    movs r0, #1
78; THUMB1-NEXT:    movs r1, #0
79; THUMB1-NEXT:    cmp r2, #0
80; THUMB1-NEXT:    beq .LBB1_2
81; THUMB1-NEXT:  @ %bb.1: @ %entry
82; THUMB1-NEXT:    mov r0, r1
83; THUMB1-NEXT:  .LBB1_2: @ %entry
84; THUMB1-NEXT:    bx lr
85;
86; THUMB2-LABEL: cmp_xor8_short_int:
87; THUMB2:         ldrb r2, [r0]
88; THUMB2-NEXT:    movs r0, #0
89; THUMB2-NEXT:    ldrb r1, [r1]
90; THUMB2-NEXT:    teq.w r1, r2
91; THUMB2-NEXT:    it eq
92; THUMB2-NEXT:    moveq r0, #1
93; THUMB2-NEXT:    bx lr
94entry:
95  %0 = load i16, i16* %a, align 2
96  %conv = zext i16 %0 to i32
97  %1 = load i32, i32* %b, align 4
98  %xor = xor i32 %1, %conv
99  %and = and i32 %xor, 255
100  %cmp = icmp eq i32 %and, 0
101  ret i1 %cmp
102}
103
104define arm_aapcscc zeroext i1 @cmp_xor8_int_int(i32* nocapture readonly %a,
105                                                i32* nocapture readonly %b) {
106; ARM-LABEL: cmp_xor8_int_int:
107; ARM:         ldrb r2, [r0]
108; ARM-NEXT:    mov r0, #0
109; ARM-NEXT:    ldrb r1, [r1]
110; ARM-NEXT:    teq r1, r2
111; ARM-NEXT:    movweq r0, #1
112; ARM-NEXT:    bx lr
113;
114; ARMEB-LABEL: cmp_xor8_int_int:
115; ARMEB:         ldrb r2, [r0, #3]
116; ARMEB-NEXT:    mov r0, #0
117; ARMEB-NEXT:    ldrb r1, [r1, #3]
118; ARMEB-NEXT:    teq r1, r2
119; ARMEB-NEXT:    movweq r0, #1
120; ARMEB-NEXT:    bx lr
121;
122; THUMB1-LABEL: cmp_xor8_int_int:
123; THUMB1:         ldrb r0, [r0]
124; THUMB1-NEXT:    ldrb r2, [r1]
125; THUMB1-NEXT:    eors r2, r0
126; THUMB1-NEXT:    movs r0, #1
127; THUMB1-NEXT:    movs r1, #0
128; THUMB1-NEXT:    cmp r2, #0
129; THUMB1-NEXT:    beq .LBB2_2
130; THUMB1-NEXT:  @ %bb.1: @ %entry
131; THUMB1-NEXT:    mov r0, r1
132; THUMB1-NEXT:  .LBB2_2: @ %entry
133; THUMB1-NEXT:    bx lr
134;
135; THUMB2-LABEL: cmp_xor8_int_int:
136; THUMB2:         ldrb r2, [r0]
137; THUMB2-NEXT:    movs r0, #0
138; THUMB2-NEXT:    ldrb r1, [r1]
139; THUMB2-NEXT:    teq.w r1, r2
140; THUMB2-NEXT:    it eq
141; THUMB2-NEXT:    moveq r0, #1
142; THUMB2-NEXT:    bx lr
143entry:
144  %0 = load i32, i32* %a, align 4
145  %1 = load i32, i32* %b, align 4
146  %xor = xor i32 %1, %0
147  %and = and i32 %xor, 255
148  %cmp = icmp eq i32 %and, 0
149  ret i1 %cmp
150}
151
152define arm_aapcscc zeroext i1 @cmp_xor16(i32* nocapture readonly %a,
153                                         i32* nocapture readonly %b) {
154; ARM-LABEL: cmp_xor16:
155; ARM:         ldrh r2, [r0]
156; ARM-NEXT:    mov r0, #0
157; ARM-NEXT:    ldrh r1, [r1]
158; ARM-NEXT:    teq r1, r2
159; ARM-NEXT:    movweq r0, #1
160; ARM-NEXT:    bx lr
161;
162; ARMEB-LABEL: cmp_xor16:
163; ARMEB:         ldrh r2, [r0, #2]
164; ARMEB-NEXT:    mov r0, #0
165; ARMEB-NEXT:    ldrh r1, [r1, #2]
166; ARMEB-NEXT:    teq r1, r2
167; ARMEB-NEXT:    movweq r0, #1
168; ARMEB-NEXT:    bx lr
169;
170; THUMB1-LABEL: cmp_xor16:
171; THUMB1:         ldrh r0, [r0]
172; THUMB1-NEXT:    ldrh r2, [r1]
173; THUMB1-NEXT:    eors r2, r0
174; THUMB1-NEXT:    movs r0, #1
175; THUMB1-NEXT:    movs r1, #0
176; THUMB1-NEXT:    cmp r2, #0
177; THUMB1-NEXT:    beq .LBB3_2
178; THUMB1-NEXT:  @ %bb.1: @ %entry
179; THUMB1-NEXT:    mov r0, r1
180; THUMB1-NEXT:  .LBB3_2: @ %entry
181; THUMB1-NEXT:    bx lr
182;
183; THUMB2-LABEL: cmp_xor16:
184; THUMB2:         ldrh r2, [r0]
185; THUMB2-NEXT:    movs r0, #0
186; THUMB2-NEXT:    ldrh r1, [r1]
187; THUMB2-NEXT:    teq.w r1, r2
188; THUMB2-NEXT:    it eq
189; THUMB2-NEXT:    moveq r0, #1
190; THUMB2-NEXT:    bx lr
191entry:
192  %0 = load i32, i32* %a, align 4
193  %1 = load i32, i32* %b, align 4
194  %xor = xor i32 %1, %0
195  %and = and i32 %xor, 65535
196  %cmp = icmp eq i32 %and, 0
197  ret i1 %cmp
198}
199
200define arm_aapcscc zeroext i1 @cmp_or8_short_short(i16* nocapture readonly %a,
201                                                   i16* nocapture readonly %b) {
202; ARM-LABEL: cmp_or8_short_short:
203; ARM:         ldrb r0, [r0]
204; ARM-NEXT:    ldrb r1, [r1]
205; ARM-NEXT:    orrs r0, r1, r0
206; ARM-NEXT:    mov r0, #0
207; ARM-NEXT:    movweq r0, #1
208; ARM-NEXT:    bx lr
209;
210; ARMEB-LABEL: cmp_or8_short_short:
211; ARMEB:         ldrb r0, [r0, #1]
212; ARMEB-NEXT:    ldrb r1, [r1, #1]
213; ARMEB-NEXT:    orrs r0, r1, r0
214; ARMEB-NEXT:    mov r0, #0
215; ARMEB-NEXT:    movweq r0, #1
216; ARMEB-NEXT:    bx lr
217;
218; THUMB1-LABEL: cmp_or8_short_short:
219; THUMB1:         ldrb r0, [r0]
220; THUMB1-NEXT:    ldrb r2, [r1]
221; THUMB1-NEXT:    orrs r2, r0
222; THUMB1-NEXT:    movs r0, #1
223; THUMB1-NEXT:    movs r1, #0
224; THUMB1-NEXT:    cmp r2, #0
225; THUMB1-NEXT:    beq .LBB4_2
226; THUMB1-NEXT:  @ %bb.1: @ %entry
227; THUMB1-NEXT:    mov r0, r1
228; THUMB1-NEXT:  .LBB4_2: @ %entry
229; THUMB1-NEXT:    bx lr
230;
231; THUMB2-LABEL: cmp_or8_short_short:
232; THUMB2:         ldrb r0, [r0]
233; THUMB2-NEXT:    ldrb r1, [r1]
234; THUMB2-NEXT:    orrs r0, r1
235; THUMB2-NEXT:    mov.w r0, #0
236; THUMB2-NEXT:    it eq
237; THUMB2-NEXT:    moveq r0, #1
238; THUMB2-NEXT:    bx lr
239entry:
240  %0 = load i16, i16* %a, align 2
241  %1 = load i16, i16* %b, align 2
242  %or2 = or i16 %1, %0
243  %2 = and i16 %or2, 255
244  %cmp = icmp eq i16 %2, 0
245  ret i1 %cmp
246}
247
248define arm_aapcscc zeroext i1 @cmp_or8_short_int(i16* nocapture readonly %a,
249                                                 i32* nocapture readonly %b) {
250; ARM-LABEL: cmp_or8_short_int:
251; ARM:         ldrb r0, [r0]
252; ARM-NEXT:    ldrb r1, [r1]
253; ARM-NEXT:    orrs r0, r1, r0
254; ARM-NEXT:    mov r0, #0
255; ARM-NEXT:    movweq r0, #1
256; ARM-NEXT:    bx lr
257;
258; ARMEB-LABEL: cmp_or8_short_int:
259; ARMEB:         ldrb r0, [r0, #1]
260; ARMEB-NEXT:    ldrb r1, [r1, #3]
261; ARMEB-NEXT:    orrs r0, r1, r0
262; ARMEB-NEXT:    mov r0, #0
263; ARMEB-NEXT:    movweq r0, #1
264; ARMEB-NEXT:    bx lr
265;
266; THUMB1-LABEL: cmp_or8_short_int:
267; THUMB1:         ldrb r0, [r0]
268; THUMB1-NEXT:    ldrb r2, [r1]
269; THUMB1-NEXT:    orrs r2, r0
270; THUMB1-NEXT:    movs r0, #1
271; THUMB1-NEXT:    movs r1, #0
272; THUMB1-NEXT:    cmp r2, #0
273; THUMB1-NEXT:    beq .LBB5_2
274; THUMB1-NEXT:  @ %bb.1: @ %entry
275; THUMB1-NEXT:    mov r0, r1
276; THUMB1-NEXT:  .LBB5_2: @ %entry
277; THUMB1-NEXT:    bx lr
278;
279; THUMB2-LABEL: cmp_or8_short_int:
280; THUMB2:         ldrb r0, [r0]
281; THUMB2-NEXT:    ldrb r1, [r1]
282; THUMB2-NEXT:    orrs r0, r1
283; THUMB2-NEXT:    mov.w r0, #0
284; THUMB2-NEXT:    it eq
285; THUMB2-NEXT:    moveq r0, #1
286; THUMB2-NEXT:    bx lr
287entry:
288  %0 = load i16, i16* %a, align 2
289  %conv = zext i16 %0 to i32
290  %1 = load i32, i32* %b, align 4
291  %or = or i32 %1, %conv
292  %and = and i32 %or, 255
293  %cmp = icmp eq i32 %and, 0
294  ret i1 %cmp
295}
296
297define arm_aapcscc zeroext i1 @cmp_or8_int_int(i32* nocapture readonly %a,
298                                               i32* nocapture readonly %b) {
299; ARM-LABEL: cmp_or8_int_int:
300; ARM:         ldrb r0, [r0]
301; ARM-NEXT:    ldrb r1, [r1]
302; ARM-NEXT:    orrs r0, r1, r0
303; ARM-NEXT:    mov r0, #0
304; ARM-NEXT:    movweq r0, #1
305; ARM-NEXT:    bx lr
306;
307; ARMEB-LABEL: cmp_or8_int_int:
308; ARMEB:         ldrb r0, [r0, #3]
309; ARMEB-NEXT:    ldrb r1, [r1, #3]
310; ARMEB-NEXT:    orrs r0, r1, r0
311; ARMEB-NEXT:    mov r0, #0
312; ARMEB-NEXT:    movweq r0, #1
313; ARMEB-NEXT:    bx lr
314;
315; THUMB1-LABEL: cmp_or8_int_int:
316; THUMB1:         ldrb r0, [r0]
317; THUMB1-NEXT:    ldrb r2, [r1]
318; THUMB1-NEXT:    orrs r2, r0
319; THUMB1-NEXT:    movs r0, #1
320; THUMB1-NEXT:    movs r1, #0
321; THUMB1-NEXT:    cmp r2, #0
322; THUMB1-NEXT:    beq .LBB6_2
323; THUMB1-NEXT:  @ %bb.1: @ %entry
324; THUMB1-NEXT:    mov r0, r1
325; THUMB1-NEXT:  .LBB6_2: @ %entry
326; THUMB1-NEXT:    bx lr
327;
328; THUMB2-LABEL: cmp_or8_int_int:
329; THUMB2:         ldrb r0, [r0]
330; THUMB2-NEXT:    ldrb r1, [r1]
331; THUMB2-NEXT:    orrs r0, r1
332; THUMB2-NEXT:    mov.w r0, #0
333; THUMB2-NEXT:    it eq
334; THUMB2-NEXT:    moveq r0, #1
335; THUMB2-NEXT:    bx lr
336entry:
337  %0 = load i32, i32* %a, align 4
338  %1 = load i32, i32* %b, align 4
339  %or = or i32 %1, %0
340  %and = and i32 %or, 255
341  %cmp = icmp eq i32 %and, 0
342  ret i1 %cmp
343}
344
345define arm_aapcscc zeroext i1 @cmp_or16(i32* nocapture readonly %a,
346                                        i32* nocapture readonly %b) {
347; ARM-LABEL: cmp_or16:
348; ARM:         ldrh r0, [r0]
349; ARM-NEXT:    ldrh r1, [r1]
350; ARM-NEXT:    orrs r0, r1, r0
351; ARM-NEXT:    mov r0, #0
352; ARM-NEXT:    movweq r0, #1
353; ARM-NEXT:    bx lr
354;
355; ARMEB-LABEL: cmp_or16:
356; ARMEB:         ldrh r0, [r0, #2]
357; ARMEB-NEXT:    ldrh r1, [r1, #2]
358; ARMEB-NEXT:    orrs r0, r1, r0
359; ARMEB-NEXT:    mov r0, #0
360; ARMEB-NEXT:    movweq r0, #1
361; ARMEB-NEXT:    bx lr
362;
363; THUMB1-LABEL: cmp_or16:
364; THUMB1:         ldrh r0, [r0]
365; THUMB1-NEXT:    ldrh r2, [r1]
366; THUMB1-NEXT:    orrs r2, r0
367; THUMB1-NEXT:    movs r0, #1
368; THUMB1-NEXT:    movs r1, #0
369; THUMB1-NEXT:    cmp r2, #0
370; THUMB1-NEXT:    beq .LBB7_2
371; THUMB1-NEXT:  @ %bb.1: @ %entry
372; THUMB1-NEXT:    mov r0, r1
373; THUMB1-NEXT:  .LBB7_2: @ %entry
374; THUMB1-NEXT:    bx lr
375;
376; THUMB2-LABEL: cmp_or16:
377; THUMB2:         ldrh r0, [r0]
378; THUMB2-NEXT:    ldrh r1, [r1]
379; THUMB2-NEXT:    orrs r0, r1
380; THUMB2-NEXT:    mov.w r0, #0
381; THUMB2-NEXT:    it eq
382; THUMB2-NEXT:    moveq r0, #1
383; THUMB2-NEXT:    bx lr
384entry:
385  %0 = load i32, i32* %a, align 4
386  %1 = load i32, i32* %b, align 4
387  %or = or i32 %1, %0
388  %and = and i32 %or, 65535
389  %cmp = icmp eq i32 %and, 0
390  ret i1 %cmp
391}
392
393define arm_aapcscc zeroext i1 @cmp_and8_short_short(i16* nocapture readonly %a,
394                                                    i16* nocapture readonly %b) {
395; ARM-LABEL: cmp_and8_short_short:
396; ARM:         ldrb r2, [r0]
397; ARM-NEXT:    mov r0, #0
398; ARM-NEXT:    ldrb r1, [r1]
399; ARM-NEXT:    tst r2, r1
400; ARM-NEXT:    movweq r0, #1
401; ARM-NEXT:    bx lr
402;
403; ARMEB-LABEL: cmp_and8_short_short:
404; ARMEB:         ldrb r2, [r0, #1]
405; ARMEB-NEXT:    mov r0, #0
406; ARMEB-NEXT:    ldrb r1, [r1, #1]
407; ARMEB-NEXT:    tst r2, r1
408; ARMEB-NEXT:    movweq r0, #1
409; ARMEB-NEXT:    bx lr
410;
411; THUMB1-LABEL: cmp_and8_short_short:
412; THUMB1:         ldrb r2, [r1]
413; THUMB1-NEXT:    ldrb r3, [r0]
414; THUMB1-NEXT:    movs r0, #1
415; THUMB1-NEXT:    movs r1, #0
416; THUMB1-NEXT:    tst r3, r2
417; THUMB1-NEXT:    beq .LBB8_2
418; THUMB1-NEXT:  @ %bb.1: @ %entry
419; THUMB1-NEXT:    mov r0, r1
420; THUMB1-NEXT:  .LBB8_2: @ %entry
421; THUMB1-NEXT:    bx lr
422;
423; THUMB2-LABEL: cmp_and8_short_short:
424; THUMB2:         ldrb r2, [r0]
425; THUMB2-NEXT:    movs r0, #0
426; THUMB2-NEXT:    ldrb r1, [r1]
427; THUMB2-NEXT:    tst r2, r1
428; THUMB2-NEXT:    it eq
429; THUMB2-NEXT:    moveq r0, #1
430; THUMB2-NEXT:    bx lr
431entry:
432  %0 = load i16, i16* %a, align 2
433  %1 = load i16, i16* %b, align 2
434  %and3 = and i16 %0, 255
435  %2 = and i16 %and3, %1
436  %cmp = icmp eq i16 %2, 0
437  ret i1 %cmp
438}
439
440define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a,
441                                                  i32* nocapture readonly %b) {
442; ARM-LABEL: cmp_and8_short_int:
443; ARM:         ldrb r2, [r0]
444; ARM-NEXT:    mov r0, #0
445; ARM-NEXT:    ldrb r1, [r1]
446; ARM-NEXT:    tst r1, r2
447; ARM-NEXT:    movweq r0, #1
448; ARM-NEXT:    bx lr
449;
450; ARMEB-LABEL: cmp_and8_short_int:
451; ARMEB:         ldrb r2, [r0, #1]
452; ARMEB-NEXT:    mov r0, #0
453; ARMEB-NEXT:    ldrb r1, [r1, #3]
454; ARMEB-NEXT:    tst r1, r2
455; ARMEB-NEXT:    movweq r0, #1
456; ARMEB-NEXT:    bx lr
457;
458; THUMB1-LABEL: cmp_and8_short_int:
459; THUMB1:         ldrb r2, [r0]
460; THUMB1-NEXT:    ldrb r3, [r1]
461; THUMB1-NEXT:    movs r0, #1
462; THUMB1-NEXT:    movs r1, #0
463; THUMB1-NEXT:    tst r3, r2
464; THUMB1-NEXT:    beq .LBB9_2
465; THUMB1-NEXT:  @ %bb.1: @ %entry
466; THUMB1-NEXT:    mov r0, r1
467; THUMB1-NEXT:  .LBB9_2: @ %entry
468; THUMB1-NEXT:    bx lr
469;
470; THUMB2-LABEL: cmp_and8_short_int:
471; THUMB2:         ldrb r2, [r0]
472; THUMB2-NEXT:    movs r0, #0
473; THUMB2-NEXT:    ldrb r1, [r1]
474; THUMB2-NEXT:    tst r1, r2
475; THUMB2-NEXT:    it eq
476; THUMB2-NEXT:    moveq r0, #1
477; THUMB2-NEXT:    bx lr
478entry:
479  %0 = load i16, i16* %a, align 2
480  %1 = load i32, i32* %b, align 4
481  %2 = and i16 %0, 255
482  %and = zext i16 %2 to i32
483  %and1 = and i32 %1, %and
484  %cmp = icmp eq i32 %and1, 0
485  ret i1 %cmp
486}
487
488define arm_aapcscc zeroext i1 @cmp_and8_int_int(i32* nocapture readonly %a,
489                                                i32* nocapture readonly %b) {
490; ARM-LABEL: cmp_and8_int_int:
491; ARM:         ldrb r2, [r0]
492; ARM-NEXT:    mov r0, #0
493; ARM-NEXT:    ldrb r1, [r1]
494; ARM-NEXT:    tst r2, r1
495; ARM-NEXT:    movweq r0, #1
496; ARM-NEXT:    bx lr
497;
498; ARMEB-LABEL: cmp_and8_int_int:
499; ARMEB:         ldrb r2, [r0, #3]
500; ARMEB-NEXT:    mov r0, #0
501; ARMEB-NEXT:    ldrb r1, [r1, #3]
502; ARMEB-NEXT:    tst r2, r1
503; ARMEB-NEXT:    movweq r0, #1
504; ARMEB-NEXT:    bx lr
505;
506; THUMB1-LABEL: cmp_and8_int_int:
507; THUMB1:         ldrb r2, [r1]
508; THUMB1-NEXT:    ldrb r3, [r0]
509; THUMB1-NEXT:    movs r0, #1
510; THUMB1-NEXT:    movs r1, #0
511; THUMB1-NEXT:    tst r3, r2
512; THUMB1-NEXT:    beq .LBB10_2
513; THUMB1-NEXT:  @ %bb.1: @ %entry
514; THUMB1-NEXT:    mov r0, r1
515; THUMB1-NEXT:  .LBB10_2: @ %entry
516; THUMB1-NEXT:    bx lr
517;
518; THUMB2-LABEL: cmp_and8_int_int:
519; THUMB2:         ldrb r2, [r0]
520; THUMB2-NEXT:    movs r0, #0
521; THUMB2-NEXT:    ldrb r1, [r1]
522; THUMB2-NEXT:    tst r2, r1
523; THUMB2-NEXT:    it eq
524; THUMB2-NEXT:    moveq r0, #1
525; THUMB2-NEXT:    bx lr
526entry:
527  %0 = load i32, i32* %a, align 4
528  %1 = load i32, i32* %b, align 4
529  %and = and i32 %0, 255
530  %and1 = and i32 %and, %1
531  %cmp = icmp eq i32 %and1, 0
532  ret i1 %cmp
533}
534
535define arm_aapcscc zeroext i1 @cmp_and16(i32* nocapture readonly %a,
536                                         i32* nocapture readonly %b) {
537; ARM-LABEL: cmp_and16:
538; ARM:         ldrh r2, [r0]
539; ARM-NEXT:    mov r0, #0
540; ARM-NEXT:    ldrh r1, [r1]
541; ARM-NEXT:    tst r2, r1
542; ARM-NEXT:    movweq r0, #1
543; ARM-NEXT:    bx lr
544;
545; ARMEB-LABEL: cmp_and16:
546; ARMEB:         ldrh r2, [r0, #2]
547; ARMEB-NEXT:    mov r0, #0
548; ARMEB-NEXT:    ldrh r1, [r1, #2]
549; ARMEB-NEXT:    tst r2, r1
550; ARMEB-NEXT:    movweq r0, #1
551; ARMEB-NEXT:    bx lr
552;
553; THUMB1-LABEL: cmp_and16:
554; THUMB1:         ldrh r2, [r1]
555; THUMB1-NEXT:    ldrh r3, [r0]
556; THUMB1-NEXT:    movs r0, #1
557; THUMB1-NEXT:    movs r1, #0
558; THUMB1-NEXT:    tst r3, r2
559; THUMB1-NEXT:    beq .LBB11_2
560; THUMB1-NEXT:  @ %bb.1: @ %entry
561; THUMB1-NEXT:    mov r0, r1
562; THUMB1-NEXT:  .LBB11_2: @ %entry
563; THUMB1-NEXT:    bx lr
564;
565; THUMB2-LABEL: cmp_and16:
566; THUMB2:         ldrh r2, [r0]
567; THUMB2-NEXT:    movs r0, #0
568; THUMB2-NEXT:    ldrh r1, [r1]
569; THUMB2-NEXT:    tst r2, r1
570; THUMB2-NEXT:    it eq
571; THUMB2-NEXT:    moveq r0, #1
572; THUMB2-NEXT:    bx lr
573entry:
574  %0 = load i32, i32* %a, align 4
575  %1 = load i32, i32* %b, align 4
576  %and = and i32 %0, 65535
577  %and1 = and i32 %and, %1
578  %cmp = icmp eq i32 %and1, 0
579  ret i1 %cmp
580}
581
582define arm_aapcscc i32 @add_and16(i32* nocapture readonly %a, i32 %y, i32 %z) {
583; ARM-LABEL: add_and16:
584; ARM:         add r1, r1, r2
585; ARM-NEXT:    ldrh r0, [r0]
586; ARM-NEXT:    uxth r1, r1
587; ARM-NEXT:    orr r0, r0, r1
588; ARM-NEXT:    bx lr
589;
590; ARMEB-LABEL: add_and16:
591; ARMEB:         add r1, r1, r2
592; ARMEB-NEXT:    ldrh r0, [r0, #2]
593; ARMEB-NEXT:    uxth r1, r1
594; ARMEB-NEXT:    orr r0, r0, r1
595; ARMEB-NEXT:    bx lr
596;
597; THUMB1-LABEL: add_and16:
598; THUMB1:         adds r1, r1, r2
599; THUMB1-NEXT:    uxth r1, r1
600; THUMB1-NEXT:    ldrh r0, [r0]
601; THUMB1-NEXT:    orrs r0, r1
602; THUMB1-NEXT:    bx lr
603;
604; THUMB2-LABEL: add_and16:
605; THUMB2:         add r1, r2
606; THUMB2-NEXT:    ldrh r0, [r0]
607; THUMB2-NEXT:    uxth r1, r1
608; THUMB2-NEXT:    orrs r0, r1
609; THUMB2-NEXT:    bx lr
610entry:
611  %x = load i32, i32* %a, align 4
612  %add = add i32 %y, %z
613  %or = or i32 %x, %add
614  %and = and i32 %or, 65535
615  ret i32 %and
616}
617
618define arm_aapcscc i32 @test1(i32* %a, i32* %b, i32 %x, i32 %y) {
619; ARM-LABEL: test1:
620; ARM:         mul r2, r2, r3
621; ARM-NEXT:    ldrh r1, [r1]
622; ARM-NEXT:    ldrh r0, [r0]
623; ARM-NEXT:    eor r0, r0, r1
624; ARM-NEXT:    uxth r1, r2
625; ARM-NEXT:    orr r0, r0, r1
626; ARM-NEXT:    bx lr
627;
628; ARMEB-LABEL: test1:
629; ARMEB:         mul r2, r2, r3
630; ARMEB-NEXT:    ldrh r1, [r1, #2]
631; ARMEB-NEXT:    ldrh r0, [r0, #2]
632; ARMEB-NEXT:    eor r0, r0, r1
633; ARMEB-NEXT:    uxth r1, r2
634; ARMEB-NEXT:    orr r0, r0, r1
635; ARMEB-NEXT:    bx lr
636;
637; THUMB1-LABEL: test1:
638; THUMB1:         ldrh r1, [r1]
639; THUMB1-NEXT:    ldrh r4, [r0]
640; THUMB1-NEXT:    eors r4, r1
641; THUMB1-NEXT:    muls r2, r3, r2
642; THUMB1-NEXT:    uxth r0, r2
643; THUMB1-NEXT:    orrs r0, r4
644; THUMB1-NEXT:    pop
645;
646; THUMB2-LABEL: test1:
647; THUMB2:         ldrh r1, [r1]
648; THUMB2-NEXT:    ldrh r0, [r0]
649; THUMB2-NEXT:    eors r0, r1
650; THUMB2-NEXT:    mul r1, r2, r3
651; THUMB2-NEXT:    uxth r1, r1
652; THUMB2-NEXT:    orrs r0, r1
653; THUMB2-NEXT:    bx lr
654entry:
655  %0 = load i32, i32* %a, align 4
656  %1 = load i32, i32* %b, align 4
657  %mul = mul i32 %x, %y
658  %xor = xor i32 %0, %1
659  %or = or i32 %xor, %mul
660  %and = and i32 %or, 65535
661  ret i32 %and
662}
663
664define arm_aapcscc i32 @test2(i32* %a, i32* %b, i32 %x, i32 %y) {
665; ARM-LABEL: test2:
666; ARM:         ldr r1, [r1]
667; ARM-NEXT:    ldr r0, [r0]
668; ARM-NEXT:    mul r1, r2, r1
669; ARM-NEXT:    eor r0, r0, r3
670; ARM-NEXT:    orr r0, r0, r1
671; ARM-NEXT:    uxth r0, r0
672; ARM-NEXT:    bx lr
673;
674; ARMEB-LABEL: test2:
675; ARMEB:         ldr r1, [r1]
676; ARMEB-NEXT:    ldr r0, [r0]
677; ARMEB-NEXT:    mul r1, r2, r1
678; ARMEB-NEXT:    eor r0, r0, r3
679; ARMEB-NEXT:    orr r0, r0, r1
680; ARMEB-NEXT:    uxth r0, r0
681; ARMEB-NEXT:    bx lr
682;
683; THUMB1-LABEL: test2:
684; THUMB1:         ldr r1, [r1]
685; THUMB1-NEXT:    muls r1, r2, r1
686; THUMB1-NEXT:    ldr r0, [r0]
687; THUMB1-NEXT:    eors r0, r3
688; THUMB1-NEXT:    orrs r0, r1
689; THUMB1-NEXT:    uxth r0, r0
690; THUMB1-NEXT:    bx lr
691;
692; THUMB2-LABEL: test2:
693; THUMB2:         ldr r1, [r1]
694; THUMB2-NEXT:    ldr r0, [r0]
695; THUMB2-NEXT:    muls r1, r2, r1
696; THUMB2-NEXT:    eors r0, r3
697; THUMB2-NEXT:    orrs r0, r1
698; THUMB2-NEXT:    uxth r0, r0
699; THUMB2-NEXT:    bx lr
700entry:
701  %0 = load i32, i32* %a, align 4
702  %1 = load i32, i32* %b, align 4
703  %mul = mul i32 %x, %1
704  %xor = xor i32 %0, %y
705  %or = or i32 %xor, %mul
706  %and = and i32 %or, 65535
707  ret i32 %and
708}
709
710define arm_aapcscc i32 @test3(i32* %a, i32* %b, i32 %x, i16* %y) {
711; ARM-LABEL: test3:
712; ARM:         ldr r0, [r0]
713; ARM-NEXT:    mul r1, r2, r0
714; ARM-NEXT:    ldrh r2, [r3]
715; ARM-NEXT:    eor r0, r0, r2
716; ARM-NEXT:    orr r0, r0, r1
717; ARM-NEXT:    uxth r0, r0
718; ARM-NEXT:    bx lr
719;
720; ARMEB-LABEL: test3:
721; ARMEB:         ldr r0, [r0]
722; ARMEB-NEXT:    mul r1, r2, r0
723; ARMEB-NEXT:    ldrh r2, [r3]
724; ARMEB-NEXT:    eor r0, r0, r2
725; ARMEB-NEXT:    orr r0, r0, r1
726; ARMEB-NEXT:    uxth r0, r0
727; ARMEB-NEXT:    bx lr
728;
729; THUMB1-LABEL: test3:
730; THUMB1:         ldr r0, [r0]
731; THUMB1-NEXT:    muls r2, r0, r2
732; THUMB1-NEXT:    ldrh r1, [r3]
733; THUMB1-NEXT:    eors r1, r0
734; THUMB1-NEXT:    orrs r1, r2
735; THUMB1-NEXT:    uxth r0, r1
736; THUMB1-NEXT:    bx lr
737;
738; THUMB2-LABEL: test3:
739; THUMB2:         ldr r0, [r0]
740; THUMB2-NEXT:    mul r1, r2, r0
741; THUMB2-NEXT:    ldrh r2, [r3]
742; THUMB2-NEXT:    eors r0, r2
743; THUMB2-NEXT:    orrs r0, r1
744; THUMB2-NEXT:    uxth r0, r0
745; THUMB2-NEXT:    bx lr
746entry:
747  %0 = load i32, i32* %a, align 4
748  %1 = load i16, i16* %y, align 4
749  %2 = zext i16 %1 to i32
750  %mul = mul i32 %x, %0
751  %xor = xor i32 %0, %2
752  %or = or i32 %xor, %mul
753  %and = and i32 %or, 65535
754  ret i32 %and
755}
756
757define arm_aapcscc i32 @test4(i32* %a, i32* %b, i32 %x, i32 %y) {
758; ARM-LABEL: test4:
759; ARM:         mul r2, r2, r3
760; ARM-NEXT:    ldrh r1, [r1]
761; ARM-NEXT:    ldrh r0, [r0]
762; ARM-NEXT:    eor r0, r0, r1
763; ARM-NEXT:    uxth r1, r2
764; ARM-NEXT:    orr r0, r0, r1
765; ARM-NEXT:    bx lr
766;
767; ARMEB-LABEL: test4:
768; ARMEB:         mul r2, r2, r3
769; ARMEB-NEXT:    ldrh r1, [r1, #2]
770; ARMEB-NEXT:    ldrh r0, [r0, #2]
771; ARMEB-NEXT:    eor r0, r0, r1
772; ARMEB-NEXT:    uxth r1, r2
773; ARMEB-NEXT:    orr r0, r0, r1
774; ARMEB-NEXT:    bx lr
775;
776; THUMB1-LABEL: test4:
777; THUMB1:         ldrh r1, [r1]
778; THUMB1-NEXT:    ldrh r4, [r0]
779; THUMB1-NEXT:    eors r4, r1
780; THUMB1-NEXT:    muls r2, r3, r2
781; THUMB1-NEXT:    uxth r0, r2
782; THUMB1-NEXT:    orrs r0, r4
783; THUMB1-NEXT:    pop
784;
785; THUMB2-LABEL: test4:
786; THUMB2:         ldrh r1, [r1]
787; THUMB2-NEXT:    ldrh r0, [r0]
788; THUMB2-NEXT:    eors r0, r1
789; THUMB2-NEXT:    mul r1, r2, r3
790; THUMB2-NEXT:    uxth r1, r1
791; THUMB2-NEXT:    orrs r0, r1
792; THUMB2-NEXT:    bx lr
793entry:
794  %0 = load i32, i32* %a, align 4
795  %1 = load i32, i32* %b, align 4
796  %mul = mul i32 %x, %y
797  %xor = xor i32 %0, %1
798  %or = or i32 %xor, %mul
799  %and = and i32 %or, 65535
800  ret i32 %and
801}
802
803define arm_aapcscc i32 @test5(i32* %a, i32* %b, i32 %x, i16 zeroext %y) {
804; ARM-LABEL: test5:
805; ARM:         ldr r1, [r1]
806; ARM-NEXT:    ldrh r0, [r0]
807; ARM-NEXT:    mul r1, r2, r1
808; ARM-NEXT:    eor r0, r0, r3
809; ARM-NEXT:    uxth r1, r1
810; ARM-NEXT:    orr r0, r0, r1
811; ARM-NEXT:    bx lr
812;
813; ARMEB-LABEL: test5:
814; ARMEB:         ldr r1, [r1]
815; ARMEB-NEXT:    ldrh r0, [r0, #2]
816; ARMEB-NEXT:    mul r1, r2, r1
817; ARMEB-NEXT:    eor r0, r0, r3
818; ARMEB-NEXT:    uxth r1, r1
819; ARMEB-NEXT:    orr r0, r0, r1
820; ARMEB-NEXT:    bx lr
821;
822; THUMB1-LABEL: test5:
823; THUMB1:         ldrh r4, [r0]
824; THUMB1-NEXT:    eors r4, r3
825; THUMB1-NEXT:    ldr r0, [r1]
826; THUMB1-NEXT:    muls r0, r2, r0
827; THUMB1-NEXT:    uxth r0, r0
828; THUMB1-NEXT:    orrs r0, r4
829; THUMB1-NEXT:    pop
830;
831; THUMB2-LABEL: test5:
832; THUMB2:         ldr r1, [r1]
833; THUMB2-NEXT:    ldrh r0, [r0]
834; THUMB2-NEXT:    muls r1, r2, r1
835; THUMB2-NEXT:    eors r0, r3
836; THUMB2-NEXT:    uxth r1, r1
837; THUMB2-NEXT:    orrs r0, r1
838; THUMB2-NEXT:    bx lr
839entry:
840  %0 = load i32, i32* %a, align 4
841  %1 = load i32, i32* %b, align 4
842  %mul = mul i32 %x, %1
843  %ext = zext i16 %y to i32
844  %xor = xor i32 %0, %ext
845  %or = or i32 %xor, %mul
846  %and = and i32 %or, 65535
847  ret i32 %and
848}
849
850define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
851; ARM-LABEL: test6:
852; ARM:       @ %bb.0: @ %entry
853; ARM-NEXT:    ldrb r0, [r0]
854; ARM-NEXT:    uxtb r2, r2
855; ARM-NEXT:    and r1, r0, r1
856; ARM-NEXT:    mov r0, #0
857; ARM-NEXT:    cmp r1, r2
858; ARM-NEXT:    movweq r0, #1
859; ARM-NEXT:    bx lr
860;
861; ARMEB-LABEL: test6:
862; ARMEB:       @ %bb.0: @ %entry
863; ARMEB-NEXT:    ldrb r0, [r0]
864; ARMEB-NEXT:    uxtb r2, r2
865; ARMEB-NEXT:    and r1, r0, r1
866; ARMEB-NEXT:    mov r0, #0
867; ARMEB-NEXT:    cmp r1, r2
868; ARMEB-NEXT:    movweq r0, #1
869; ARMEB-NEXT:    bx lr
870;
871; THUMB1-LABEL: test6:
872; THUMB1:       @ %bb.0: @ %entry
873; THUMB1-NEXT:    ldrb r3, [r0]
874; THUMB1-NEXT:    ands r3, r1
875; THUMB1-NEXT:    uxtb r2, r2
876; THUMB1-NEXT:    movs r0, #1
877; THUMB1-NEXT:    movs r1, #0
878; THUMB1-NEXT:    cmp r3, r2
879; THUMB1-NEXT:    beq .LBB18_2
880; THUMB1-NEXT:  @ %bb.1: @ %entry
881; THUMB1-NEXT:    mov r0, r1
882; THUMB1-NEXT:  .LBB18_2: @ %entry
883; THUMB1-NEXT:    bx lr
884;
885; THUMB2-LABEL: test6:
886; THUMB2:       @ %bb.0: @ %entry
887; THUMB2-NEXT:    ldrb r0, [r0]
888; THUMB2-NEXT:    uxtb r2, r2
889; THUMB2-NEXT:    ands r1, r0
890; THUMB2-NEXT:    movs r0, #0
891; THUMB2-NEXT:    cmp r1, r2
892; THUMB2-NEXT:    it eq
893; THUMB2-NEXT:    moveq r0, #1
894; THUMB2-NEXT:    bx lr
895entry:
896  %0 = load i8, i8* %x, align 4
897  %1 = and i8 %0, %y
898  %2 = icmp eq i8 %1, %z
899  ret i1 %2
900}
901
902define arm_aapcscc i1 @test7(i16* %x, i16 %y, i8 %z) {
903; ARM-LABEL: test7:
904; ARM:       @ %bb.0: @ %entry
905; ARM-NEXT:    ldrb r0, [r0]
906; ARM-NEXT:    uxtb r2, r2
907; ARM-NEXT:    and r1, r0, r1
908; ARM-NEXT:    mov r0, #0
909; ARM-NEXT:    cmp r1, r2
910; ARM-NEXT:    movweq r0, #1
911; ARM-NEXT:    bx lr
912;
913; ARMEB-LABEL: test7:
914; ARMEB:       @ %bb.0: @ %entry
915; ARMEB-NEXT:    ldrb r0, [r0, #1]
916; ARMEB-NEXT:    uxtb r2, r2
917; ARMEB-NEXT:    and r1, r0, r1
918; ARMEB-NEXT:    mov r0, #0
919; ARMEB-NEXT:    cmp r1, r2
920; ARMEB-NEXT:    movweq r0, #1
921; ARMEB-NEXT:    bx lr
922;
923; THUMB1-LABEL: test7:
924; THUMB1:       @ %bb.0: @ %entry
925; THUMB1-NEXT:    ldrb r3, [r0]
926; THUMB1-NEXT:    ands r3, r1
927; THUMB1-NEXT:    uxtb r2, r2
928; THUMB1-NEXT:    movs r0, #1
929; THUMB1-NEXT:    movs r1, #0
930; THUMB1-NEXT:    cmp r3, r2
931; THUMB1-NEXT:    beq .LBB19_2
932; THUMB1-NEXT:  @ %bb.1: @ %entry
933; THUMB1-NEXT:    mov r0, r1
934; THUMB1-NEXT:  .LBB19_2: @ %entry
935; THUMB1-NEXT:    bx lr
936;
937; THUMB2-LABEL: test7:
938; THUMB2:       @ %bb.0: @ %entry
939; THUMB2-NEXT:    ldrb r0, [r0]
940; THUMB2-NEXT:    uxtb r2, r2
941; THUMB2-NEXT:    ands r1, r0
942; THUMB2-NEXT:    movs r0, #0
943; THUMB2-NEXT:    cmp r1, r2
944; THUMB2-NEXT:    it eq
945; THUMB2-NEXT:    moveq r0, #1
946; THUMB2-NEXT:    bx lr
947entry:
948  %0 = load i16, i16* %x, align 4
949  %1 = and i16 %0, %y
950  %2 = trunc i16 %1 to i8
951  %3 = icmp eq i8 %2, %z
952  ret i1 %3
953}
954
955define arm_aapcscc void @test8(i32* nocapture %p) {
956; ARM-LABEL: test8:
957; ARM:       @ %bb.0: @ %entry
958; ARM-NEXT:    ldrb r1, [r0]
959; ARM-NEXT:    eor r1, r1, #255
960; ARM-NEXT:    str r1, [r0]
961; ARM-NEXT:    bx lr
962;
963; ARMEB-LABEL: test8:
964; ARMEB:       @ %bb.0: @ %entry
965; ARMEB-NEXT:    ldrb r1, [r0, #3]
966; ARMEB-NEXT:    eor r1, r1, #255
967; ARMEB-NEXT:    str r1, [r0]
968; ARMEB-NEXT:    bx lr
969;
970; THUMB1-LABEL: test8:
971; THUMB1:       @ %bb.0: @ %entry
972; THUMB1-NEXT:    ldrb r1, [r0]
973; THUMB1-NEXT:    movs r2, #255
974; THUMB1-NEXT:    eors r2, r1
975; THUMB1-NEXT:    str r2, [r0]
976; THUMB1-NEXT:    bx lr
977;
978; THUMB2-LABEL: test8:
979; THUMB2:       @ %bb.0: @ %entry
980; THUMB2-NEXT:    ldrb r1, [r0]
981; THUMB2-NEXT:    eor r1, r1, #255
982; THUMB2-NEXT:    str r1, [r0]
983; THUMB2-NEXT:    bx lr
984entry:
985  %0 = load i32, i32* %p, align 4
986  %neg = and i32 %0, 255
987  %and = xor i32 %neg, 255
988  store i32 %and, i32* %p, align 4
989  ret void
990}
991
992define arm_aapcscc void @test9(i32* nocapture %p) {
993; ARM-LABEL: test9:
994; ARM:       @ %bb.0: @ %entry
995; ARM-NEXT:    ldrb r1, [r0]
996; ARM-NEXT:    eor r1, r1, #255
997; ARM-NEXT:    str r1, [r0]
998; ARM-NEXT:    bx lr
999;
1000; ARMEB-LABEL: test9:
1001; ARMEB:       @ %bb.0: @ %entry
1002; ARMEB-NEXT:    ldrb r1, [r0, #3]
1003; ARMEB-NEXT:    eor r1, r1, #255
1004; ARMEB-NEXT:    str r1, [r0]
1005; ARMEB-NEXT:    bx lr
1006;
1007; THUMB1-LABEL: test9:
1008; THUMB1:       @ %bb.0: @ %entry
1009; THUMB1-NEXT:    ldrb r1, [r0]
1010; THUMB1-NEXT:    movs r2, #255
1011; THUMB1-NEXT:    eors r2, r1
1012; THUMB1-NEXT:    str r2, [r0]
1013; THUMB1-NEXT:    bx lr
1014;
1015; THUMB2-LABEL: test9:
1016; THUMB2:       @ %bb.0: @ %entry
1017; THUMB2-NEXT:    ldrb r1, [r0]
1018; THUMB2-NEXT:    eor r1, r1, #255
1019; THUMB2-NEXT:    str r1, [r0]
1020; THUMB2-NEXT:    bx lr
1021entry:
1022  %0 = load i32, i32* %p, align 4
1023  %neg = xor i32 %0, -1
1024  %and = and i32 %neg, 255
1025  store i32 %and, i32* %p, align 4
1026  ret void
1027}
1028
1029; ARM-LABEL: test10:
1030; ARM:       @ %bb.0: @ %entry
1031; ARM-NEXT:    ldrb r1, [r0]
1032; ARM-NEXT:    eor r1, r1, #255
1033; ARM-NEXT:    str r1, [r0]
1034; ARM-NEXT:    bx lr
1035;
1036; ARMEB-LABEL: test10:
1037; ARMEB:       @ %bb.0: @ %entry
1038; ARMEB-NEXT:    ldrb r1, [r0, #3]
1039; ARMEB-NEXT:    eor r1, r1, #255
1040; ARMEB-NEXT:    str r1, [r0]
1041; ARMEB-NEXT:    bx lr
1042;
1043; THUMB1-LABEL: test10:
1044; THUMB1:       @ %bb.0: @ %entry
1045; THUMB1-NEXT:    ldrb r1, [r0]
1046; THUMB1-NEXT:    movs r2, #255
1047; THUMB1-NEXT:    eors r2, r1
1048; THUMB1-NEXT:    str r2, [r0]
1049; THUMB1-NEXT:    bx lr
1050;
1051; THUMB2-LABEL: test10:
1052; THUMB2:       @ %bb.0: @ %entry
1053; THUMB2-NEXT:    ldrb r1, [r0]
1054; THUMB2-NEXT:    eor r1, r1, #255
1055; THUMB2-NEXT:    str r1, [r0]
1056; THUMB2-NEXT:    bx lr
1057define arm_aapcscc void @test10(i32* nocapture %p) {
1058entry:
1059  %0 = load i32, i32* %p, align 4
1060  %neg = and i32 %0, 255
1061  %and = xor i32 %neg, 255
1062  store i32 %and, i32* %p, align 4
1063  ret void
1064}
1065
1066