11314a288SDiana Picus; RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD 21314a288SDiana Picus; RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT-AEABI 31314a288SDiana Picus; RUN: llc -mtriple arm-linux-gnu- -mattr=+vfp2,+soft-float -float-abi=soft -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT-DEFAULT 4a5bab61aSDiana Picus 5a5bab61aSDiana Picusdefine arm_aapcscc float @test_frem_float(float %x, float %y) { 6a5bab61aSDiana Picus; CHECK-LABEL: test_frem_float: 7b3502212SDiana Picus; CHECK: bl fmodf 8a5bab61aSDiana Picus %r = frem float %x, %y 9a5bab61aSDiana Picus ret float %r 10a5bab61aSDiana Picus} 11a5bab61aSDiana Picus 123c608448SDiana Picusdefine arm_aapcscc double @test_frem_double(double %x, double %y) { 133c608448SDiana Picus; CHECK-LABEL: test_frem_double: 14b3502212SDiana Picus; CHECK: bl fmod 153c608448SDiana Picus %r = frem double %x, %y 163c608448SDiana Picus ret double %r 173c608448SDiana Picus} 183ff82c8cSDiana Picus 193ff82c8cSDiana Picusdeclare float @llvm.pow.f32(float %x, float %y) 203ff82c8cSDiana Picusdefine arm_aapcscc float @test_fpow_float(float %x, float %y) { 213ff82c8cSDiana Picus; CHECK-LABEL: test_fpow_float: 22b3502212SDiana Picus; CHECK: bl powf 233ff82c8cSDiana Picus %r = call float @llvm.pow.f32(float %x, float %y) 243ff82c8cSDiana Picus ret float %r 253ff82c8cSDiana Picus} 263ff82c8cSDiana Picus 273ff82c8cSDiana Picusdeclare double @llvm.pow.f64(double %x, double %y) 283ff82c8cSDiana Picusdefine arm_aapcscc double @test_fpow_double(double %x, double %y) { 293ff82c8cSDiana Picus; CHECK-LABEL: test_fpow_double: 30b3502212SDiana Picus; CHECK: bl pow 313ff82c8cSDiana Picus %r = call double @llvm.pow.f64(double %x, double %y) 323ff82c8cSDiana Picus ret double %r 333ff82c8cSDiana Picus} 341314a288SDiana Picus 351314a288SDiana Picusdefine arm_aapcscc float @test_add_float(float %x, float %y) { 361314a288SDiana Picus; CHECK-LABEL: test_add_float: 371314a288SDiana Picus; HARD: vadd.f32 38b3502212SDiana Picus; SOFT-AEABI: bl __aeabi_fadd 39b3502212SDiana Picus; SOFT-DEFAULT: bl __addsf3 401314a288SDiana Picus %r = fadd float %x, %y 411314a288SDiana Picus ret float %r 421314a288SDiana Picus} 431314a288SDiana Picus 441314a288SDiana Picusdefine arm_aapcscc double @test_add_double(double %x, double %y) { 451314a288SDiana Picus; CHECK-LABEL: test_add_double: 461314a288SDiana Picus; HARD: vadd.f64 47b3502212SDiana Picus; SOFT-AEABI: bl __aeabi_dadd 48b3502212SDiana Picus; SOFT-DEFAULT: bl __adddf3 491314a288SDiana Picus %r = fadd double %x, %y 501314a288SDiana Picus ret double %r 511314a288SDiana Picus} 525b916538SDiana Picus 53*5cde1ccbSJaved Absardefine arm_aapcscc float @test_sub_float(float %x, float %y) { 54*5cde1ccbSJaved Absar; CHECK-LABEL: test_sub_float: 55*5cde1ccbSJaved Absar; HARD: vsub.f32 56*5cde1ccbSJaved Absar; SOFT-AEABI: bl __aeabi_fsub 57*5cde1ccbSJaved Absar; SOFT-DEFAULT: bl __subsf3 58*5cde1ccbSJaved Absar %r = fsub float %x, %y 59*5cde1ccbSJaved Absar ret float %r 60*5cde1ccbSJaved Absar} 61*5cde1ccbSJaved Absar 62*5cde1ccbSJaved Absardefine arm_aapcscc double @test_sub_double(double %x, double %y) { 63*5cde1ccbSJaved Absar; CHECK-LABEL: test_sub_double: 64*5cde1ccbSJaved Absar; HARD: vsub.f64 65*5cde1ccbSJaved Absar; SOFT-AEABI: bl __aeabi_dsub 66*5cde1ccbSJaved Absar; SOFT-DEFAULT: bl __subdf3 67*5cde1ccbSJaved Absar %r = fsub double %x, %y 68*5cde1ccbSJaved Absar ret double %r 69*5cde1ccbSJaved Absar} 705b916538SDiana Picusdefine arm_aapcs_vfpcc i32 @test_cmp_float_ogt(float %x, float %y) { 715b916538SDiana Picus; CHECK-LABEL: test_cmp_float_ogt 725b916538SDiana Picus; HARD: vcmp.f32 735b916538SDiana Picus; HARD: vmrs APSR_nzcv, fpscr 745b916538SDiana Picus; HARD-NEXT: movgt 75b3502212SDiana Picus; SOFT-AEABI: bl __aeabi_fcmpgt 76b3502212SDiana Picus; SOFT-DEFAULT: bl __gtsf2 775b916538SDiana Picusentry: 785b916538SDiana Picus %v = fcmp ogt float %x, %y 795b916538SDiana Picus %r = zext i1 %v to i32 805b916538SDiana Picus ret i32 %r 815b916538SDiana Picus} 825b916538SDiana Picus 835b916538SDiana Picusdefine arm_aapcs_vfpcc i32 @test_cmp_float_one(float %x, float %y) { 845b916538SDiana Picus; CHECK-LABEL: test_cmp_float_one 855b916538SDiana Picus; HARD: vcmp.f32 865b916538SDiana Picus; HARD: vmrs APSR_nzcv, fpscr 875b916538SDiana Picus; HARD: movgt 885b916538SDiana Picus; HARD-NOT: vcmp 895b916538SDiana Picus; HARD: movmi 90b3502212SDiana Picus; SOFT-AEABI-DAG: bl __aeabi_fcmpgt 91b3502212SDiana Picus; SOFT-AEABI-DAG: bl __aeabi_fcmplt 92b3502212SDiana Picus; SOFT-DEFAULT-DAG: bl __gtsf2 93b3502212SDiana Picus; SOFT-DEFAULT-DAG: bl __ltsf2 945b916538SDiana Picusentry: 955b916538SDiana Picus %v = fcmp one float %x, %y 965b916538SDiana Picus %r = zext i1 %v to i32 975b916538SDiana Picus ret i32 %r 985b916538SDiana Picus} 99