1; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s 2; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=CHECK-V8 %s 3; rdar://13782395 4 5define i32 @t1(i32 %a, i32 %b, i8** %retaddr) { 6; CHECK-LABEL: t1: 7; CHECK: Block address taken 8; CHECK-NOT: Address of block that was removed by CodeGen 9 store i8* blockaddress(@t1, %cond_true), i8** %retaddr 10 %tmp2 = icmp eq i32 %a, 0 11 br i1 %tmp2, label %cond_false, label %cond_true 12 13cond_true: 14 %tmp5 = add i32 %b, 1 15 ret i32 %tmp5 16 17cond_false: 18 %tmp7 = add i32 %b, -1 19 ret i32 %tmp7 20} 21 22define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) { 23; CHECK-LABEL: t2: 24; CHECK: Block address taken 25; CHECK: %cond_true 26; CHECK: add 27; CHECK: bx lr 28 store i8* blockaddress(@t2, %cond_true), i8** %retaddr 29 %tmp2 = icmp sgt i32 %c, 10 30 %tmp5 = icmp slt i32 %d, 4 31 %tmp8 = and i1 %tmp5, %tmp2 32 %tmp13 = add i32 %b, %a 33 br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock 34 35cond_true: 36 %tmp15 = add i32 %tmp13, %c 37 %tmp1821 = sub i32 %tmp15, %d 38 ret i32 %tmp1821 39 40UnifiedReturnBlock: 41 ret i32 %tmp13 42} 43 44define hidden fastcc void @t3(i8** %retaddr) { 45; CHECK-LABEL: t3: 46; CHECK: Block address taken 47; CHECK-NOT: Address of block that was removed by CodeGen 48bb: 49 store i8* blockaddress(@t3, %KBBlockZero_return_1), i8** %retaddr 50 br i1 undef, label %bb77, label %bb7.i 51 52bb7.i: ; preds = %bb35 53 br label %bb2.i 54 55KBBlockZero_return_1: ; preds = %KBBlockZero.exit 56 unreachable 57 58KBBlockZero_return_0: ; preds = %KBBlockZero.exit 59 unreachable 60 61bb77: ; preds = %bb26, %bb12, %bb 62 ret void 63 64bb2.i: ; preds = %bb6.i350, %bb7.i 65 br i1 undef, label %bb6.i350, label %KBBlockZero.exit 66 67bb6.i350: ; preds = %bb2.i 68 br label %bb2.i 69 70KBBlockZero.exit: ; preds = %bb2.i 71 indirectbr i8* undef, [label %KBBlockZero_return_1, label %KBBlockZero_return_0] 72} 73 74 75; If-converter was checking for the wrong predicate subsumes pattern when doing 76; nested predicates. 77; E.g., Let A be a basic block that flows conditionally into B and B be a 78; predicated block. 79; B can be predicated with A.BrToBPredicate into A iff B.Predicate is less 80; "permissive" than A.BrToBPredicate, i.e., iff A.BrToBPredicate subsumes 81; B.Predicate. 82; <rdar://problem/14379453> 83 84; Hard-coded registers comes from the ABI. 85; CHECK: wrapDistance: 86; CHECK: cmp r1, #59 87; CHECK-NEXT: itt le 88; CHECK-NEXT: suble r0, r2, #1 89; CHECK-NEXT: bxle lr 90; CHECK-NEXT: subs [[REG:r[0-9]+]], #120 91; CHECK-NEXT: cmp [[REG]], r1 92; CHECK-NOT: it lt 93; CHECK-NEXT: bge [[LABEL:.+]] 94; Next BB 95; CHECK-NOT: cmplt 96; CHECK: cmp r0, #119 97; CHECK-NEXT: itt le 98; CHECK-NEXT: addle r0, r1, #1 99; CHECK-NEXT: bxle lr 100; Next BB 101; CHECK: [[LABEL]]: 102; CHECK-NEXT: subs r0, r1, r0 103; CHECK-NEXT: bx lr 104 105; CHECK-V8-LABEL: wrapDistance: 106; CHECK-V8: cmp r1, #59 107; CHECK-V8-NEXT: bgt 108; CHECK-V8-NEXT: %if.then 109; CHECK-V8-NEXT: subs r0, r2, #1 110; CHECK-V8-NEXT: bx lr 111; CHECK-V8-NEXT: %if.else 112; CHECK-V8-NEXT: subs [[REG:r[0-9]+]], #120 113; CHECK-V8-NEXT: cmp [[REG]], r1 114; CHECK-V8-NEXT: bge 115; CHECK-V8-NEXT: %if.else 116; CHECK-V8-NEXT: cmp r0, #119 117; CHECK-V8-NEXT: bgt 118; CHECK-V8-NEXT: %if.then4 119; CHECK-V8-NEXT: adds r0, r1, #1 120; CHECK-V8-NEXT: bx lr 121; CHECK-V8-NEXT: %if.end5 122; CHECK-V8-NEXT: subs r0, r1, r0 123; CHECK-V8-NEXT: bx lr 124 125define i32 @wrapDistance(i32 %tx, i32 %sx, i32 %w) { 126entry: 127 %cmp = icmp slt i32 %sx, 60 128 br i1 %cmp, label %if.then, label %if.else 129 130if.then: ; preds = %entry 131 %sub = add nsw i32 %w, -1 132 br label %return 133 134if.else: ; preds = %entry 135 %sub1 = add nsw i32 %w, -120 136 %cmp2 = icmp slt i32 %sub1, %sx 137 %cmp3 = icmp slt i32 %tx, 120 138 %or.cond = and i1 %cmp2, %cmp3 139 br i1 %or.cond, label %if.then4, label %if.end5 140 141if.then4: ; preds = %if.else 142 %add = add nsw i32 %sx, 1 143 br label %return 144 145if.end5: ; preds = %if.else 146 %sub6 = sub nsw i32 %sx, %tx 147 br label %return 148 149return: ; preds = %if.end5, %if.then4, %if.then 150 %retval.0 = phi i32 [ %sub, %if.then ], [ %add, %if.then4 ], [ %sub6, %if.end5 ] 151 ret i32 %retval.0 152} 153