xref: /llvm-project/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll (revision 7899572c88c6516b142c35e95e911917b623e057)
1*7899572cSMatt Arsenault; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs=0 -O0 2> %t.err < %s | FileCheck %s
2f6365a47SMatt Arsenault; RUN: FileCheck -check-prefix=ERR %s < %t.err
3f6365a47SMatt Arsenault
4f6365a47SMatt Arsenault; FIXME: This error will be fixed by supporting arbitrary divergent
5f6365a47SMatt Arsenault; dynamic allocas by performing a wave umax of the size.
6f6365a47SMatt Arsenault
7f6365a47SMatt Arsenault; ERR: error: <unknown>:0:0: in function move_to_valu_assert_srd_is_physreg_swdev503538 i32 (ptr addrspace(1)): illegal VGPR to SGPR copy
8f6365a47SMatt Arsenault
9f6365a47SMatt Arsenault; CHECK: ; illegal copy v0 to s32
10f6365a47SMatt Arsenault
11f6365a47SMatt Arsenaultdefine i32 @move_to_valu_assert_srd_is_physreg_swdev503538(ptr addrspace(1) %ptr) {
12f6365a47SMatt Arsenaultentry:
13f6365a47SMatt Arsenault  %idx = load i32, ptr addrspace(1) %ptr, align 4
14f6365a47SMatt Arsenault  %zero = extractelement <4 x i32> zeroinitializer, i32 %idx
15f6365a47SMatt Arsenault  %alloca = alloca [2048 x i8], i32 %zero, align 8, addrspace(5)
16f6365a47SMatt Arsenault  %ld = load i32, ptr addrspace(5) %alloca, align 8
17f6365a47SMatt Arsenault  call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 2048, i1 false)
18f6365a47SMatt Arsenault  ret i32 %ld
19f6365a47SMatt Arsenault}
20f6365a47SMatt Arsenault
21f6365a47SMatt Arsenaultdeclare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture writeonly, i8, i32, i1 immarg) #0
22f6365a47SMatt Arsenault
23f6365a47SMatt Arsenaultattributes #0 = { nocallback nofree nounwind willreturn memory(argmem: write) }
24