xref: /llvm-project/llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1*9e9907f1SFangrui Song# RUN: llc -mtriple=amdgcn -run-pass machine-scheduler -verify-machineinstrs %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
25a64c89cSJay Foad# REQUIRES: asserts
35a64c89cSJay Foad
45a64c89cSJay Foad# CHECK:     SU(0):   $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec
55a64c89cSJay Foad# CHECK:       Successors:
65a64c89cSJay Foad# CHECK-NEXT:    SU(2): Out  Latency=1
75a64c89cSJay Foad# CHECK-NEXT:    SU(2): Data Latency=1 Reg=$vgpr0
85a64c89cSJay Foad# CHECK:     SU(1):   $vgpr1 = V_MOV_B32_e32 $sgpr0, implicit $exec
95a64c89cSJay Foad# CHECK:       Successors:
105a64c89cSJay Foad# CHECK-NEXT:    SU(3): Out  Latency=1
115a64c89cSJay Foad# CHECK-NEXT:    SU(3): Data Latency=1 Reg=$vgpr1
125a64c89cSJay Foad# CHECK:     SU(2):   $vgpr0 = V_ADD_CO_U32_e32 $sgpr2, $vgpr0, implicit-def $vcc, implicit $exec
135a64c89cSJay Foad# CHECK:       Predecessors:
145a64c89cSJay Foad# CHECK-NEXT:    SU(0): Out  Latency=1
155a64c89cSJay Foad# CHECK-NEXT:    SU(0): Data Latency=1 Reg=$vgpr0
165a64c89cSJay Foad# CHECK:       Successors:
175a64c89cSJay Foad# CHECK-NEXT:    SU(4): Out  Latency=1
185a64c89cSJay Foad# CHECK-NEXT:    SU(4): Data Latency=1 Reg=$vgpr0_vgpr1
195a64c89cSJay Foad# CHECK-NEXT:    SU(3): Out  Latency=1
205a64c89cSJay Foad# CHECK-NEXT:    SU(3): Data Latency=1 Reg=$vcc
215a64c89cSJay Foad# CHECK:     SU(3):   $vgpr1 = V_ADDC_U32_e32 0, $vgpr1, implicit-def dead $vcc, implicit $vcc, implicit $exec
225a64c89cSJay Foad# CHECK:       Predecessors:
235a64c89cSJay Foad# CHECK-NEXT:    SU(2): Out  Latency=1
245a64c89cSJay Foad# CHECK-NEXT:    SU(2): Data Latency=1 Reg=$vcc
255a64c89cSJay Foad# CHECK-NEXT:    SU(1): Out  Latency=1
265a64c89cSJay Foad# CHECK-NEXT:    SU(1): Data Latency=1 Reg=$vgpr1
275a64c89cSJay Foad# CHECK:       Successors:
285a64c89cSJay Foad# CHECK-NEXT:    SU(4): Out  Latency=1
295a64c89cSJay Foad# CHECK-NEXT:    SU(4): Data Latency=1 Reg=$vgpr0_vgpr1
305a64c89cSJay Foad# CHECK:     SU(4):   $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
315a64c89cSJay Foad# CHECK:       Predecessors:
325a64c89cSJay Foad# CHECK-NEXT:    SU(3): Out  Latency=1
335a64c89cSJay Foad# CHECK-NEXT:    SU(3): Data Latency=1 Reg=$vgpr0_vgpr1
345a64c89cSJay Foad# CHECK-NEXT:    SU(2): Out  Latency=1
355a64c89cSJay Foad# CHECK-NEXT:    SU(2): Data Latency=1 Reg=$vgpr0_vgpr1
365a64c89cSJay Foad# CHECK:       Successors:
375a64c89cSJay Foad# CHECK-NEXT:    ExitSU: Ord  Latency=3 Artificial
385a64c89cSJay Foad
395a64c89cSJay Foad---
405a64c89cSJay Foadname: test
415a64c89cSJay FoadtracksRegLiveness: true
425a64c89cSJay Foadbody: |
435a64c89cSJay Foad  bb.0:
445a64c89cSJay Foad    liveins: $sgpr0, $sgpr1, $sgpr2
455a64c89cSJay Foad    $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec
465a64c89cSJay Foad    $vgpr1 = V_MOV_B32_e32 $sgpr0, implicit $exec
475a64c89cSJay Foad    $vgpr0 = V_ADD_CO_U32_e32 $sgpr2, $vgpr0, implicit-def $vcc, implicit $exec
485a64c89cSJay Foad    $vgpr1 = V_ADDC_U32_e32 0, $vgpr1, implicit-def dead $vcc, implicit $vcc, implicit $exec
495a64c89cSJay Foad    $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
505a64c89cSJay Foad...
51