xref: /llvm-project/llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll (revision 78bc1b64a6dc3fb6191355a5e1b502be8b3668e7) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s
3
4define amdgpu_kernel void @cannot_create_empty_or_backwards_segment(i1 %arg, i1 %arg1, i1 %arg2, i1 %arg3, i1 %arg4, i1 %arg5) {
5; CHECK-LABEL: cannot_create_empty_or_backwards_segment:
6; CHECK:       ; %bb.0: ; %bb
7; CHECK-NEXT:    s_mov_b64 s[26:27], s[2:3]
8; CHECK-NEXT:    s_mov_b64 s[24:25], s[0:1]
9; CHECK-NEXT:    s_load_dword s2, s[6:7], 0x0
10; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
11; CHECK-NEXT:    s_load_dword s14, s[6:7], 0x4
12; CHECK-NEXT:    s_add_u32 s24, s24, s13
13; CHECK-NEXT:    s_addc_u32 s25, s25, 0
14; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
15; CHECK-NEXT:    s_bitcmp1_b32 s2, 0
16; CHECK-NEXT:    s_cselect_b64 s[16:17], -1, 0
17; CHECK-NEXT:    s_bitcmp1_b32 s2, 8
18; CHECK-NEXT:    s_cselect_b64 s[10:11], -1, 0
19; CHECK-NEXT:    s_bitcmp1_b32 s2, 16
20; CHECK-NEXT:    s_cselect_b64 s[2:3], -1, 0
21; CHECK-NEXT:    s_bitcmp1_b32 s0, 24
22; CHECK-NEXT:    s_cselect_b64 s[8:9], -1, 0
23; CHECK-NEXT:    s_xor_b64 s[4:5], s[8:9], -1
24; CHECK-NEXT:    s_bitcmp1_b32 s1, 0
25; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[2:3]
26; CHECK-NEXT:    s_cselect_b64 s[12:13], -1, 0
27; CHECK-NEXT:    s_bitcmp1_b32 s14, 8
28; CHECK-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, v0
29; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[16:17]
30; CHECK-NEXT:    s_cselect_b64 s[14:15], -1, 0
31; CHECK-NEXT:    s_and_b64 s[4:5], exec, s[4:5]
32; CHECK-NEXT:    s_and_b64 s[6:7], exec, s[10:11]
33; CHECK-NEXT:    v_cmp_ne_u32_e64 s[0:1], 1, v0
34; CHECK-NEXT:    v_mov_b32_e32 v0, 0
35; CHECK-NEXT:    s_branch .LBB0_3
36; CHECK-NEXT:  .LBB0_1: ; in Loop: Header=BB0_3 Depth=1
37; CHECK-NEXT:    s_mov_b64 s[18:19], 0
38; CHECK-NEXT:    s_mov_b64 s[20:21], -1
39; CHECK-NEXT:    s_mov_b64 s[16:17], -1
40; CHECK-NEXT:    s_mov_b64 s[22:23], -1
41; CHECK-NEXT:  .LBB0_2: ; %Flow7
42; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
43; CHECK-NEXT:    s_and_b64 vcc, exec, s[22:23]
44; CHECK-NEXT:    s_cbranch_vccnz .LBB0_12
45; CHECK-NEXT:  .LBB0_3: ; %bb7
46; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
47; CHECK-NEXT:    s_and_b64 vcc, exec, s[2:3]
48; CHECK-NEXT:    s_cbranch_vccnz .LBB0_1
49; CHECK-NEXT:  ; %bb.4: ; %bb8
50; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
51; CHECK-NEXT:    s_mov_b64 vcc, s[4:5]
52; CHECK-NEXT:    s_cbranch_vccz .LBB0_6
53; CHECK-NEXT:  ; %bb.5: ; %bb9
54; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
55; CHECK-NEXT:    s_mov_b64 s[16:17], 0
56; CHECK-NEXT:    s_mov_b64 s[18:19], -1
57; CHECK-NEXT:    s_mov_b64 s[22:23], s[10:11]
58; CHECK-NEXT:    s_cbranch_execz .LBB0_7
59; CHECK-NEXT:    s_branch .LBB0_8
60; CHECK-NEXT:  .LBB0_6: ; in Loop: Header=BB0_3 Depth=1
61; CHECK-NEXT:    s_mov_b64 s[16:17], -1
62; CHECK-NEXT:    s_mov_b64 s[18:19], 0
63; CHECK-NEXT:    s_mov_b64 s[22:23], 0
64; CHECK-NEXT:  .LBB0_7: ; %bb10
65; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
66; CHECK-NEXT:    s_mov_b64 s[18:19], -1
67; CHECK-NEXT:    s_mov_b64 s[16:17], 0
68; CHECK-NEXT:    s_mov_b64 s[22:23], s[14:15]
69; CHECK-NEXT:  .LBB0_8: ; %Flow9
70; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
71; CHECK-NEXT:    s_mov_b64 s[20:21], -1
72; CHECK-NEXT:    s_andn2_b64 vcc, exec, s[22:23]
73; CHECK-NEXT:    s_mov_b64 s[22:23], -1
74; CHECK-NEXT:    s_cbranch_vccnz .LBB0_2
75; CHECK-NEXT:  ; %bb.9: ; %bb13
76; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
77; CHECK-NEXT:    s_mov_b64 vcc, s[6:7]
78; CHECK-NEXT:    s_cbranch_vccz .LBB0_11
79; CHECK-NEXT:  ; %bb.10: ; %bb16
80; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
81; CHECK-NEXT:    s_mov_b64 s[16:17], 0
82; CHECK-NEXT:    s_mov_b64 s[22:23], s[12:13]
83; CHECK-NEXT:    s_mov_b64 s[18:19], s[16:17]
84; CHECK-NEXT:    s_branch .LBB0_2
85; CHECK-NEXT:  .LBB0_11: ; in Loop: Header=BB0_3 Depth=1
86; CHECK-NEXT:    s_mov_b64 s[20:21], 0
87; CHECK-NEXT:    ; implicit-def: $sgpr16_sgpr17
88; CHECK-NEXT:    s_mov_b64 s[18:19], s[16:17]
89; CHECK-NEXT:    s_branch .LBB0_2
90; CHECK-NEXT:  .LBB0_12: ; %loop.exit.guard6
91; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
92; CHECK-NEXT:    s_xor_b64 s[22:23], s[20:21], -1
93; CHECK-NEXT:    s_mov_b64 s[20:21], -1
94; CHECK-NEXT:    s_and_b64 vcc, exec, s[22:23]
95; CHECK-NEXT:    s_cbranch_vccz .LBB0_16
96; CHECK-NEXT:  ; %bb.13: ; %bb14
97; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
98; CHECK-NEXT:    s_and_b64 vcc, exec, s[0:1]
99; CHECK-NEXT:    s_cbranch_vccnz .LBB0_15
100; CHECK-NEXT:  ; %bb.14: ; %bb15
101; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
102; CHECK-NEXT:    buffer_store_dword v0, off, s[24:27], 0 offset:4
103; CHECK-NEXT:    buffer_store_dword v0, off, s[24:27], 0
104; CHECK-NEXT:  .LBB0_15: ; %Flow
105; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
106; CHECK-NEXT:    s_mov_b64 s[20:21], 0
107; CHECK-NEXT:  .LBB0_16: ; %Flow13
108; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
109; CHECK-NEXT:    s_andn2_b64 vcc, exec, s[20:21]
110; CHECK-NEXT:    s_cbranch_vccnz .LBB0_3
111; CHECK-NEXT:  ; %bb.17: ; %loop.exit.guard
112; CHECK-NEXT:    s_and_b64 vcc, exec, s[16:17]
113; CHECK-NEXT:    s_cbranch_vccnz .LBB0_22
114; CHECK-NEXT:  ; %bb.18: ; %loop.exit.guard5
115; CHECK-NEXT:    s_and_b64 vcc, exec, s[18:19]
116; CHECK-NEXT:    s_cbranch_vccnz .LBB0_23
117; CHECK-NEXT:  ; %bb.19: ; %bb17
118; CHECK-NEXT:    s_and_b64 vcc, exec, s[8:9]
119; CHECK-NEXT:    s_cbranch_vccz .LBB0_21
120; CHECK-NEXT:  ; %bb.20: ; %bb19
121; CHECK-NEXT:    s_and_b64 vcc, exec, s[0:1]
122; CHECK-NEXT:    s_cbranch_vccz .LBB0_22
123; CHECK-NEXT:  .LBB0_21: ; %bb18
124; CHECK-NEXT:    s_endpgm
125; CHECK-NEXT:  .LBB0_22: ; %bb20
126; CHECK-NEXT:  .LBB0_23: ; %bb12
127bb:
128  br label %bb6
129
130bb6:                                              ; preds = %bb15, %bb14, %bb
131  br label %bb7
132
133bb7:                                              ; preds = %bb16, %bb6
134  br i1 %arg2, label %bb8, label %bb20
135
136bb8:                                              ; preds = %bb7
137  br i1 %arg3, label %bb10, label %bb9
138
139bb9:                                              ; preds = %bb8
140  br i1 %arg1, label %bb13, label %bb12
141
142bb10:                                             ; preds = %bb8
143  br i1 %arg5, label %bb11, label %bb12
144
145bb11:                                             ; preds = %bb10
146  br label %bb13
147
148bb12:                                             ; preds = %bb10, %bb9
149  unreachable
150
151bb13:                                             ; preds = %bb11, %bb9
152  br i1 %arg1, label %bb16, label %bb14
153
154bb14:                                             ; preds = %bb13
155  br i1 %arg, label %bb15, label %bb6
156
157bb15:                                             ; preds = %bb14
158  store double 0.000000e+00, ptr addrspace(5) null, align 2147483648
159  br label %bb6
160
161bb16:                                             ; preds = %bb13
162  br i1 %arg4, label %bb17, label %bb7
163
164bb17:                                             ; preds = %bb16
165  br i1 %arg3, label %bb19, label %bb18
166
167bb18:                                             ; preds = %bb17
168  ret void
169
170bb19:                                             ; preds = %bb17
171  br i1 %arg, label %bb20, label %bb21
172
173bb20:                                             ; preds = %bb19, %bb7
174  unreachable
175
176bb21:                                             ; preds = %bb19
177  ret void
178}
179