1*11e482c4SMatt Arsenault# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 2*11e482c4SMatt Arsenault# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=greedy,2 -stress-regalloc=4 -stop-after=virtregrewriter,2 -regalloc-enable-priority-advisor=default -o - %s | FileCheck -check-prefixes=CHECK,DEFAULT %s 3*11e482c4SMatt Arsenault# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=greedy,2 -stress-regalloc=4 -stop-after=virtregrewriter,2 -regalloc-enable-priority-advisor=dummy -o - %s | FileCheck -check-prefixes=CHECK,DUMMY %s 4*11e482c4SMatt Arsenault 5*11e482c4SMatt Arsenault# Check that the regalloc-enable-priority-advisor=dummy option works 6*11e482c4SMatt Arsenault# and the result is different from the default. Ordinarily %1 would be 7*11e482c4SMatt Arsenault# prioritized higher than %0 due to the register class priority 8*11e482c4SMatt Arsenault 9*11e482c4SMatt Arsenault--- 10*11e482c4SMatt Arsenaultname: foo 11*11e482c4SMatt ArsenaulttracksRegLiveness: true 12*11e482c4SMatt ArsenaultmachineFunctionInfo: 13*11e482c4SMatt Arsenault scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 14*11e482c4SMatt Arsenault frameOffsetReg: '$sgpr33' 15*11e482c4SMatt Arsenault stackPtrOffsetReg: '$sgpr32' 16*11e482c4SMatt Arsenaultregisters: 17*11e482c4SMatt Arsenault - { id: 0, class: vgpr_32 } 18*11e482c4SMatt Arsenault - { id: 1, class: vreg_128 } 19*11e482c4SMatt Arsenault - { id: 2, class: vgpr_32 } 20*11e482c4SMatt Arsenaultbody: | 21*11e482c4SMatt Arsenault bb.0: 22*11e482c4SMatt Arsenault liveins: $vgpr0, $vgpr1 23*11e482c4SMatt Arsenault 24*11e482c4SMatt Arsenault ; DEFAULT-LABEL: name: foo 25*11e482c4SMatt Arsenault ; DEFAULT: liveins: $vgpr0, $vgpr1 26*11e482c4SMatt Arsenault ; DEFAULT-NEXT: {{ $}} 27*11e482c4SMatt Arsenault ; DEFAULT-NEXT: SI_SPILL_V128_SAVE $vgpr1_vgpr2_vgpr3_vgpr4, %stack.0, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5) 28*11e482c4SMatt Arsenault ; DEFAULT-NEXT: SI_SPILL_V32_SAVE $vgpr0, %stack.1, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) 29*11e482c4SMatt Arsenault ; DEFAULT-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 30*11e482c4SMatt Arsenault ; DEFAULT-NEXT: renamable $vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) 31*11e482c4SMatt Arsenault ; DEFAULT-NEXT: renamable $vgpr3 = SI_SPILL_V32_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) 32*11e482c4SMatt Arsenault ; DEFAULT-NEXT: renamable $vgpr3 = V_ADD_U32_e32 killed $vgpr2, killed $vgpr3, implicit $exec 33*11e482c4SMatt Arsenault ; DEFAULT-NEXT: SI_RETURN implicit $vgpr3, implicit $vgpr0, implicit $vgpr1 34*11e482c4SMatt Arsenault ; 35*11e482c4SMatt Arsenault ; DUMMY-LABEL: name: foo 36*11e482c4SMatt Arsenault ; DUMMY: liveins: $vgpr0, $vgpr1 37*11e482c4SMatt Arsenault ; DUMMY-NEXT: {{ $}} 38*11e482c4SMatt Arsenault ; DUMMY-NEXT: SI_SPILL_V128_SAVE $vgpr1_vgpr2_vgpr3_vgpr4, %stack.1, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.1, align 4, addrspace 5) 39*11e482c4SMatt Arsenault ; DUMMY-NEXT: SI_SPILL_V32_SAVE $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) 40*11e482c4SMatt Arsenault ; DUMMY-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 41*11e482c4SMatt Arsenault ; DUMMY-NEXT: renamable $vgpr2 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) 42*11e482c4SMatt Arsenault ; DUMMY-NEXT: renamable $vgpr3_vgpr4_vgpr5_vgpr6 = SI_SPILL_V128_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.1, align 4, addrspace 5) 43*11e482c4SMatt Arsenault ; DUMMY-NEXT: renamable $vgpr3 = V_ADD_U32_e32 killed $vgpr3, killed $vgpr2, implicit $exec 44*11e482c4SMatt Arsenault ; DUMMY-NEXT: SI_RETURN implicit $vgpr3, implicit $vgpr0, implicit $vgpr1 45*11e482c4SMatt Arsenault undef %1.sub0:vreg_128 = COPY $vgpr1 46*11e482c4SMatt Arsenault %0:vgpr_32 = COPY $vgpr0 47*11e482c4SMatt Arsenault S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 48*11e482c4SMatt Arsenault %2:vgpr_32 = V_ADD_U32_e32 %1.sub0, %0, implicit $exec 49*11e482c4SMatt Arsenault $vgpr3 = COPY %2 50*11e482c4SMatt Arsenault SI_RETURN implicit $vgpr3, implicit $vgpr0, implicit $vgpr1 51*11e482c4SMatt Arsenault 52*11e482c4SMatt Arsenault... 53*11e482c4SMatt Arsenault 54*11e482c4SMatt Arsenault# CHECK: {{.*}} 55