17bc9d95bSChaitanya; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 4 27bc9d95bSChaitanya; RUN: opt < %s -passes=amdgpu-sw-lower-lds -S -amdgpu-asan-instrument-lds=false -mtriple=amdgcn-amd-amdhsa | FileCheck %s 3*3c79a04cSChaitanya; RUN: llc < %s -enable-new-pm -stop-after=amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false -mtriple=amdgcn-amd-amdhsa | FileCheck %s 47bc9d95bSChaitanya 57bc9d95bSChaitanya; Test to check if static LDS accesses in kernel are lowered correctly. 67bc9d95bSChaitanya@lds_1 = internal addrspace(3) global [1 x i8] poison, align 4 77bc9d95bSChaitanya@lds_2 = internal addrspace(3) global [1 x i32] poison, align 8 87bc9d95bSChaitanya 97bc9d95bSChaitanya;. 107bc9d95bSChaitanya; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0:![0-9]+]] 117bc9d95bSChaitanya; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 32, i32 1, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 64, i32 4, i32 32 } }, no_sanitize_address 127bc9d95bSChaitanya;. 137bc9d95bSChaitanyadefine amdgpu_kernel void @k0() sanitize_address { 147bc9d95bSChaitanya; CHECK-LABEL: define amdgpu_kernel void @k0( 157bc9d95bSChaitanya; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { 167bc9d95bSChaitanya; CHECK-NEXT: WId: 177bc9d95bSChaitanya; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 187bc9d95bSChaitanya; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 197bc9d95bSChaitanya; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 207bc9d95bSChaitanya; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]] 217bc9d95bSChaitanya; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]] 227bc9d95bSChaitanya; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 237bc9d95bSChaitanya; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]] 247bc9d95bSChaitanya; CHECK: Malloc: 257bc9d95bSChaitanya; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4 267bc9d95bSChaitanya; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4 277bc9d95bSChaitanya; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP13]], [[TMP14]] 287bc9d95bSChaitanya; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP16]] to i64 297bc9d95bSChaitanya; CHECK-NEXT: [[TMP23:%.*]] = call ptr @llvm.returnaddress(i32 0) 307bc9d95bSChaitanya; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP23]] to i64 317bc9d95bSChaitanya; CHECK-NEXT: [[TMP12:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP15]], i64 [[TMP11]]) 327bc9d95bSChaitanya; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP12]] to ptr addrspace(1) 337bc9d95bSChaitanya; CHECK-NEXT: store ptr addrspace(1) [[TMP6]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8 347bc9d95bSChaitanya; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP6]], i64 8 357bc9d95bSChaitanya; CHECK-NEXT: [[TMP41:%.*]] = ptrtoint ptr addrspace(1) [[TMP25]] to i64 367bc9d95bSChaitanya; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP41]], i64 24) 377bc9d95bSChaitanya; CHECK-NEXT: [[TMP61:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP6]], i64 33 387bc9d95bSChaitanya; CHECK-NEXT: [[TMP62:%.*]] = ptrtoint ptr addrspace(1) [[TMP61]] to i64 397bc9d95bSChaitanya; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP62]], i64 31) 407bc9d95bSChaitanya; CHECK-NEXT: [[TMP63:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP6]], i64 68 417bc9d95bSChaitanya; CHECK-NEXT: [[TMP64:%.*]] = ptrtoint ptr addrspace(1) [[TMP63]] to i64 427bc9d95bSChaitanya; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP64]], i64 28) 437bc9d95bSChaitanya; CHECK-NEXT: br label [[TMP7]] 447bc9d95bSChaitanya; CHECK: 20: 457bc9d95bSChaitanya; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ] 467bc9d95bSChaitanya; CHECK-NEXT: call void @llvm.amdgcn.s.barrier() 477bc9d95bSChaitanya; CHECK-NEXT: [[TMP19:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8 487bc9d95bSChaitanya; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4 497bc9d95bSChaitanya; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP10]] 507bc9d95bSChaitanya; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4 517bc9d95bSChaitanya; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP17]] 527bc9d95bSChaitanya; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr addrspace(3) [[TMP18]] to i32 537bc9d95bSChaitanya; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP19]], i32 [[TMP26]] 547bc9d95bSChaitanya; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP27]], align 4 557bc9d95bSChaitanya; CHECK-NEXT: [[TMP43:%.*]] = ptrtoint ptr addrspace(3) [[TMP24]] to i32 567bc9d95bSChaitanya; CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP19]], i32 [[TMP43]] 577bc9d95bSChaitanya; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP44]], align 2 587bc9d95bSChaitanya; CHECK-NEXT: br label [[CONDFREE1:%.*]] 597bc9d95bSChaitanya; CHECK: CondFree: 607bc9d95bSChaitanya; CHECK-NEXT: call void @llvm.amdgcn.s.barrier() 617bc9d95bSChaitanya; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]] 627bc9d95bSChaitanya; CHECK: Free: 637bc9d95bSChaitanya; CHECK-NEXT: [[TMP20:%.*]] = call ptr @llvm.returnaddress(i32 0) 647bc9d95bSChaitanya; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP20]] to i64 657bc9d95bSChaitanya; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr addrspace(1) [[TMP19]] to i64 667bc9d95bSChaitanya; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP22]], i64 [[TMP21]]) 677bc9d95bSChaitanya; CHECK-NEXT: br label [[END]] 687bc9d95bSChaitanya; CHECK: End: 697bc9d95bSChaitanya; CHECK-NEXT: ret void 707bc9d95bSChaitanya; 717bc9d95bSChaitanya store i8 7, ptr addrspace(3) @lds_1, align 4 727bc9d95bSChaitanya store i32 8, ptr addrspace(3) @lds_2, align 2 737bc9d95bSChaitanya ret void 747bc9d95bSChaitanya} 757bc9d95bSChaitanya 767bc9d95bSChaitanya!llvm.module.flags = !{!0} 777bc9d95bSChaitanya!0 = !{i32 4, !"nosanitize_address", i32 1} 787bc9d95bSChaitanya 797bc9d95bSChaitanya;. 807bc9d95bSChaitanya; CHECK: attributes #[[ATTR0]] = { sanitize_address "amdgpu-lds-size"="8" } 817bc9d95bSChaitanya; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 827bc9d95bSChaitanya; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) } 837bc9d95bSChaitanya; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn } 847bc9d95bSChaitanya;. 857bc9d95bSChaitanya; CHECK: [[META0]] = !{i32 0, i32 1} 867bc9d95bSChaitanya;. 87