1*009368f1SMatt Arsenault; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 5 2*009368f1SMatt Arsenault; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-lower-kernel-attributes %s | FileCheck %s 3*009368f1SMatt Arsenault 4*009368f1SMatt Arsenaultdefine i32 @use_grid_size_x_max_num_workgroups() #0 { 5*009368f1SMatt Arsenault; CHECK-LABEL: define i32 @use_grid_size_x_max_num_workgroups( 6*009368f1SMatt Arsenault; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { 7*009368f1SMatt Arsenault; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 8*009368f1SMatt Arsenault; CHECK-NEXT: [[GRID_SIZE_X:%.*]] = load i32, ptr addrspace(4) [[IMPLICITARG_PTR]], align 4, !range [[RNG0:![0-9]+]] 9*009368f1SMatt Arsenault; CHECK-NEXT: ret i32 [[GRID_SIZE_X]] 10*009368f1SMatt Arsenault; 11*009368f1SMatt Arsenault %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 12*009368f1SMatt Arsenault %grid.size.x = load i32, ptr addrspace(4) %implicitarg.ptr, align 4 13*009368f1SMatt Arsenault ret i32 %grid.size.x 14*009368f1SMatt Arsenault} 15*009368f1SMatt Arsenault 16*009368f1SMatt Arsenaultdefine i32 @use_grid_size_x_max_num_workgroups_existing_nonzero_range() #0 { 17*009368f1SMatt Arsenault; CHECK-LABEL: define i32 @use_grid_size_x_max_num_workgroups_existing_nonzero_range( 18*009368f1SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 19*009368f1SMatt Arsenault; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 20*009368f1SMatt Arsenault; CHECK-NEXT: [[GRID_SIZE_X:%.*]] = load i32, ptr addrspace(4) [[IMPLICITARG_PTR]], align 4, !range [[RNG0]] 21*009368f1SMatt Arsenault; CHECK-NEXT: ret i32 [[GRID_SIZE_X]] 22*009368f1SMatt Arsenault; 23*009368f1SMatt Arsenault %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 24*009368f1SMatt Arsenault %grid.size.x = load i32, ptr addrspace(4) %implicitarg.ptr, align 4, !range !0 25*009368f1SMatt Arsenault ret i32 %grid.size.x 26*009368f1SMatt Arsenault} 27*009368f1SMatt Arsenault 28*009368f1SMatt Arsenaultdefine i32 @use_grid_size_y_max_num_workgroups() #0 { 29*009368f1SMatt Arsenault; CHECK-LABEL: define i32 @use_grid_size_y_max_num_workgroups( 30*009368f1SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 31*009368f1SMatt Arsenault; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 32*009368f1SMatt Arsenault; CHECK-NEXT: [[GEP_GRID_SIZE_Y:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 4 33*009368f1SMatt Arsenault; CHECK-NEXT: [[GRID_SIZE_Y:%.*]] = load i32, ptr addrspace(4) [[GEP_GRID_SIZE_Y]], align 4, !range [[RNG1:![0-9]+]] 34*009368f1SMatt Arsenault; CHECK-NEXT: ret i32 [[GRID_SIZE_Y]] 35*009368f1SMatt Arsenault; 36*009368f1SMatt Arsenault %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 37*009368f1SMatt Arsenault %gep.grid.size.y = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 4 38*009368f1SMatt Arsenault %grid.size.y = load i32, ptr addrspace(4) %gep.grid.size.y, align 4 39*009368f1SMatt Arsenault ret i32 %grid.size.y 40*009368f1SMatt Arsenault} 41*009368f1SMatt Arsenault 42*009368f1SMatt Arsenaultdefine i32 @use_grid_size_z_max_num_workgroups() #0 { 43*009368f1SMatt Arsenault; CHECK-LABEL: define i32 @use_grid_size_z_max_num_workgroups( 44*009368f1SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 45*009368f1SMatt Arsenault; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 46*009368f1SMatt Arsenault; CHECK-NEXT: [[GEP_GRID_SIZE_Z:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[IMPLICITARG_PTR]], i64 8 47*009368f1SMatt Arsenault; CHECK-NEXT: [[GRID_SIZE_Z:%.*]] = load i32, ptr addrspace(4) [[GEP_GRID_SIZE_Z]], align 4, !range [[RNG2:![0-9]+]] 48*009368f1SMatt Arsenault; CHECK-NEXT: ret i32 [[GRID_SIZE_Z]] 49*009368f1SMatt Arsenault; 50*009368f1SMatt Arsenault %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 51*009368f1SMatt Arsenault %gep.grid.size.z = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 8 52*009368f1SMatt Arsenault %grid.size.z = load i32, ptr addrspace(4) %gep.grid.size.z, align 4 53*009368f1SMatt Arsenault ret i32 %grid.size.z 54*009368f1SMatt Arsenault} 55*009368f1SMatt Arsenault 56*009368f1SMatt Arsenaultdefine <2 x i16> @use_grid_size_x_max_num_workgroups_load_wrong_type() #0 { 57*009368f1SMatt Arsenault; CHECK-LABEL: define <2 x i16> @use_grid_size_x_max_num_workgroups_load_wrong_type( 58*009368f1SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 59*009368f1SMatt Arsenault; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 60*009368f1SMatt Arsenault; CHECK-NEXT: [[GRID_SIZE_X:%.*]] = load <2 x i16>, ptr addrspace(4) [[IMPLICITARG_PTR]], align 4 61*009368f1SMatt Arsenault; CHECK-NEXT: ret <2 x i16> [[GRID_SIZE_X]] 62*009368f1SMatt Arsenault; 63*009368f1SMatt Arsenault %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 64*009368f1SMatt Arsenault %grid.size.x = load <2 x i16>, ptr addrspace(4) %implicitarg.ptr, align 4 65*009368f1SMatt Arsenault ret <2 x i16> %grid.size.x 66*009368f1SMatt Arsenault} 67*009368f1SMatt Arsenault 68*009368f1SMatt Arsenaultdefine i32 @use_grid_size_x_max_num_workgroups_max_minus_1() #1 { 69*009368f1SMatt Arsenault; CHECK-LABEL: define i32 @use_grid_size_x_max_num_workgroups_max_minus_1( 70*009368f1SMatt Arsenault; CHECK-SAME: ) #[[ATTR1:[0-9]+]] { 71*009368f1SMatt Arsenault; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 72*009368f1SMatt Arsenault; CHECK-NEXT: [[GRID_SIZE_X:%.*]] = load i32, ptr addrspace(4) [[IMPLICITARG_PTR]], align 4, !range [[RNG3:![0-9]+]] 73*009368f1SMatt Arsenault; CHECK-NEXT: ret i32 [[GRID_SIZE_X]] 74*009368f1SMatt Arsenault; 75*009368f1SMatt Arsenault %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 76*009368f1SMatt Arsenault %grid.size.x = load i32, ptr addrspace(4) %implicitarg.ptr, align 4 77*009368f1SMatt Arsenault ret i32 %grid.size.x 78*009368f1SMatt Arsenault} 79*009368f1SMatt Arsenault 80*009368f1SMatt Arsenaultdefine i32 @use_grid_size_x_max_num_workgroups_max() #2 { 81*009368f1SMatt Arsenault; CHECK-LABEL: define i32 @use_grid_size_x_max_num_workgroups_max( 82*009368f1SMatt Arsenault; CHECK-SAME: ) #[[ATTR2:[0-9]+]] { 83*009368f1SMatt Arsenault; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 84*009368f1SMatt Arsenault; CHECK-NEXT: [[GRID_SIZE_X:%.*]] = load i32, ptr addrspace(4) [[IMPLICITARG_PTR]], align 4 85*009368f1SMatt Arsenault; CHECK-NEXT: ret i32 [[GRID_SIZE_X]] 86*009368f1SMatt Arsenault; 87*009368f1SMatt Arsenault %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 88*009368f1SMatt Arsenault %grid.size.x = load i32, ptr addrspace(4) %implicitarg.ptr, align 4 89*009368f1SMatt Arsenault ret i32 %grid.size.x 90*009368f1SMatt Arsenault} 91*009368f1SMatt Arsenault 92*009368f1SMatt Arsenaultdefine i32 @use_grid_size_x_max_num_workgroups_zero() #3 { 93*009368f1SMatt Arsenault; CHECK-LABEL: define i32 @use_grid_size_x_max_num_workgroups_zero( 94*009368f1SMatt Arsenault; CHECK-SAME: ) #[[ATTR3:[0-9]+]] { 95*009368f1SMatt Arsenault; CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 96*009368f1SMatt Arsenault; CHECK-NEXT: [[GRID_SIZE_X:%.*]] = load i32, ptr addrspace(4) [[IMPLICITARG_PTR]], align 4 97*009368f1SMatt Arsenault; CHECK-NEXT: ret i32 [[GRID_SIZE_X]] 98*009368f1SMatt Arsenault; 99*009368f1SMatt Arsenault %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 100*009368f1SMatt Arsenault %grid.size.x = load i32, ptr addrspace(4) %implicitarg.ptr, align 4 101*009368f1SMatt Arsenault ret i32 %grid.size.x 102*009368f1SMatt Arsenault} 103*009368f1SMatt Arsenault 104*009368f1SMatt Arsenaultdeclare noundef align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #3 105*009368f1SMatt Arsenault 106*009368f1SMatt Arsenaultattributes #0 = { "amdgpu-max-num-workgroups"="36,42,89" } 107*009368f1SMatt Arsenaultattributes #1 = { "amdgpu-max-num-workgroups"="4294967294,42,89" } 108*009368f1SMatt Arsenaultattributes #2 = { "amdgpu-max-num-workgroups"="4294967295,42,89" } 109*009368f1SMatt Arsenaultattributes #3 = { "amdgpu-max-num-workgroups"="0,42,89" } 110*009368f1SMatt Arsenault 111*009368f1SMatt Arsenault!0 = !{i32 0, i32 -1} 112*009368f1SMatt Arsenault 113*009368f1SMatt Arsenault;. 114*009368f1SMatt Arsenault; CHECK: attributes #[[ATTR0]] = { "amdgpu-max-num-workgroups"="36,42,89" } 115*009368f1SMatt Arsenault; CHECK: attributes #[[ATTR1]] = { "amdgpu-max-num-workgroups"="4294967294,42,89" } 116*009368f1SMatt Arsenault; CHECK: attributes #[[ATTR2]] = { "amdgpu-max-num-workgroups"="4294967295,42,89" } 117*009368f1SMatt Arsenault; CHECK: attributes #[[ATTR3]] = { "amdgpu-max-num-workgroups"="0,42,89" } 118*009368f1SMatt Arsenault; CHECK: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 119*009368f1SMatt Arsenault;. 120*009368f1SMatt Arsenault; CHECK: [[RNG0]] = !{i32 1, i32 37} 121*009368f1SMatt Arsenault; CHECK: [[RNG1]] = !{i32 1, i32 43} 122*009368f1SMatt Arsenault; CHECK: [[RNG2]] = !{i32 1, i32 90} 123*009368f1SMatt Arsenault; CHECK: [[RNG3]] = !{i32 1, i32 -1} 124*009368f1SMatt Arsenault;. 125