1b6b703b2SMatt Arsenault; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals all --version 4 2b6b703b2SMatt Arsenault; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -passes=amdgpu-attributor %s | FileCheck %s 3b6b703b2SMatt Arsenault 4b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_uses_asm_virtreg() { 5b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg( 6b6b703b2SMatt Arsenault; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { 7b6b703b2SMatt Arsenault; CHECK-NEXT: call void asm sideeffect " 8b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 9b6b703b2SMatt Arsenault; 10b6b703b2SMatt Arsenault call void asm sideeffect "; use $0", "a"(i32 poison) 11b6b703b2SMatt Arsenault ret void 12b6b703b2SMatt Arsenault} 13b6b703b2SMatt Arsenault 14b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_uses_asm_virtreg_def() { 15b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def( 16b6b703b2SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 17b6b703b2SMatt Arsenault; CHECK-NEXT: [[DEF:%.*]] = call i32 asm sideeffect " 18b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 19b6b703b2SMatt Arsenault; 20b6b703b2SMatt Arsenault %def = call i32 asm sideeffect "; def $0", "=a"() 21b6b703b2SMatt Arsenault ret void 22b6b703b2SMatt Arsenault} 23b6b703b2SMatt Arsenault 24b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_uses_asm_physreg_def_tuple() { 25b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_def_tuple( 26b6b703b2SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 27b6b703b2SMatt Arsenault; CHECK-NEXT: [[DEF:%.*]] = call i64 asm sideeffect " 28b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 29b6b703b2SMatt Arsenault; 30b6b703b2SMatt Arsenault %def = call i64 asm sideeffect "; def $0", "={a[0:1]}"() 31b6b703b2SMatt Arsenault ret void 32b6b703b2SMatt Arsenault} 33b6b703b2SMatt Arsenault 34b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_uses_asm_virtreg_second_arg() { 35b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_second_arg( 36b6b703b2SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 37b6b703b2SMatt Arsenault; CHECK-NEXT: call void asm sideeffect " 38b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 39b6b703b2SMatt Arsenault; 40b6b703b2SMatt Arsenault call void asm sideeffect "; use $0", "v,a"(i32 poison, i32 poison) 41b6b703b2SMatt Arsenault ret void 42b6b703b2SMatt Arsenault} 43b6b703b2SMatt Arsenault 44b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_uses_non_agpr_asm() { 45b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_non_agpr_asm( 46b6b703b2SMatt Arsenault; CHECK-SAME: ) #[[ATTR1:[0-9]+]] { 47b6b703b2SMatt Arsenault; CHECK-NEXT: call void asm sideeffect " 48b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 49b6b703b2SMatt Arsenault; 50b6b703b2SMatt Arsenault call void asm sideeffect "; use $0", "v"(i32 poison) 51b6b703b2SMatt Arsenault ret void 52b6b703b2SMatt Arsenault} 53b6b703b2SMatt Arsenault 54b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_uses_asm_physreg() { 55b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg( 56b6b703b2SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 57b6b703b2SMatt Arsenault; CHECK-NEXT: call void asm sideeffect " 58b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 59b6b703b2SMatt Arsenault; 60b6b703b2SMatt Arsenault call void asm sideeffect "; use $0", "{a0}"(i32 poison) 61b6b703b2SMatt Arsenault ret void 62b6b703b2SMatt Arsenault} 63b6b703b2SMatt Arsenault 64b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_uses_asm_physreg_tuple() { 65b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_tuple( 66b6b703b2SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 67b6b703b2SMatt Arsenault; CHECK-NEXT: call void asm sideeffect " 68b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 69b6b703b2SMatt Arsenault; 70b6b703b2SMatt Arsenault call void asm sideeffect "; use $0", "{a[0:1]}"(i64 poison) 71b6b703b2SMatt Arsenault ret void 72b6b703b2SMatt Arsenault} 73b6b703b2SMatt Arsenault 74b6b703b2SMatt Arsenaultdefine void @func_uses_asm_virtreg_agpr() { 75b6b703b2SMatt Arsenault; CHECK-LABEL: define void @func_uses_asm_virtreg_agpr( 76*7dbd6cd2SShilei Tian; CHECK-SAME: ) #[[ATTR0]] { 77b6b703b2SMatt Arsenault; CHECK-NEXT: call void asm sideeffect " 78b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 79b6b703b2SMatt Arsenault; 80b6b703b2SMatt Arsenault call void asm sideeffect "; use $0", "a"(i32 poison) 81b6b703b2SMatt Arsenault ret void 82b6b703b2SMatt Arsenault} 83b6b703b2SMatt Arsenault 84b6b703b2SMatt Arsenaultdefine void @func_uses_asm_physreg_agpr() { 85b6b703b2SMatt Arsenault; CHECK-LABEL: define void @func_uses_asm_physreg_agpr( 86*7dbd6cd2SShilei Tian; CHECK-SAME: ) #[[ATTR0]] { 87b6b703b2SMatt Arsenault; CHECK-NEXT: call void asm sideeffect " 88b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 89b6b703b2SMatt Arsenault; 90b6b703b2SMatt Arsenault call void asm sideeffect "; use $0", "{a0}"(i32 poison) 91b6b703b2SMatt Arsenault ret void 92b6b703b2SMatt Arsenault} 93b6b703b2SMatt Arsenault 94b6b703b2SMatt Arsenaultdefine void @func_uses_asm_physreg_agpr_tuple() { 95b6b703b2SMatt Arsenault; CHECK-LABEL: define void @func_uses_asm_physreg_agpr_tuple( 96*7dbd6cd2SShilei Tian; CHECK-SAME: ) #[[ATTR0]] { 97b6b703b2SMatt Arsenault; CHECK-NEXT: call void asm sideeffect " 98b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 99b6b703b2SMatt Arsenault; 100b6b703b2SMatt Arsenault call void asm sideeffect "; use $0", "{a[0:1]}"(i64 poison) 101b6b703b2SMatt Arsenault ret void 102b6b703b2SMatt Arsenault} 103b6b703b2SMatt Arsenault 104b6b703b2SMatt Arsenaultdeclare void @unknown() 105b6b703b2SMatt Arsenault 106b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_calls_extern() { 107b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern( 108*7dbd6cd2SShilei Tian; CHECK-SAME: ) #[[ATTR2:[0-9]+]] { 109b6b703b2SMatt Arsenault; CHECK-NEXT: call void @unknown() 110b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 111b6b703b2SMatt Arsenault; 112b6b703b2SMatt Arsenault call void @unknown() 113b6b703b2SMatt Arsenault ret void 114b6b703b2SMatt Arsenault} 115b6b703b2SMatt Arsenault 116b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_calls_extern_marked_callsite() { 117b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern_marked_callsite( 118*7dbd6cd2SShilei Tian; CHECK-SAME: ) #[[ATTR2]] { 119*7dbd6cd2SShilei Tian; CHECK-NEXT: call void @unknown() #[[ATTR6:[0-9]+]] 120b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 121b6b703b2SMatt Arsenault; 122b6b703b2SMatt Arsenault call void @unknown() #0 123b6b703b2SMatt Arsenault ret void 124b6b703b2SMatt Arsenault} 125b6b703b2SMatt Arsenault 126b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_calls_indirect(ptr %indirect) { 127b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect( 128*7dbd6cd2SShilei Tian; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR2]] { 129b6b703b2SMatt Arsenault; CHECK-NEXT: call void [[INDIRECT]]() 130b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 131b6b703b2SMatt Arsenault; 132b6b703b2SMatt Arsenault call void %indirect() 133b6b703b2SMatt Arsenault ret void 134b6b703b2SMatt Arsenault} 135b6b703b2SMatt Arsenault 136b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_calls_indirect_marked_callsite(ptr %indirect) { 137b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect_marked_callsite( 138*7dbd6cd2SShilei Tian; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR2]] { 139*7dbd6cd2SShilei Tian; CHECK-NEXT: call void [[INDIRECT]]() #[[ATTR6]] 140b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 141b6b703b2SMatt Arsenault; 142b6b703b2SMatt Arsenault call void %indirect() #0 143b6b703b2SMatt Arsenault ret void 144b6b703b2SMatt Arsenault} 145b6b703b2SMatt Arsenault 146b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_transitively_uses_agpr_asm() { 147b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_transitively_uses_agpr_asm( 148b6b703b2SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 149b6b703b2SMatt Arsenault; CHECK-NEXT: call void @func_uses_asm_physreg_agpr() 150b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 151b6b703b2SMatt Arsenault; 152b6b703b2SMatt Arsenault call void @func_uses_asm_physreg_agpr() 153b6b703b2SMatt Arsenault ret void 154b6b703b2SMatt Arsenault} 155b6b703b2SMatt Arsenault 156b6b703b2SMatt Arsenaultdefine void @empty() { 157b6b703b2SMatt Arsenault; CHECK-LABEL: define void @empty( 158*7dbd6cd2SShilei Tian; CHECK-SAME: ) #[[ATTR1]] { 159b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 160b6b703b2SMatt Arsenault; 161b6b703b2SMatt Arsenault ret void 162b6b703b2SMatt Arsenault} 163b6b703b2SMatt Arsenault 164b6b703b2SMatt Arsenaultdefine void @also_empty() { 165b6b703b2SMatt Arsenault; CHECK-LABEL: define void @also_empty( 166*7dbd6cd2SShilei Tian; CHECK-SAME: ) #[[ATTR1]] { 167b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 168b6b703b2SMatt Arsenault; 169b6b703b2SMatt Arsenault ret void 170b6b703b2SMatt Arsenault} 171b6b703b2SMatt Arsenault 172b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_calls_empty() { 173b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_empty( 174b6b703b2SMatt Arsenault; CHECK-SAME: ) #[[ATTR1]] { 175b6b703b2SMatt Arsenault; CHECK-NEXT: call void @empty() 176b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 177b6b703b2SMatt Arsenault; 178b6b703b2SMatt Arsenault call void @empty() 179b6b703b2SMatt Arsenault ret void 180b6b703b2SMatt Arsenault} 181b6b703b2SMatt Arsenault 182b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_calls_non_agpr_and_agpr() { 183b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_non_agpr_and_agpr( 184b6b703b2SMatt Arsenault; CHECK-SAME: ) #[[ATTR0]] { 185b6b703b2SMatt Arsenault; CHECK-NEXT: call void @empty() 186b6b703b2SMatt Arsenault; CHECK-NEXT: call void @func_uses_asm_physreg_agpr() 187b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 188b6b703b2SMatt Arsenault; 189b6b703b2SMatt Arsenault call void @empty() 190b6b703b2SMatt Arsenault call void @func_uses_asm_physreg_agpr() 191b6b703b2SMatt Arsenault ret void 192b6b703b2SMatt Arsenault} 193b6b703b2SMatt Arsenault 194b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_calls_generic_intrinsic(ptr %ptr0, ptr %ptr1, i64 %size) { 195b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_generic_intrinsic( 196b6b703b2SMatt Arsenault; CHECK-SAME: ptr [[PTR0:%.*]], ptr [[PTR1:%.*]], i64 [[SIZE:%.*]]) #[[ATTR1]] { 197b6b703b2SMatt Arsenault; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr [[PTR0]], ptr [[PTR1]], i64 [[SIZE]], i1 false) 198b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 199b6b703b2SMatt Arsenault; 200b6b703b2SMatt Arsenault call void @llvm.memcpy.p0.p0.i64(ptr %ptr0, ptr %ptr1, i64 %size, i1 false) 201b6b703b2SMatt Arsenault ret void 202b6b703b2SMatt Arsenault} 203b6b703b2SMatt Arsenault 204b6b703b2SMatt Arsenaultdeclare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32 immarg, i32 immarg, i32 immarg) 205b6b703b2SMatt Arsenault 206b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_calls_mfma.f32.32x32x1f32(ptr addrspace(1) %out, float %a, float %b, <32 x float> %c) { 207b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_mfma.f32.32x32x1f32( 208b6b703b2SMatt Arsenault; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float [[B:%.*]], <32 x float> [[C:%.*]]) #[[ATTR1]] { 209b6b703b2SMatt Arsenault; CHECK-NEXT: [[RESULT:%.*]] = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float [[A]], float [[B]], <32 x float> [[C]], i32 0, i32 0, i32 0) 210b6b703b2SMatt Arsenault; CHECK-NEXT: store <32 x float> [[RESULT]], ptr addrspace(1) [[OUT]], align 128 211b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 212b6b703b2SMatt Arsenault; 213b6b703b2SMatt Arsenault %result = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %a, float %b, <32 x float> %c, i32 0, i32 0, i32 0) 214b6b703b2SMatt Arsenault store <32 x float> %result, ptr addrspace(1) %out 215b6b703b2SMatt Arsenault ret void 216b6b703b2SMatt Arsenault} 217b6b703b2SMatt Arsenault 218b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @kernel_calls_workitem_id_x(ptr addrspace(1) %out) { 219b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_workitem_id_x( 220b6b703b2SMatt Arsenault; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]]) #[[ATTR1]] { 221b6b703b2SMatt Arsenault; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 222b6b703b2SMatt Arsenault; CHECK-NEXT: store i32 [[RESULT]], ptr addrspace(1) [[OUT]], align 4 223b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 224b6b703b2SMatt Arsenault; 225b6b703b2SMatt Arsenault %result = call i32 @llvm.amdgcn.workitem.id.x() 226b6b703b2SMatt Arsenault store i32 %result, ptr addrspace(1) %out 227b6b703b2SMatt Arsenault ret void 228b6b703b2SMatt Arsenault} 229b6b703b2SMatt Arsenault 230b6b703b2SMatt Arsenaultdefine amdgpu_kernel void @indirect_calls_none_agpr(i1 %cond) { 231b6b703b2SMatt Arsenault; CHECK-LABEL: define amdgpu_kernel void @indirect_calls_none_agpr( 232b6b703b2SMatt Arsenault; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR0]] { 233b6b703b2SMatt Arsenault; CHECK-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @empty, ptr @also_empty 234d880f5a4SShilei Tian; CHECK-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @also_empty 235d880f5a4SShilei Tian; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] 236d880f5a4SShilei Tian; CHECK: 2: 237d880f5a4SShilei Tian; CHECK-NEXT: call void @also_empty() 238d880f5a4SShilei Tian; CHECK-NEXT: br label [[TMP6:%.*]] 239d880f5a4SShilei Tian; CHECK: 3: 240d880f5a4SShilei Tian; CHECK-NEXT: br i1 true, label [[TMP4:%.*]], label [[TMP5:%.*]] 241d880f5a4SShilei Tian; CHECK: 4: 242d880f5a4SShilei Tian; CHECK-NEXT: call void @empty() 243d880f5a4SShilei Tian; CHECK-NEXT: br label [[TMP6]] 244d880f5a4SShilei Tian; CHECK: 5: 245d880f5a4SShilei Tian; CHECK-NEXT: unreachable 246d880f5a4SShilei Tian; CHECK: 6: 247b6b703b2SMatt Arsenault; CHECK-NEXT: ret void 248b6b703b2SMatt Arsenault; 249b6b703b2SMatt Arsenault %fptr = select i1 %cond, ptr @empty, ptr @also_empty 250b6b703b2SMatt Arsenault call void %fptr() 251b6b703b2SMatt Arsenault ret void 252b6b703b2SMatt Arsenault} 253b6b703b2SMatt Arsenault 254b6b703b2SMatt Arsenault 255b6b703b2SMatt Arsenaultattributes #0 = { "amdgpu-no-agpr" } 256b6b703b2SMatt Arsenault;. 25741ed16c3SJun Wang; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } 25841ed16c3SJun Wang; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" } 259*7dbd6cd2SShilei Tian; CHECK: attributes #[[ATTR2]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" } 260*7dbd6cd2SShilei Tian; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" } 261*7dbd6cd2SShilei Tian; CHECK: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" } 262*7dbd6cd2SShilei Tian; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" } 263*7dbd6cd2SShilei Tian; CHECK: attributes #[[ATTR6]] = { "amdgpu-no-agpr" } 264b6b703b2SMatt Arsenault;. 265