1; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefixes=SI,GCN %s 2; RUN: llc < %s -mtriple=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefixes=CI,GCN,SICIVI %s 3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefixes=VI,GCN,SICIVI %s 4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding -verify-machineinstrs -global-isel < %s | FileCheck --check-prefixes=GFX9_10,GCN,VIGFX9_10,SIVIGFX9_10 %s 5; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding -verify-machineinstrs -global-isel < %s | FileCheck --check-prefixes=GFX9_10,GCN,VIGFX9_10,SIVIGFX9_10 %s 6 7; SMRD load with an immediate offset. 8; GCN-LABEL: {{^}}smrd0: 9; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01 10; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 11define amdgpu_kernel void @smrd0(ptr addrspace(4) %ptr) { 12entry: 13 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 1 14 %1 = load i32, ptr addrspace(4) %0 15 store i32 %1, ptr addrspace(1) undef 16 ret void 17} 18 19; SMRD load with the largest possible immediate offset. 20; GCN-LABEL: {{^}}smrd1: 21; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}} 22; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc 23define amdgpu_kernel void @smrd1(ptr addrspace(4) %ptr) { 24entry: 25 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 255 26 %1 = load i32, ptr addrspace(4) %0 27 store i32 %1, ptr addrspace(1) undef 28 ret void 29} 30 31; SMRD load with an offset greater than the largest possible immediate. 32; GCN-LABEL: {{^}}smrd2: 33; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400 34; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] 35; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100 36; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 37; GCN: s_endpgm 38define amdgpu_kernel void @smrd2(ptr addrspace(4) %ptr) { 39entry: 40 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 256 41 %1 = load i32, ptr addrspace(4) %0 42 store i32 %1, ptr addrspace(1) undef 43 ret void 44} 45 46; SMRD load with a 64-bit offset 47; GCN-LABEL: {{^}}smrd3: 48; FIXME: There are too many copies here because we don't fold immediates 49; through REG_SEQUENCE 50; XSI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b 51; TODO: Add VI checks 52; XGCN: s_endpgm 53define amdgpu_kernel void @smrd3(ptr addrspace(4) %ptr) { 54entry: 55 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 4294967296 ; 2 ^ 32 56 %1 = load i32, ptr addrspace(4) %0 57 store i32 %1, ptr addrspace(1) undef 58 ret void 59} 60 61; SMRD load with the largest possible immediate offset on VI 62; GCN-LABEL: {{^}}smrd4: 63; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc 64; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 65; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff 66; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc 67; GFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc 68; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 69define amdgpu_kernel void @smrd4(ptr addrspace(4) %ptr) { 70entry: 71 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 262143 72 %1 = load i32, ptr addrspace(4) %0 73 store i32 %1, ptr addrspace(1) undef 74 ret void 75} 76 77; SMRD load with an offset greater than the largest possible immediate on VI 78; GCN-LABEL: {{^}}smrd5: 79; SIVIGFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000 80; SIVIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 81; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000 82; GCN: s_endpgm 83define amdgpu_kernel void @smrd5(ptr addrspace(4) %ptr) { 84entry: 85 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 262144 86 %1 = load i32, ptr addrspace(4) %0 87 store i32 %1, ptr addrspace(1) undef 88 ret void 89} 90 91; GFX9+ can use a signed immediate byte offset but not without sgpr[offset] 92; GCN-LABEL: {{^}}smrd6: 93; SICIVI: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, -4 94; SICIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0 95; GFX9_10: s_add_u32 s2, s2, -4 96; GFX9_10: s_addc_u32 s3, s3, -1 97; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0 98define amdgpu_kernel void @smrd6(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 { 99entry: 100 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 -1 101 %tmp1 = load i32, ptr addrspace(4) %tmp 102 store i32 %tmp1, ptr addrspace(1) %out 103 ret void 104} 105 106; Don't use a negative SGPR offset 107; GCN-LABEL: {{^}}smrd7: 108; GCN: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, 0xffe00000 109; SICIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0 110; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0 111define amdgpu_kernel void @smrd7(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 { 112entry: 113 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 -524288 114 %tmp1 = load i32, ptr addrspace(4) %tmp 115 store i32 %tmp1, ptr addrspace(1) %out 116 ret void 117} 118