xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll (revision e1472db58ef501264547ac8c97be2bf7c481ec04) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
3; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
4; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
5; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
6
7; ===================================================================================
8; V_ADD_LSHL_U32
9; ===================================================================================
10
11define amdgpu_ps float @add_shl(i32 %a, i32 %b, i32 %c) {
12; VI-LABEL: add_shl:
13; VI:       ; %bb.0:
14; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
15; VI-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
16; VI-NEXT:    ; return to shader part epilog
17;
18; GFX9-LABEL: add_shl:
19; GFX9:       ; %bb.0:
20; GFX9-NEXT:    v_add_lshl_u32 v0, v0, v1, v2
21; GFX9-NEXT:    ; return to shader part epilog
22;
23; GFX10-LABEL: add_shl:
24; GFX10:       ; %bb.0:
25; GFX10-NEXT:    v_add_lshl_u32 v0, v0, v1, v2
26; GFX10-NEXT:    ; return to shader part epilog
27  %x = add i32 %a, %b
28  %result = shl i32 %x, %c
29  %bc = bitcast i32 %result to float
30  ret float %bc
31}
32
33define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
34; VI-LABEL: add_shl_vgpr_c:
35; VI:       ; %bb.0:
36; VI-NEXT:    s_add_i32 s2, s2, s3
37; VI-NEXT:    v_lshlrev_b32_e64 v0, v0, s2
38; VI-NEXT:    ; return to shader part epilog
39;
40; GFX9-LABEL: add_shl_vgpr_c:
41; GFX9:       ; %bb.0:
42; GFX9-NEXT:    s_add_i32 s2, s2, s3
43; GFX9-NEXT:    v_lshlrev_b32_e64 v0, v0, s2
44; GFX9-NEXT:    ; return to shader part epilog
45;
46; GFX10-LABEL: add_shl_vgpr_c:
47; GFX10:       ; %bb.0:
48; GFX10-NEXT:    s_add_i32 s2, s2, s3
49; GFX10-NEXT:    v_lshlrev_b32_e64 v0, v0, s2
50; GFX10-NEXT:    ; return to shader part epilog
51  %x = add i32 %a, %b
52  %result = shl i32 %x, %c
53  %bc = bitcast i32 %result to float
54  ret float %bc
55}
56
57define amdgpu_ps float @add_shl_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
58; VI-LABEL: add_shl_vgpr_ac:
59; VI:       ; %bb.0:
60; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
61; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
62; VI-NEXT:    ; return to shader part epilog
63;
64; GFX9-LABEL: add_shl_vgpr_ac:
65; GFX9:       ; %bb.0:
66; GFX9-NEXT:    v_add_lshl_u32 v0, v0, s2, v1
67; GFX9-NEXT:    ; return to shader part epilog
68;
69; GFX10-LABEL: add_shl_vgpr_ac:
70; GFX10:       ; %bb.0:
71; GFX10-NEXT:    v_add_lshl_u32 v0, v0, s2, v1
72; GFX10-NEXT:    ; return to shader part epilog
73  %x = add i32 %a, %b
74  %result = shl i32 %x, %c
75  %bc = bitcast i32 %result to float
76  ret float %bc
77}
78
79define amdgpu_ps float @add_shl_vgpr_const(i32 %a, i32 %b) {
80; VI-LABEL: add_shl_vgpr_const:
81; VI:       ; %bb.0:
82; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
83; VI-NEXT:    v_lshlrev_b32_e32 v0, 9, v0
84; VI-NEXT:    ; return to shader part epilog
85;
86; GFX9-LABEL: add_shl_vgpr_const:
87; GFX9:       ; %bb.0:
88; GFX9-NEXT:    v_add_lshl_u32 v0, v0, v1, 9
89; GFX9-NEXT:    ; return to shader part epilog
90;
91; GFX10-LABEL: add_shl_vgpr_const:
92; GFX10:       ; %bb.0:
93; GFX10-NEXT:    v_add_lshl_u32 v0, v0, v1, 9
94; GFX10-NEXT:    ; return to shader part epilog
95  %x = add i32 %a, %b
96  %result = shl i32 %x, 9
97  %bc = bitcast i32 %result to float
98  ret float %bc
99}
100
101define amdgpu_ps float @add_shl_vgpr_const_inline_const(i32 %a) {
102; VI-LABEL: add_shl_vgpr_const_inline_const:
103; VI:       ; %bb.0:
104; VI-NEXT:    v_lshlrev_b32_e32 v0, 9, v0
105; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x7e800, v0
106; VI-NEXT:    ; return to shader part epilog
107;
108; GFX9-LABEL: add_shl_vgpr_const_inline_const:
109; GFX9:       ; %bb.0:
110; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7e800
111; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 9, v1
112; GFX9-NEXT:    ; return to shader part epilog
113;
114; GFX10-LABEL: add_shl_vgpr_const_inline_const:
115; GFX10:       ; %bb.0:
116; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 9, 0x7e800
117; GFX10-NEXT:    ; return to shader part epilog
118  %x = add i32 %a, 1012
119  %result = shl i32 %x, 9
120  %bc = bitcast i32 %result to float
121  ret float %bc
122}
123
124define amdgpu_ps float @add_shl_vgpr_inline_const_x2(i32 %a) {
125; VI-LABEL: add_shl_vgpr_inline_const_x2:
126; VI:       ; %bb.0:
127; VI-NEXT:    v_lshlrev_b32_e32 v0, 9, v0
128; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x600, v0
129; VI-NEXT:    ; return to shader part epilog
130;
131; GFX9-LABEL: add_shl_vgpr_inline_const_x2:
132; GFX9:       ; %bb.0:
133; GFX9-NEXT:    v_mov_b32_e32 v1, 0x600
134; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 9, v1
135; GFX9-NEXT:    ; return to shader part epilog
136;
137; GFX10-LABEL: add_shl_vgpr_inline_const_x2:
138; GFX10:       ; %bb.0:
139; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 9, 0x600
140; GFX10-NEXT:    ; return to shader part epilog
141  %x = add i32 %a, 3
142  %result = shl i32 %x, 9
143  %bc = bitcast i32 %result to float
144  ret float %bc
145}
146