1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming < %s | FileCheck %s 3 4; lookup table expand one register 5 6define <vscale x 16 x i8> @luti2_i8(<vscale x 16 x i8> %x) { 7; CHECK-LABEL: luti2_i8: 8; CHECK: // %bb.0: 9; CHECK-NEXT: luti2 z0.b, zt0, z0[15] 10; CHECK-NEXT: ret 11 %res = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %x, i32 15) 12 ret <vscale x 16 x i8> %res 13} 14 15define <vscale x 8 x i16> @luti2_i16(<vscale x 16 x i8> %x) { 16; CHECK-LABEL: luti2_i16: 17; CHECK: // %bb.0: 18; CHECK-NEXT: luti2 z0.h, zt0, z0[15] 19; CHECK-NEXT: ret 20 %res = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %x, i32 15) 21 ret <vscale x 8 x i16> %res 22} 23 24define <vscale x 4 x i32> @luti2_i32(<vscale x 16 x i8> %x) { 25; CHECK-LABEL: luti2_i32: 26; CHECK: // %bb.0: 27; CHECK-NEXT: luti2 z0.s, zt0, z0[15] 28; CHECK-NEXT: ret 29 %res = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %x, i32 15) 30 ret <vscale x 4 x i32> %res 31} 32 33define <vscale x 8 x half> @luti2_f16(<vscale x 16 x i8> %x) { 34; CHECK-LABEL: luti2_f16: 35; CHECK: // %bb.0: 36; CHECK-NEXT: luti2 z0.h, zt0, z0[15] 37; CHECK-NEXT: ret 38 %res = call <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %x, i32 15) 39 ret <vscale x 8 x half> %res 40} 41 42define <vscale x 8 x bfloat> @luti2_bf16(<vscale x 16 x i8> %x) { 43; CHECK-LABEL: luti2_bf16: 44; CHECK: // %bb.0: 45; CHECK-NEXT: luti2 z0.h, zt0, z0[15] 46; CHECK-NEXT: ret 47 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %x, i32 15) 48 ret <vscale x 8 x bfloat> %res 49} 50 51define <vscale x 4 x float> @luti2_f32(<vscale x 16 x i8> %x) { 52; CHECK-LABEL: luti2_f32: 53; CHECK: // %bb.0: 54; CHECK-NEXT: luti2 z0.s, zt0, z0[15] 55; CHECK-NEXT: ret 56 %res = call <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %x, i32 15) 57 ret <vscale x 4 x float> %res 58} 59 60declare <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32, <vscale x 16 x i8>, i32) 61declare <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32, <vscale x 16 x i8>, i32) 62declare <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32, <vscale x 16 x i8>, i32) 63declare <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32, <vscale x 16 x i8>, i32) 64declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32, <vscale x 16 x i8>, i32) 65declare <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32, <vscale x 16 x i8>, i32) 66