xref: /llvm-project/llvm/test/Analysis/MemorySSA/many-dom-backedge.ll (revision 8e44f13c6d294e6b4864441b22045b507782540c)
1; RUN: opt -aa-pipeline=basic-aa -passes='print<memoryssa>,verify<memoryssa>' -disable-output < %s 2>&1 | FileCheck %s
2;
3; many-dom.ll, with an added back-edge back into the switch.
4; Because people love their gotos.
5
6declare i1 @getBool() readnone
7
8define i32 @foo(ptr %p) {
9entry:
10  br label %loopbegin
11
12loopbegin:
13; CHECK: 9 = MemoryPhi({entry,liveOnEntry},{sw.epilog,6})
14; CHECK-NEXT: %n =
15  %n = phi i32 [ 0, %entry ], [ %1, %sw.epilog ]
16  %m = alloca i32, align 4
17  switch i32 %n, label %sw.default [
18    i32 0, label %sw.bb
19    i32 1, label %sw.bb1
20    i32 2, label %sw.bb2
21    i32 3, label %sw.bb3
22  ]
23
24sw.bb:
25; CHECK: 1 = MemoryDef(9)
26; CHECK-NEXT: store i32 1
27  store i32 1, ptr %m, align 4
28  br label %sw.epilog
29
30sw.bb1:
31; CHECK: 2 = MemoryDef(9)
32; CHECK-NEXT: store i32 2
33  store i32 2, ptr %m, align 4
34  br label %sw.epilog
35
36sw.bb2:
37; CHECK: 3 = MemoryDef(9)
38; CHECK-NEXT: store i32 3
39  store i32 3, ptr %m, align 4
40  br label %sw.epilog
41
42sw.bb3:
43; CHECK: 10 = MemoryPhi({loopbegin,9},{sw.almostexit,6})
44; CHECK: 4 = MemoryDef(10)
45; CHECK-NEXT: store i32 4
46  store i32 4, ptr %m, align 4
47  br label %sw.epilog
48
49sw.default:
50; CHECK: 5 = MemoryDef(9)
51; CHECK-NEXT: store i32 5
52  store i32 5, ptr %m, align 4
53  br label %sw.epilog
54
55sw.epilog:
56; CHECK: 8 = MemoryPhi({sw.default,5},{sw.bb3,4},{sw.bb,1},{sw.bb1,2},{sw.bb2,3})
57; CHECK-NEXT: MemoryUse(8)
58; CHECK-NEXT: %0 =
59  %0 = load i32, ptr %m, align 4
60; CHECK: 6 = MemoryDef(8)
61; CHECK-NEXT: %1 =
62  %1 = load volatile i32, ptr %p, align 4
63  %2 = icmp eq i32 %0, %1
64  br i1 %2, label %sw.almostexit, label %loopbegin
65
66sw.almostexit:
67  %3 = icmp eq i32 0, %1
68  br i1 %3, label %exit, label %sw.bb3
69
70exit:
71; CHECK: 7 = MemoryDef(6)
72; CHECK-NEXT: %4 = load volatile i32
73  %4 = load volatile i32, ptr %p, align 4
74  %5 = add i32 %4, %1
75  ret i32 %5
76}
77