1 //===- VPlanTransforms.h - Utility VPlan to VPlan transforms --------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file provides utility VPlan to VPlan transformations. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_TRANSFORMS_VECTORIZE_VPLANTRANSFORMS_H 14 #define LLVM_TRANSFORMS_VECTORIZE_VPLANTRANSFORMS_H 15 16 #include "VPlan.h" 17 #include "llvm/ADT/STLFunctionalExtras.h" 18 19 namespace llvm { 20 21 class InductionDescriptor; 22 class Instruction; 23 class PHINode; 24 class ScalarEvolution; 25 class PredicatedScalarEvolution; 26 class TargetLibraryInfo; 27 class VPBuilder; 28 class VPRecipeBuilder; 29 30 struct VPlanTransforms { 31 /// Replaces the VPInstructions in \p Plan with corresponding 32 /// widen recipes. 33 static void 34 VPInstructionsToVPRecipes(VPlanPtr &Plan, 35 function_ref<const InductionDescriptor *(PHINode *)> 36 GetIntOrFpInductionDescriptor, 37 ScalarEvolution &SE, const TargetLibraryInfo &TLI); 38 39 /// Sink users of fixed-order recurrences after the recipe defining their 40 /// previous value. Then introduce FirstOrderRecurrenceSplice VPInstructions 41 /// to combine the value from the recurrence phis and previous values. The 42 /// current implementation assumes all users can be sunk after the previous 43 /// value, which is enforced by earlier legality checks. 44 /// \returns true if all users of fixed-order recurrences could be re-arranged 45 /// as needed or false if it is not possible. In the latter case, \p Plan is 46 /// not valid. 47 static bool adjustFixedOrderRecurrences(VPlan &Plan, VPBuilder &Builder); 48 49 /// Clear NSW/NUW flags from reduction instructions if necessary. 50 static void clearReductionWrapFlags(VPlan &Plan); 51 52 /// Optimize \p Plan based on \p BestVF and \p BestUF. This may restrict the 53 /// resulting plan to \p BestVF and \p BestUF. 54 static void optimizeForVFAndUF(VPlan &Plan, ElementCount BestVF, 55 unsigned BestUF, 56 PredicatedScalarEvolution &PSE); 57 58 /// Apply VPlan-to-VPlan optimizations to \p Plan, including induction recipe 59 /// optimizations, dead recipe removal, replicate region optimizations and 60 /// block merging. 61 static void optimize(VPlan &Plan, ScalarEvolution &SE); 62 63 /// Wrap predicated VPReplicateRecipes with a mask operand in an if-then 64 /// region block and remove the mask operand. Optimize the created regions by 65 /// iteratively sinking scalar operands into the region, followed by merging 66 /// regions until no improvements are remaining. 67 static void createAndOptimizeReplicateRegions(VPlan &Plan); 68 69 /// Replace (ICMP_ULE, wide canonical IV, backedge-taken-count) checks with an 70 /// (active-lane-mask recipe, wide canonical IV, trip-count). If \p 71 /// UseActiveLaneMaskForControlFlow is true, introduce an 72 /// VPActiveLaneMaskPHIRecipe. If \p DataAndControlFlowWithoutRuntimeCheck is 73 /// true, no minimum-iteration runtime check will be created (during skeleton 74 /// creation) and instead it is handled using active-lane-mask. \p 75 /// DataAndControlFlowWithoutRuntimeCheck implies \p 76 /// UseActiveLaneMaskForControlFlow. 77 static void addActiveLaneMask(VPlan &Plan, 78 bool UseActiveLaneMaskForControlFlow, 79 bool DataAndControlFlowWithoutRuntimeCheck); 80 81 /// Insert truncates and extends for any truncated recipe. Redundant casts 82 /// will be folded later. 83 static void 84 truncateToMinimalBitwidths(VPlan &Plan, 85 const MapVector<Instruction *, uint64_t> &MinBWs, 86 LLVMContext &Ctx); 87 88 /// Drop poison flags from recipes that may generate a poison value that is 89 /// used after vectorization, even when their operands are not poison. Those 90 /// recipes meet the following conditions: 91 /// * Contribute to the address computation of a recipe generating a widen 92 /// memory load/store (VPWidenMemoryInstructionRecipe or 93 /// VPInterleaveRecipe). 94 /// * Such a widen memory load/store has at least one underlying Instruction 95 /// that is in a basic block that needs predication and after vectorization 96 /// the generated instruction won't be predicated. 97 /// Uses \p BlockNeedsPredication to check if a block needs predicating. 98 /// TODO: Replace BlockNeedsPredication callback with retrieving info from 99 /// VPlan directly. 100 static void dropPoisonGeneratingRecipes( 101 VPlan &Plan, function_ref<bool(BasicBlock *)> BlockNeedsPredication); 102 103 /// Add a VPEVLBasedIVPHIRecipe and related recipes to \p Plan and 104 /// replaces all uses except the canonical IV increment of 105 /// VPCanonicalIVPHIRecipe with a VPEVLBasedIVPHIRecipe. 106 /// VPCanonicalIVPHIRecipe is only used to control the loop after 107 /// this transformation. 108 /// \returns true if the transformation succeeds, or false if it doesn't. 109 static bool tryAddExplicitVectorLength(VPlan &Plan); 110 111 // For each Interleave Group in \p InterleaveGroups replace the Recipes 112 // widening its memory instructions with a single VPInterleaveRecipe at its 113 // insertion point. 114 static void createInterleaveGroups( 115 const SmallPtrSetImpl<const InterleaveGroup<Instruction> *> &InterleaveGroups, 116 VPRecipeBuilder &RecipeBuilder, bool ScalarEpilogueAllowed); 117 }; 118 119 } // namespace llvm 120 121 #endif // LLVM_TRANSFORMS_VECTORIZE_VPLANTRANSFORMS_H 122