1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler. 10 // It contains code to translate the data produced by the decoder into 11 // MCInsts. 12 // 13 // 14 // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and 15 // 64-bit X86 instruction sets. The main decode sequence for an assembly 16 // instruction in this disassembler is: 17 // 18 // 1. Read the prefix bytes and determine the attributes of the instruction. 19 // These attributes, recorded in enum attributeBits 20 // (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM 21 // provides a mapping from bitmasks to contexts, which are represented by 22 // enum InstructionContext (ibid.). 23 // 24 // 2. Read the opcode, and determine what kind of opcode it is. The 25 // disassembler distinguishes four kinds of opcodes, which are enumerated in 26 // OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte 27 // (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a 28 // (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context. 29 // 30 // 3. Depending on the opcode type, look in one of four ClassDecision structures 31 // (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which 32 // OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get 33 // a ModRMDecision (ibid.). 34 // 35 // 4. Some instructions, such as escape opcodes or extended opcodes, or even 36 // instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the 37 // ModR/M byte to complete decode. The ModRMDecision's type is an entry from 38 // ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the 39 // ModR/M byte is required and how to interpret it. 40 // 41 // 5. After resolving the ModRMDecision, the disassembler has a unique ID 42 // of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in 43 // INSTRUCTIONS_SYM yields the name of the instruction and the encodings and 44 // meanings of its operands. 45 // 46 // 6. For each operand, its encoding is an entry from OperandEncoding 47 // (X86DisassemblerDecoderCommon.h) and its type is an entry from 48 // OperandType (ibid.). The encoding indicates how to read it from the 49 // instruction; the type indicates how to interpret the value once it has 50 // been read. For example, a register operand could be stored in the R/M 51 // field of the ModR/M byte, the REG field of the ModR/M byte, or added to 52 // the main opcode. This is orthogonal from its meaning (an GPR or an XMM 53 // register, for instance). Given this information, the operands can be 54 // extracted and interpreted. 55 // 56 // 7. As the last step, the disassembler translates the instruction information 57 // and operands into a format understandable by the client - in this case, an 58 // MCInst for use by the MC infrastructure. 59 // 60 // The disassembler is broken broadly into two parts: the table emitter that 61 // emits the instruction decode tables discussed above during compilation, and 62 // the disassembler itself. The table emitter is documented in more detail in 63 // utils/TableGen/X86DisassemblerEmitter.h. 64 // 65 // X86Disassembler.cpp contains the code responsible for step 7, and for 66 // invoking the decoder to execute steps 1-6. 67 // X86DisassemblerDecoderCommon.h contains the definitions needed by both the 68 // table emitter and the disassembler. 69 // X86DisassemblerDecoder.h contains the public interface of the decoder, 70 // factored out into C for possible use by other projects. 71 // X86DisassemblerDecoder.c contains the source code of the decoder, which is 72 // responsible for steps 1-6. 73 // 74 //===----------------------------------------------------------------------===// 75 76 #include "MCTargetDesc/X86BaseInfo.h" 77 #include "MCTargetDesc/X86MCTargetDesc.h" 78 #include "TargetInfo/X86TargetInfo.h" 79 #include "X86DisassemblerDecoder.h" 80 #include "llvm/MC/MCContext.h" 81 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 82 #include "llvm/MC/MCExpr.h" 83 #include "llvm/MC/MCInst.h" 84 #include "llvm/MC/MCInstrInfo.h" 85 #include "llvm/MC/MCSubtargetInfo.h" 86 #include "llvm/MC/TargetRegistry.h" 87 #include "llvm/Support/Debug.h" 88 #include "llvm/Support/Format.h" 89 #include "llvm/Support/raw_ostream.h" 90 91 using namespace llvm; 92 using namespace llvm::X86Disassembler; 93 94 #define DEBUG_TYPE "x86-disassembler" 95 96 #define debug(s) LLVM_DEBUG(dbgs() << __LINE__ << ": " << s); 97 98 // Specifies whether a ModR/M byte is needed and (if so) which 99 // instruction each possible value of the ModR/M byte corresponds to. Once 100 // this information is known, we have narrowed down to a single instruction. 101 struct ModRMDecision { 102 uint8_t modrm_type; 103 uint16_t instructionIDs; 104 }; 105 106 // Specifies which set of ModR/M->instruction tables to look at 107 // given a particular opcode. 108 struct OpcodeDecision { 109 ModRMDecision modRMDecisions[256]; 110 }; 111 112 // Specifies which opcode->instruction tables to look at given 113 // a particular context (set of attributes). Since there are many possible 114 // contexts, the decoder first uses CONTEXTS_SYM to determine which context 115 // applies given a specific set of attributes. Hence there are only IC_max 116 // entries in this table, rather than 2^(ATTR_max). 117 struct ContextDecision { 118 OpcodeDecision opcodeDecisions[IC_max]; 119 }; 120 121 #include "X86GenDisassemblerTables.inc" 122 123 static InstrUID decode(OpcodeType type, InstructionContext insnContext, 124 uint8_t opcode, uint8_t modRM) { 125 const struct ModRMDecision *dec; 126 127 switch (type) { 128 case ONEBYTE: 129 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 130 break; 131 case TWOBYTE: 132 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 133 break; 134 case THREEBYTE_38: 135 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 136 break; 137 case THREEBYTE_3A: 138 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 139 break; 140 case XOP8_MAP: 141 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 142 break; 143 case XOP9_MAP: 144 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 145 break; 146 case XOPA_MAP: 147 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 148 break; 149 case THREEDNOW_MAP: 150 dec = 151 &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 152 break; 153 case MAP4: 154 dec = &MAP4_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 155 break; 156 case MAP5: 157 dec = &MAP5_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 158 break; 159 case MAP6: 160 dec = &MAP6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 161 break; 162 case MAP7: 163 dec = &MAP7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 164 break; 165 } 166 167 switch (dec->modrm_type) { 168 default: 169 llvm_unreachable("Corrupt table! Unknown modrm_type"); 170 return 0; 171 case MODRM_ONEENTRY: 172 return modRMTable[dec->instructionIDs]; 173 case MODRM_SPLITRM: 174 if (modFromModRM(modRM) == 0x3) 175 return modRMTable[dec->instructionIDs + 1]; 176 return modRMTable[dec->instructionIDs]; 177 case MODRM_SPLITREG: 178 if (modFromModRM(modRM) == 0x3) 179 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3) + 8]; 180 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)]; 181 case MODRM_SPLITMISC: 182 if (modFromModRM(modRM) == 0x3) 183 return modRMTable[dec->instructionIDs + (modRM & 0x3f) + 8]; 184 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)]; 185 case MODRM_FULL: 186 return modRMTable[dec->instructionIDs + modRM]; 187 } 188 } 189 190 static bool peek(struct InternalInstruction *insn, uint8_t &byte) { 191 uint64_t offset = insn->readerCursor - insn->startLocation; 192 if (offset >= insn->bytes.size()) 193 return true; 194 byte = insn->bytes[offset]; 195 return false; 196 } 197 198 template <typename T> static bool consume(InternalInstruction *insn, T &ptr) { 199 auto r = insn->bytes; 200 uint64_t offset = insn->readerCursor - insn->startLocation; 201 if (offset + sizeof(T) > r.size()) 202 return true; 203 ptr = support::endian::read<T>(&r[offset], llvm::endianness::little); 204 insn->readerCursor += sizeof(T); 205 return false; 206 } 207 208 static bool isREX(struct InternalInstruction *insn, uint8_t prefix) { 209 return insn->mode == MODE_64BIT && prefix >= 0x40 && prefix <= 0x4f; 210 } 211 212 static bool isREX2(struct InternalInstruction *insn, uint8_t prefix) { 213 return insn->mode == MODE_64BIT && prefix == 0xd5; 214 } 215 216 // Consumes all of an instruction's prefix bytes, and marks the 217 // instruction as having them. Also sets the instruction's default operand, 218 // address, and other relevant data sizes to report operands correctly. 219 // 220 // insn must not be empty. 221 static int readPrefixes(struct InternalInstruction *insn) { 222 bool isPrefix = true; 223 uint8_t byte = 0; 224 uint8_t nextByte; 225 226 LLVM_DEBUG(dbgs() << "readPrefixes()"); 227 228 while (isPrefix) { 229 // If we fail reading prefixes, just stop here and let the opcode reader 230 // deal with it. 231 if (consume(insn, byte)) 232 break; 233 234 // If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then 235 // break and let it be disassembled as a normal "instruction". 236 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0) // LOCK 237 break; 238 239 if ((byte == 0xf2 || byte == 0xf3) && !peek(insn, nextByte)) { 240 // If the byte is 0xf2 or 0xf3, and any of the following conditions are 241 // met: 242 // - it is followed by a LOCK (0xf0) prefix 243 // - it is followed by an xchg instruction 244 // then it should be disassembled as a xacquire/xrelease not repne/rep. 245 if (((nextByte == 0xf0) || 246 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) { 247 insn->xAcquireRelease = true; 248 if (!(byte == 0xf3 && nextByte == 0x90)) // PAUSE instruction support 249 break; 250 } 251 // Also if the byte is 0xf3, and the following condition is met: 252 // - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or 253 // "mov mem, imm" (opcode 0xc6/0xc7) instructions. 254 // then it should be disassembled as an xrelease not rep. 255 if (byte == 0xf3 && (nextByte == 0x88 || nextByte == 0x89 || 256 nextByte == 0xc6 || nextByte == 0xc7)) { 257 insn->xAcquireRelease = true; 258 break; 259 } 260 if (isREX(insn, nextByte)) { 261 uint8_t nnextByte; 262 // Go to REX prefix after the current one 263 if (consume(insn, nnextByte)) 264 return -1; 265 // We should be able to read next byte after REX prefix 266 if (peek(insn, nnextByte)) 267 return -1; 268 --insn->readerCursor; 269 } 270 } 271 272 switch (byte) { 273 case 0xf0: // LOCK 274 insn->hasLockPrefix = true; 275 break; 276 case 0xf2: // REPNE/REPNZ 277 case 0xf3: { // REP or REPE/REPZ 278 uint8_t nextByte; 279 if (peek(insn, nextByte)) 280 break; 281 // TODO: 282 // 1. There could be several 0x66 283 // 2. if (nextByte == 0x66) and nextNextByte != 0x0f then 284 // it's not mandatory prefix 285 // 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need 286 // 0x0f exactly after it to be mandatory prefix 287 if (isREX(insn, nextByte) || nextByte == 0x0f || nextByte == 0x66) 288 // The last of 0xf2 /0xf3 is mandatory prefix 289 insn->mandatoryPrefix = byte; 290 insn->repeatPrefix = byte; 291 break; 292 } 293 case 0x2e: // CS segment override -OR- Branch not taken 294 insn->segmentOverride = SEG_OVERRIDE_CS; 295 break; 296 case 0x36: // SS segment override -OR- Branch taken 297 insn->segmentOverride = SEG_OVERRIDE_SS; 298 break; 299 case 0x3e: // DS segment override 300 insn->segmentOverride = SEG_OVERRIDE_DS; 301 break; 302 case 0x26: // ES segment override 303 insn->segmentOverride = SEG_OVERRIDE_ES; 304 break; 305 case 0x64: // FS segment override 306 insn->segmentOverride = SEG_OVERRIDE_FS; 307 break; 308 case 0x65: // GS segment override 309 insn->segmentOverride = SEG_OVERRIDE_GS; 310 break; 311 case 0x66: { // Operand-size override { 312 uint8_t nextByte; 313 insn->hasOpSize = true; 314 if (peek(insn, nextByte)) 315 break; 316 // 0x66 can't overwrite existing mandatory prefix and should be ignored 317 if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte))) 318 insn->mandatoryPrefix = byte; 319 break; 320 } 321 case 0x67: // Address-size override 322 insn->hasAdSize = true; 323 break; 324 default: // Not a prefix byte 325 isPrefix = false; 326 break; 327 } 328 329 if (isPrefix) 330 LLVM_DEBUG(dbgs() << format("Found prefix 0x%hhx", byte)); 331 } 332 333 insn->vectorExtensionType = TYPE_NO_VEX_XOP; 334 335 if (byte == 0x62) { 336 uint8_t byte1, byte2; 337 if (consume(insn, byte1)) { 338 LLVM_DEBUG(dbgs() << "Couldn't read second byte of EVEX prefix"); 339 return -1; 340 } 341 342 if (peek(insn, byte2)) { 343 LLVM_DEBUG(dbgs() << "Couldn't read third byte of EVEX prefix"); 344 return -1; 345 } 346 347 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)) { 348 insn->vectorExtensionType = TYPE_EVEX; 349 } else { 350 --insn->readerCursor; // unconsume byte1 351 --insn->readerCursor; // unconsume byte 352 } 353 354 if (insn->vectorExtensionType == TYPE_EVEX) { 355 insn->vectorExtensionPrefix[0] = byte; 356 insn->vectorExtensionPrefix[1] = byte1; 357 if (consume(insn, insn->vectorExtensionPrefix[2])) { 358 LLVM_DEBUG(dbgs() << "Couldn't read third byte of EVEX prefix"); 359 return -1; 360 } 361 if (consume(insn, insn->vectorExtensionPrefix[3])) { 362 LLVM_DEBUG(dbgs() << "Couldn't read fourth byte of EVEX prefix"); 363 return -1; 364 } 365 366 if (insn->mode == MODE_64BIT) { 367 // We simulate the REX prefix for simplicity's sake 368 insn->rexPrefix = 0x40 | 369 (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) | 370 (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) | 371 (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) | 372 (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0); 373 374 // We simulate the REX2 prefix for simplicity's sake 375 insn->rex2ExtensionPrefix[1] = 376 (r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 6) | 377 (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) << 5) | 378 (b2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4); 379 } 380 381 LLVM_DEBUG( 382 dbgs() << format( 383 "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx", 384 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], 385 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3])); 386 } 387 } else if (byte == 0xc4) { 388 uint8_t byte1; 389 if (peek(insn, byte1)) { 390 LLVM_DEBUG(dbgs() << "Couldn't read second byte of VEX"); 391 return -1; 392 } 393 394 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) 395 insn->vectorExtensionType = TYPE_VEX_3B; 396 else 397 --insn->readerCursor; 398 399 if (insn->vectorExtensionType == TYPE_VEX_3B) { 400 insn->vectorExtensionPrefix[0] = byte; 401 consume(insn, insn->vectorExtensionPrefix[1]); 402 consume(insn, insn->vectorExtensionPrefix[2]); 403 404 // We simulate the REX prefix for simplicity's sake 405 406 if (insn->mode == MODE_64BIT) 407 insn->rexPrefix = 0x40 | 408 (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3) | 409 (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2) | 410 (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1) | 411 (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0); 412 413 LLVM_DEBUG(dbgs() << format("Found VEX prefix 0x%hhx 0x%hhx 0x%hhx", 414 insn->vectorExtensionPrefix[0], 415 insn->vectorExtensionPrefix[1], 416 insn->vectorExtensionPrefix[2])); 417 } 418 } else if (byte == 0xc5) { 419 uint8_t byte1; 420 if (peek(insn, byte1)) { 421 LLVM_DEBUG(dbgs() << "Couldn't read second byte of VEX"); 422 return -1; 423 } 424 425 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) 426 insn->vectorExtensionType = TYPE_VEX_2B; 427 else 428 --insn->readerCursor; 429 430 if (insn->vectorExtensionType == TYPE_VEX_2B) { 431 insn->vectorExtensionPrefix[0] = byte; 432 consume(insn, insn->vectorExtensionPrefix[1]); 433 434 if (insn->mode == MODE_64BIT) 435 insn->rexPrefix = 436 0x40 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2); 437 438 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { 439 default: 440 break; 441 case VEX_PREFIX_66: 442 insn->hasOpSize = true; 443 break; 444 } 445 446 LLVM_DEBUG(dbgs() << format("Found VEX prefix 0x%hhx 0x%hhx", 447 insn->vectorExtensionPrefix[0], 448 insn->vectorExtensionPrefix[1])); 449 } 450 } else if (byte == 0x8f) { 451 uint8_t byte1; 452 if (peek(insn, byte1)) { 453 LLVM_DEBUG(dbgs() << "Couldn't read second byte of XOP"); 454 return -1; 455 } 456 457 if ((byte1 & 0x38) != 0x0) // 0 in these 3 bits is a POP instruction. 458 insn->vectorExtensionType = TYPE_XOP; 459 else 460 --insn->readerCursor; 461 462 if (insn->vectorExtensionType == TYPE_XOP) { 463 insn->vectorExtensionPrefix[0] = byte; 464 consume(insn, insn->vectorExtensionPrefix[1]); 465 consume(insn, insn->vectorExtensionPrefix[2]); 466 467 // We simulate the REX prefix for simplicity's sake 468 469 if (insn->mode == MODE_64BIT) 470 insn->rexPrefix = 0x40 | 471 (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3) | 472 (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2) | 473 (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1) | 474 (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0); 475 476 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { 477 default: 478 break; 479 case VEX_PREFIX_66: 480 insn->hasOpSize = true; 481 break; 482 } 483 484 LLVM_DEBUG(dbgs() << format("Found XOP prefix 0x%hhx 0x%hhx 0x%hhx", 485 insn->vectorExtensionPrefix[0], 486 insn->vectorExtensionPrefix[1], 487 insn->vectorExtensionPrefix[2])); 488 } 489 } else if (isREX2(insn, byte)) { 490 uint8_t byte1; 491 if (peek(insn, byte1)) { 492 LLVM_DEBUG(dbgs() << "Couldn't read second byte of REX2"); 493 return -1; 494 } 495 insn->rex2ExtensionPrefix[0] = byte; 496 consume(insn, insn->rex2ExtensionPrefix[1]); 497 498 // We simulate the REX prefix for simplicity's sake 499 insn->rexPrefix = 0x40 | (wFromREX2(insn->rex2ExtensionPrefix[1]) << 3) | 500 (rFromREX2(insn->rex2ExtensionPrefix[1]) << 2) | 501 (xFromREX2(insn->rex2ExtensionPrefix[1]) << 1) | 502 (bFromREX2(insn->rex2ExtensionPrefix[1]) << 0); 503 LLVM_DEBUG(dbgs() << format("Found REX2 prefix 0x%hhx 0x%hhx", 504 insn->rex2ExtensionPrefix[0], 505 insn->rex2ExtensionPrefix[1])); 506 } else if (isREX(insn, byte)) { 507 if (peek(insn, nextByte)) 508 return -1; 509 insn->rexPrefix = byte; 510 LLVM_DEBUG(dbgs() << format("Found REX prefix 0x%hhx", byte)); 511 } else 512 --insn->readerCursor; 513 514 if (insn->mode == MODE_16BIT) { 515 insn->registerSize = (insn->hasOpSize ? 4 : 2); 516 insn->addressSize = (insn->hasAdSize ? 4 : 2); 517 insn->displacementSize = (insn->hasAdSize ? 4 : 2); 518 insn->immediateSize = (insn->hasOpSize ? 4 : 2); 519 } else if (insn->mode == MODE_32BIT) { 520 insn->registerSize = (insn->hasOpSize ? 2 : 4); 521 insn->addressSize = (insn->hasAdSize ? 2 : 4); 522 insn->displacementSize = (insn->hasAdSize ? 2 : 4); 523 insn->immediateSize = (insn->hasOpSize ? 2 : 4); 524 } else if (insn->mode == MODE_64BIT) { 525 insn->displacementSize = 4; 526 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) { 527 insn->registerSize = 8; 528 insn->addressSize = (insn->hasAdSize ? 4 : 8); 529 insn->immediateSize = 4; 530 insn->hasOpSize = false; 531 } else { 532 insn->registerSize = (insn->hasOpSize ? 2 : 4); 533 insn->addressSize = (insn->hasAdSize ? 4 : 8); 534 insn->immediateSize = (insn->hasOpSize ? 2 : 4); 535 } 536 } 537 538 return 0; 539 } 540 541 // Consumes the SIB byte to determine addressing information. 542 static int readSIB(struct InternalInstruction *insn) { 543 SIBBase sibBaseBase = SIB_BASE_NONE; 544 uint8_t index, base; 545 546 LLVM_DEBUG(dbgs() << "readSIB()"); 547 switch (insn->addressSize) { 548 case 2: 549 default: 550 llvm_unreachable("SIB-based addressing doesn't work in 16-bit mode"); 551 case 4: 552 insn->sibIndexBase = SIB_INDEX_EAX; 553 sibBaseBase = SIB_BASE_EAX; 554 break; 555 case 8: 556 insn->sibIndexBase = SIB_INDEX_RAX; 557 sibBaseBase = SIB_BASE_RAX; 558 break; 559 } 560 561 if (consume(insn, insn->sib)) 562 return -1; 563 564 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3) | 565 (x2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); 566 567 if (index == 0x4) { 568 insn->sibIndex = SIB_INDEX_NONE; 569 } else { 570 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index); 571 } 572 573 insn->sibScale = 1 << scaleFromSIB(insn->sib); 574 575 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3) | 576 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); 577 578 switch (base) { 579 case 0x5: 580 case 0xd: 581 switch (modFromModRM(insn->modRM)) { 582 case 0x0: 583 insn->eaDisplacement = EA_DISP_32; 584 insn->sibBase = SIB_BASE_NONE; 585 break; 586 case 0x1: 587 insn->eaDisplacement = EA_DISP_8; 588 insn->sibBase = (SIBBase)(sibBaseBase + base); 589 break; 590 case 0x2: 591 insn->eaDisplacement = EA_DISP_32; 592 insn->sibBase = (SIBBase)(sibBaseBase + base); 593 break; 594 default: 595 llvm_unreachable("Cannot have Mod = 0b11 and a SIB byte"); 596 } 597 break; 598 default: 599 insn->sibBase = (SIBBase)(sibBaseBase + base); 600 break; 601 } 602 603 return 0; 604 } 605 606 static int readDisplacement(struct InternalInstruction *insn) { 607 int8_t d8; 608 int16_t d16; 609 int32_t d32; 610 LLVM_DEBUG(dbgs() << "readDisplacement()"); 611 612 insn->displacementOffset = insn->readerCursor - insn->startLocation; 613 switch (insn->eaDisplacement) { 614 case EA_DISP_NONE: 615 break; 616 case EA_DISP_8: 617 if (consume(insn, d8)) 618 return -1; 619 insn->displacement = d8; 620 break; 621 case EA_DISP_16: 622 if (consume(insn, d16)) 623 return -1; 624 insn->displacement = d16; 625 break; 626 case EA_DISP_32: 627 if (consume(insn, d32)) 628 return -1; 629 insn->displacement = d32; 630 break; 631 } 632 633 return 0; 634 } 635 636 // Consumes all addressing information (ModR/M byte, SIB byte, and displacement. 637 static int readModRM(struct InternalInstruction *insn) { 638 uint8_t mod, rm, reg; 639 LLVM_DEBUG(dbgs() << "readModRM()"); 640 641 if (insn->consumedModRM) 642 return 0; 643 644 if (consume(insn, insn->modRM)) 645 return -1; 646 insn->consumedModRM = true; 647 648 mod = modFromModRM(insn->modRM); 649 rm = rmFromModRM(insn->modRM); 650 reg = regFromModRM(insn->modRM); 651 652 // This goes by insn->registerSize to pick the correct register, which messes 653 // up if we're using (say) XMM or 8-bit register operands. That gets fixed in 654 // fixupReg(). 655 switch (insn->registerSize) { 656 case 2: 657 insn->regBase = MODRM_REG_AX; 658 insn->eaRegBase = EA_REG_AX; 659 break; 660 case 4: 661 insn->regBase = MODRM_REG_EAX; 662 insn->eaRegBase = EA_REG_EAX; 663 break; 664 case 8: 665 insn->regBase = MODRM_REG_RAX; 666 insn->eaRegBase = EA_REG_RAX; 667 break; 668 } 669 670 reg |= (rFromREX(insn->rexPrefix) << 3) | 671 (r2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); 672 rm |= (bFromREX(insn->rexPrefix) << 3) | 673 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); 674 675 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT) 676 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; 677 678 insn->reg = (Reg)(insn->regBase + reg); 679 680 switch (insn->addressSize) { 681 case 2: { 682 EABase eaBaseBase = EA_BASE_BX_SI; 683 684 switch (mod) { 685 case 0x0: 686 if (rm == 0x6) { 687 insn->eaBase = EA_BASE_NONE; 688 insn->eaDisplacement = EA_DISP_16; 689 if (readDisplacement(insn)) 690 return -1; 691 } else { 692 insn->eaBase = (EABase)(eaBaseBase + rm); 693 insn->eaDisplacement = EA_DISP_NONE; 694 } 695 break; 696 case 0x1: 697 insn->eaBase = (EABase)(eaBaseBase + rm); 698 insn->eaDisplacement = EA_DISP_8; 699 insn->displacementSize = 1; 700 if (readDisplacement(insn)) 701 return -1; 702 break; 703 case 0x2: 704 insn->eaBase = (EABase)(eaBaseBase + rm); 705 insn->eaDisplacement = EA_DISP_16; 706 if (readDisplacement(insn)) 707 return -1; 708 break; 709 case 0x3: 710 insn->eaBase = (EABase)(insn->eaRegBase + rm); 711 if (readDisplacement(insn)) 712 return -1; 713 break; 714 } 715 break; 716 } 717 case 4: 718 case 8: { 719 EABase eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX); 720 721 switch (mod) { 722 case 0x0: 723 insn->eaDisplacement = EA_DISP_NONE; // readSIB may override this 724 // In determining whether RIP-relative mode is used (rm=5), 725 // or whether a SIB byte is present (rm=4), 726 // the extension bits (REX.b and EVEX.x) are ignored. 727 switch (rm & 7) { 728 case 0x4: // SIB byte is present 729 insn->eaBase = (insn->addressSize == 4 ? EA_BASE_sib : EA_BASE_sib64); 730 if (readSIB(insn) || readDisplacement(insn)) 731 return -1; 732 break; 733 case 0x5: // RIP-relative 734 insn->eaBase = EA_BASE_NONE; 735 insn->eaDisplacement = EA_DISP_32; 736 if (readDisplacement(insn)) 737 return -1; 738 break; 739 default: 740 insn->eaBase = (EABase)(eaBaseBase + rm); 741 break; 742 } 743 break; 744 case 0x1: 745 insn->displacementSize = 1; 746 [[fallthrough]]; 747 case 0x2: 748 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32); 749 switch (rm & 7) { 750 case 0x4: // SIB byte is present 751 insn->eaBase = EA_BASE_sib; 752 if (readSIB(insn) || readDisplacement(insn)) 753 return -1; 754 break; 755 default: 756 insn->eaBase = (EABase)(eaBaseBase + rm); 757 if (readDisplacement(insn)) 758 return -1; 759 break; 760 } 761 break; 762 case 0x3: 763 insn->eaDisplacement = EA_DISP_NONE; 764 insn->eaBase = (EABase)(insn->eaRegBase + rm); 765 break; 766 } 767 break; 768 } 769 } // switch (insn->addressSize) 770 771 return 0; 772 } 773 774 #define GENERIC_FIXUP_FUNC(name, base, prefix) \ 775 static uint16_t name(struct InternalInstruction *insn, OperandType type, \ 776 uint8_t index, uint8_t *valid) { \ 777 *valid = 1; \ 778 switch (type) { \ 779 default: \ 780 debug("Unhandled register type"); \ 781 *valid = 0; \ 782 return 0; \ 783 case TYPE_Rv: \ 784 return base + index; \ 785 case TYPE_R8: \ 786 if (insn->rexPrefix && index >= 4 && index <= 7) \ 787 return prefix##_SPL + (index - 4); \ 788 else \ 789 return prefix##_AL + index; \ 790 case TYPE_R16: \ 791 return prefix##_AX + index; \ 792 case TYPE_R32: \ 793 return prefix##_EAX + index; \ 794 case TYPE_R64: \ 795 return prefix##_RAX + index; \ 796 case TYPE_ZMM: \ 797 return prefix##_ZMM0 + index; \ 798 case TYPE_YMM: \ 799 return prefix##_YMM0 + index; \ 800 case TYPE_XMM: \ 801 return prefix##_XMM0 + index; \ 802 case TYPE_TMM: \ 803 if (index > 7) \ 804 *valid = 0; \ 805 return prefix##_TMM0 + index; \ 806 case TYPE_VK: \ 807 index &= 0xf; \ 808 if (index > 7) \ 809 *valid = 0; \ 810 return prefix##_K0 + index; \ 811 case TYPE_VK_PAIR: \ 812 if (index > 7) \ 813 *valid = 0; \ 814 return prefix##_K0_K1 + (index / 2); \ 815 case TYPE_MM64: \ 816 return prefix##_MM0 + (index & 0x7); \ 817 case TYPE_SEGMENTREG: \ 818 if ((index & 7) > 5) \ 819 *valid = 0; \ 820 return prefix##_ES + (index & 7); \ 821 case TYPE_DEBUGREG: \ 822 return prefix##_DR0 + index; \ 823 case TYPE_CONTROLREG: \ 824 return prefix##_CR0 + index; \ 825 case TYPE_MVSIBX: \ 826 return prefix##_XMM0 + index; \ 827 case TYPE_MVSIBY: \ 828 return prefix##_YMM0 + index; \ 829 case TYPE_MVSIBZ: \ 830 return prefix##_ZMM0 + index; \ 831 } \ 832 } 833 834 // Consult an operand type to determine the meaning of the reg or R/M field. If 835 // the operand is an XMM operand, for example, an operand would be XMM0 instead 836 // of AX, which readModRM() would otherwise misinterpret it as. 837 // 838 // @param insn - The instruction containing the operand. 839 // @param type - The operand type. 840 // @param index - The existing value of the field as reported by readModRM(). 841 // @param valid - The address of a uint8_t. The target is set to 1 if the 842 // field is valid for the register class; 0 if not. 843 // @return - The proper value. 844 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG) 845 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG) 846 847 // Consult an operand specifier to determine which of the fixup*Value functions 848 // to use in correcting readModRM()'ss interpretation. 849 // 850 // @param insn - See fixup*Value(). 851 // @param op - The operand specifier. 852 // @return - 0 if fixup was successful; -1 if the register returned was 853 // invalid for its class. 854 static int fixupReg(struct InternalInstruction *insn, 855 const struct OperandSpecifier *op) { 856 uint8_t valid; 857 LLVM_DEBUG(dbgs() << "fixupReg()"); 858 859 switch ((OperandEncoding)op->encoding) { 860 default: 861 debug("Expected a REG or R/M encoding in fixupReg"); 862 return -1; 863 case ENCODING_VVVV: 864 insn->vvvv = 865 (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid); 866 if (!valid) 867 return -1; 868 break; 869 case ENCODING_REG: 870 insn->reg = (Reg)fixupRegValue(insn, (OperandType)op->type, 871 insn->reg - insn->regBase, &valid); 872 if (!valid) 873 return -1; 874 break; 875 CASE_ENCODING_RM: 876 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT && 877 modFromModRM(insn->modRM) == 3) { 878 // EVEX_X can extend the register id to 32 for a non-GPR register that is 879 // encoded in RM. 880 // mode : MODE_64_BIT 881 // Only 8 vector registers are available in 32 bit mode 882 // mod : 3 883 // RM encodes a register 884 switch (op->type) { 885 case TYPE_Rv: 886 case TYPE_R8: 887 case TYPE_R16: 888 case TYPE_R32: 889 case TYPE_R64: 890 break; 891 default: 892 insn->eaBase = 893 (EABase)(insn->eaBase + 894 (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4)); 895 break; 896 } 897 } 898 [[fallthrough]]; 899 case ENCODING_SIB: 900 if (insn->eaBase >= insn->eaRegBase) { 901 insn->eaBase = (EABase)fixupRMValue( 902 insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid); 903 if (!valid) 904 return -1; 905 } 906 break; 907 } 908 909 return 0; 910 } 911 912 // Read the opcode (except the ModR/M byte in the case of extended or escape 913 // opcodes). 914 static bool readOpcode(struct InternalInstruction *insn) { 915 uint8_t current; 916 LLVM_DEBUG(dbgs() << "readOpcode()"); 917 918 insn->opcodeType = ONEBYTE; 919 if (insn->vectorExtensionType == TYPE_EVEX) { 920 switch (mmmFromEVEX2of4(insn->vectorExtensionPrefix[1])) { 921 default: 922 LLVM_DEBUG( 923 dbgs() << format("Unhandled mmm field for instruction (0x%hhx)", 924 mmmFromEVEX2of4(insn->vectorExtensionPrefix[1]))); 925 return true; 926 case VEX_LOB_0F: 927 insn->opcodeType = TWOBYTE; 928 return consume(insn, insn->opcode); 929 case VEX_LOB_0F38: 930 insn->opcodeType = THREEBYTE_38; 931 return consume(insn, insn->opcode); 932 case VEX_LOB_0F3A: 933 insn->opcodeType = THREEBYTE_3A; 934 return consume(insn, insn->opcode); 935 case VEX_LOB_MAP4: 936 insn->opcodeType = MAP4; 937 return consume(insn, insn->opcode); 938 case VEX_LOB_MAP5: 939 insn->opcodeType = MAP5; 940 return consume(insn, insn->opcode); 941 case VEX_LOB_MAP6: 942 insn->opcodeType = MAP6; 943 return consume(insn, insn->opcode); 944 } 945 } else if (insn->vectorExtensionType == TYPE_VEX_3B) { 946 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) { 947 default: 948 LLVM_DEBUG( 949 dbgs() << format("Unhandled m-mmmm field for instruction (0x%hhx)", 950 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]))); 951 return true; 952 case VEX_LOB_0F: 953 insn->opcodeType = TWOBYTE; 954 return consume(insn, insn->opcode); 955 case VEX_LOB_0F38: 956 insn->opcodeType = THREEBYTE_38; 957 return consume(insn, insn->opcode); 958 case VEX_LOB_0F3A: 959 insn->opcodeType = THREEBYTE_3A; 960 return consume(insn, insn->opcode); 961 case VEX_LOB_MAP5: 962 insn->opcodeType = MAP5; 963 return consume(insn, insn->opcode); 964 case VEX_LOB_MAP6: 965 insn->opcodeType = MAP6; 966 return consume(insn, insn->opcode); 967 case VEX_LOB_MAP7: 968 insn->opcodeType = MAP7; 969 return consume(insn, insn->opcode); 970 } 971 } else if (insn->vectorExtensionType == TYPE_VEX_2B) { 972 insn->opcodeType = TWOBYTE; 973 return consume(insn, insn->opcode); 974 } else if (insn->vectorExtensionType == TYPE_XOP) { 975 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) { 976 default: 977 LLVM_DEBUG( 978 dbgs() << format("Unhandled m-mmmm field for instruction (0x%hhx)", 979 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]))); 980 return true; 981 case XOP_MAP_SELECT_8: 982 insn->opcodeType = XOP8_MAP; 983 return consume(insn, insn->opcode); 984 case XOP_MAP_SELECT_9: 985 insn->opcodeType = XOP9_MAP; 986 return consume(insn, insn->opcode); 987 case XOP_MAP_SELECT_A: 988 insn->opcodeType = XOPA_MAP; 989 return consume(insn, insn->opcode); 990 } 991 } else if (mFromREX2(insn->rex2ExtensionPrefix[1])) { 992 // m bit indicates opcode map 1 993 insn->opcodeType = TWOBYTE; 994 return consume(insn, insn->opcode); 995 } 996 997 if (consume(insn, current)) 998 return true; 999 1000 if (current == 0x0f) { 1001 LLVM_DEBUG( 1002 dbgs() << format("Found a two-byte escape prefix (0x%hhx)", current)); 1003 if (consume(insn, current)) 1004 return true; 1005 1006 if (current == 0x38) { 1007 LLVM_DEBUG(dbgs() << format("Found a three-byte escape prefix (0x%hhx)", 1008 current)); 1009 if (consume(insn, current)) 1010 return true; 1011 1012 insn->opcodeType = THREEBYTE_38; 1013 } else if (current == 0x3a) { 1014 LLVM_DEBUG(dbgs() << format("Found a three-byte escape prefix (0x%hhx)", 1015 current)); 1016 if (consume(insn, current)) 1017 return true; 1018 1019 insn->opcodeType = THREEBYTE_3A; 1020 } else if (current == 0x0f) { 1021 LLVM_DEBUG( 1022 dbgs() << format("Found a 3dnow escape prefix (0x%hhx)", current)); 1023 1024 // Consume operands before the opcode to comply with the 3DNow encoding 1025 if (readModRM(insn)) 1026 return true; 1027 1028 if (consume(insn, current)) 1029 return true; 1030 1031 insn->opcodeType = THREEDNOW_MAP; 1032 } else { 1033 LLVM_DEBUG(dbgs() << "Didn't find a three-byte escape prefix"); 1034 insn->opcodeType = TWOBYTE; 1035 } 1036 } else if (insn->mandatoryPrefix) 1037 // The opcode with mandatory prefix must start with opcode escape. 1038 // If not it's legacy repeat prefix 1039 insn->mandatoryPrefix = 0; 1040 1041 // At this point we have consumed the full opcode. 1042 // Anything we consume from here on must be unconsumed. 1043 insn->opcode = current; 1044 1045 return false; 1046 } 1047 1048 // Determine whether equiv is the 16-bit equivalent of orig (32-bit or 64-bit). 1049 static bool is16BitEquivalent(const char *orig, const char *equiv) { 1050 for (int i = 0;; i++) { 1051 if (orig[i] == '\0' && equiv[i] == '\0') 1052 return true; 1053 if (orig[i] == '\0' || equiv[i] == '\0') 1054 return false; 1055 if (orig[i] != equiv[i]) { 1056 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W') 1057 continue; 1058 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1') 1059 continue; 1060 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6') 1061 continue; 1062 return false; 1063 } 1064 } 1065 } 1066 1067 // Determine whether this instruction is a 64-bit instruction. 1068 static bool is64Bit(const char *name) { 1069 for (int i = 0;; ++i) { 1070 if (name[i] == '\0') 1071 return false; 1072 if (name[i] == '6' && name[i + 1] == '4') 1073 return true; 1074 } 1075 } 1076 1077 // Determine the ID of an instruction, consuming the ModR/M byte as appropriate 1078 // for extended and escape opcodes, and using a supplied attribute mask. 1079 static int getInstructionIDWithAttrMask(uint16_t *instructionID, 1080 struct InternalInstruction *insn, 1081 uint16_t attrMask) { 1082 auto insnCtx = InstructionContext(x86DisassemblerContexts[attrMask]); 1083 const ContextDecision *decision; 1084 switch (insn->opcodeType) { 1085 case ONEBYTE: 1086 decision = &ONEBYTE_SYM; 1087 break; 1088 case TWOBYTE: 1089 decision = &TWOBYTE_SYM; 1090 break; 1091 case THREEBYTE_38: 1092 decision = &THREEBYTE38_SYM; 1093 break; 1094 case THREEBYTE_3A: 1095 decision = &THREEBYTE3A_SYM; 1096 break; 1097 case XOP8_MAP: 1098 decision = &XOP8_MAP_SYM; 1099 break; 1100 case XOP9_MAP: 1101 decision = &XOP9_MAP_SYM; 1102 break; 1103 case XOPA_MAP: 1104 decision = &XOPA_MAP_SYM; 1105 break; 1106 case THREEDNOW_MAP: 1107 decision = &THREEDNOW_MAP_SYM; 1108 break; 1109 case MAP4: 1110 decision = &MAP4_SYM; 1111 break; 1112 case MAP5: 1113 decision = &MAP5_SYM; 1114 break; 1115 case MAP6: 1116 decision = &MAP6_SYM; 1117 break; 1118 case MAP7: 1119 decision = &MAP7_SYM; 1120 break; 1121 } 1122 1123 if (decision->opcodeDecisions[insnCtx] 1124 .modRMDecisions[insn->opcode] 1125 .modrm_type != MODRM_ONEENTRY) { 1126 if (readModRM(insn)) 1127 return -1; 1128 *instructionID = 1129 decode(insn->opcodeType, insnCtx, insn->opcode, insn->modRM); 1130 } else { 1131 *instructionID = decode(insn->opcodeType, insnCtx, insn->opcode, 0); 1132 } 1133 1134 return 0; 1135 } 1136 1137 static bool isNF(InternalInstruction *insn) { 1138 if (!nfFromEVEX4of4(insn->vectorExtensionPrefix[3])) 1139 return false; 1140 if (insn->opcodeType == MAP4) 1141 return true; 1142 // Below NF instructions are not in map4. 1143 if (insn->opcodeType == THREEBYTE_38 && 1144 ppFromEVEX3of4(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) { 1145 switch (insn->opcode) { 1146 case 0xf2: // ANDN 1147 case 0xf3: // BLSI, BLSR, BLSMSK 1148 case 0xf5: // BZHI 1149 case 0xf7: // BEXTR 1150 return true; 1151 default: 1152 break; 1153 } 1154 } 1155 return false; 1156 } 1157 1158 // Determine the ID of an instruction, consuming the ModR/M byte as appropriate 1159 // for extended and escape opcodes. Determines the attributes and context for 1160 // the instruction before doing so. 1161 static int getInstructionID(struct InternalInstruction *insn, 1162 const MCInstrInfo *mii) { 1163 uint16_t attrMask; 1164 uint16_t instructionID; 1165 1166 LLVM_DEBUG(dbgs() << "getID()"); 1167 1168 attrMask = ATTR_NONE; 1169 1170 if (insn->mode == MODE_64BIT) 1171 attrMask |= ATTR_64BIT; 1172 1173 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) { 1174 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX; 1175 1176 if (insn->vectorExtensionType == TYPE_EVEX) { 1177 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) { 1178 case VEX_PREFIX_66: 1179 attrMask |= ATTR_OPSIZE; 1180 break; 1181 case VEX_PREFIX_F3: 1182 attrMask |= ATTR_XS; 1183 break; 1184 case VEX_PREFIX_F2: 1185 attrMask |= ATTR_XD; 1186 break; 1187 } 1188 1189 if (zFromEVEX4of4(insn->vectorExtensionPrefix[3])) 1190 attrMask |= ATTR_EVEXKZ; 1191 if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) 1192 attrMask |= ATTR_EVEXB; 1193 if (isNF(insn)) // NF bit is the MSB of aaa. 1194 attrMask |= ATTR_EVEXNF; 1195 else if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])) 1196 attrMask |= ATTR_EVEXK; 1197 if (lFromEVEX4of4(insn->vectorExtensionPrefix[3])) 1198 attrMask |= ATTR_VEXL; 1199 if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3])) 1200 attrMask |= ATTR_EVEXL2; 1201 } else if (insn->vectorExtensionType == TYPE_VEX_3B) { 1202 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) { 1203 case VEX_PREFIX_66: 1204 attrMask |= ATTR_OPSIZE; 1205 break; 1206 case VEX_PREFIX_F3: 1207 attrMask |= ATTR_XS; 1208 break; 1209 case VEX_PREFIX_F2: 1210 attrMask |= ATTR_XD; 1211 break; 1212 } 1213 1214 if (lFromVEX3of3(insn->vectorExtensionPrefix[2])) 1215 attrMask |= ATTR_VEXL; 1216 } else if (insn->vectorExtensionType == TYPE_VEX_2B) { 1217 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { 1218 case VEX_PREFIX_66: 1219 attrMask |= ATTR_OPSIZE; 1220 if (insn->hasAdSize) 1221 attrMask |= ATTR_ADSIZE; 1222 break; 1223 case VEX_PREFIX_F3: 1224 attrMask |= ATTR_XS; 1225 break; 1226 case VEX_PREFIX_F2: 1227 attrMask |= ATTR_XD; 1228 break; 1229 } 1230 1231 if (lFromVEX2of2(insn->vectorExtensionPrefix[1])) 1232 attrMask |= ATTR_VEXL; 1233 } else if (insn->vectorExtensionType == TYPE_XOP) { 1234 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { 1235 case VEX_PREFIX_66: 1236 attrMask |= ATTR_OPSIZE; 1237 break; 1238 case VEX_PREFIX_F3: 1239 attrMask |= ATTR_XS; 1240 break; 1241 case VEX_PREFIX_F2: 1242 attrMask |= ATTR_XD; 1243 break; 1244 } 1245 1246 if (lFromXOP3of3(insn->vectorExtensionPrefix[2])) 1247 attrMask |= ATTR_VEXL; 1248 } else { 1249 return -1; 1250 } 1251 } else if (!insn->mandatoryPrefix) { 1252 // If we don't have mandatory prefix we should use legacy prefixes here 1253 if (insn->hasOpSize && (insn->mode != MODE_16BIT)) 1254 attrMask |= ATTR_OPSIZE; 1255 if (insn->hasAdSize) 1256 attrMask |= ATTR_ADSIZE; 1257 if (insn->opcodeType == ONEBYTE) { 1258 if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90)) 1259 // Special support for PAUSE 1260 attrMask |= ATTR_XS; 1261 } else { 1262 if (insn->repeatPrefix == 0xf2) 1263 attrMask |= ATTR_XD; 1264 else if (insn->repeatPrefix == 0xf3) 1265 attrMask |= ATTR_XS; 1266 } 1267 } else { 1268 switch (insn->mandatoryPrefix) { 1269 case 0xf2: 1270 attrMask |= ATTR_XD; 1271 break; 1272 case 0xf3: 1273 attrMask |= ATTR_XS; 1274 break; 1275 case 0x66: 1276 if (insn->mode != MODE_16BIT) 1277 attrMask |= ATTR_OPSIZE; 1278 if (insn->hasAdSize) 1279 attrMask |= ATTR_ADSIZE; 1280 break; 1281 case 0x67: 1282 attrMask |= ATTR_ADSIZE; 1283 break; 1284 } 1285 } 1286 1287 if (insn->rexPrefix & 0x08) { 1288 attrMask |= ATTR_REXW; 1289 attrMask &= ~ATTR_ADSIZE; 1290 } 1291 1292 // Absolute jump and pushp/popp need special handling 1293 if (insn->rex2ExtensionPrefix[0] == 0xd5 && insn->opcodeType == ONEBYTE && 1294 (insn->opcode == 0xA1 || (insn->opcode & 0xf0) == 0x50)) 1295 attrMask |= ATTR_REX2; 1296 1297 if (insn->mode == MODE_16BIT) { 1298 // JCXZ/JECXZ need special handling for 16-bit mode because the meaning 1299 // of the AdSize prefix is inverted w.r.t. 32-bit mode. 1300 if (insn->opcodeType == ONEBYTE && insn->opcode == 0xE3) 1301 attrMask ^= ATTR_ADSIZE; 1302 // If we're in 16-bit mode and this is one of the relative jumps and opsize 1303 // prefix isn't present, we need to force the opsize attribute since the 1304 // prefix is inverted relative to 32-bit mode. 1305 if (!insn->hasOpSize && insn->opcodeType == ONEBYTE && 1306 (insn->opcode == 0xE8 || insn->opcode == 0xE9)) 1307 attrMask |= ATTR_OPSIZE; 1308 1309 if (!insn->hasOpSize && insn->opcodeType == TWOBYTE && 1310 insn->opcode >= 0x80 && insn->opcode <= 0x8F) 1311 attrMask |= ATTR_OPSIZE; 1312 } 1313 1314 1315 if (getInstructionIDWithAttrMask(&instructionID, insn, attrMask)) 1316 return -1; 1317 1318 // The following clauses compensate for limitations of the tables. 1319 1320 if (insn->mode != MODE_64BIT && 1321 insn->vectorExtensionType != TYPE_NO_VEX_XOP) { 1322 // The tables can't distinquish between cases where the W-bit is used to 1323 // select register size and cases where its a required part of the opcode. 1324 if ((insn->vectorExtensionType == TYPE_EVEX && 1325 wFromEVEX3of4(insn->vectorExtensionPrefix[2])) || 1326 (insn->vectorExtensionType == TYPE_VEX_3B && 1327 wFromVEX3of3(insn->vectorExtensionPrefix[2])) || 1328 (insn->vectorExtensionType == TYPE_XOP && 1329 wFromXOP3of3(insn->vectorExtensionPrefix[2]))) { 1330 1331 uint16_t instructionIDWithREXW; 1332 if (getInstructionIDWithAttrMask(&instructionIDWithREXW, insn, 1333 attrMask | ATTR_REXW)) { 1334 insn->instructionID = instructionID; 1335 insn->spec = &INSTRUCTIONS_SYM[instructionID]; 1336 return 0; 1337 } 1338 1339 auto SpecName = mii->getName(instructionIDWithREXW); 1340 // If not a 64-bit instruction. Switch the opcode. 1341 if (!is64Bit(SpecName.data())) { 1342 insn->instructionID = instructionIDWithREXW; 1343 insn->spec = &INSTRUCTIONS_SYM[instructionIDWithREXW]; 1344 return 0; 1345 } 1346 } 1347 } 1348 1349 // Absolute moves, umonitor, and movdir64b need special handling. 1350 // -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are 1351 // inverted w.r.t. 1352 // -For 32-bit mode we need to ensure the ADSIZE prefix is observed in 1353 // any position. 1354 if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) || 1355 (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) || 1356 (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8) || 1357 (insn->opcodeType == MAP4 && insn->opcode == 0xF8)) { 1358 // Make sure we observed the prefixes in any position. 1359 if (insn->hasAdSize) 1360 attrMask |= ATTR_ADSIZE; 1361 if (insn->hasOpSize) 1362 attrMask |= ATTR_OPSIZE; 1363 1364 // In 16-bit, invert the attributes. 1365 if (insn->mode == MODE_16BIT) { 1366 attrMask ^= ATTR_ADSIZE; 1367 1368 // The OpSize attribute is only valid with the absolute moves. 1369 if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) 1370 attrMask ^= ATTR_OPSIZE; 1371 } 1372 1373 if (getInstructionIDWithAttrMask(&instructionID, insn, attrMask)) 1374 return -1; 1375 1376 insn->instructionID = instructionID; 1377 insn->spec = &INSTRUCTIONS_SYM[instructionID]; 1378 return 0; 1379 } 1380 1381 if ((insn->mode == MODE_16BIT || insn->hasOpSize) && 1382 !(attrMask & ATTR_OPSIZE)) { 1383 // The instruction tables make no distinction between instructions that 1384 // allow OpSize anywhere (i.e., 16-bit operations) and that need it in a 1385 // particular spot (i.e., many MMX operations). In general we're 1386 // conservative, but in the specific case where OpSize is present but not in 1387 // the right place we check if there's a 16-bit operation. 1388 const struct InstructionSpecifier *spec; 1389 uint16_t instructionIDWithOpsize; 1390 llvm::StringRef specName, specWithOpSizeName; 1391 1392 spec = &INSTRUCTIONS_SYM[instructionID]; 1393 1394 if (getInstructionIDWithAttrMask(&instructionIDWithOpsize, insn, 1395 attrMask | ATTR_OPSIZE)) { 1396 // ModRM required with OpSize but not present. Give up and return the 1397 // version without OpSize set. 1398 insn->instructionID = instructionID; 1399 insn->spec = spec; 1400 return 0; 1401 } 1402 1403 specName = mii->getName(instructionID); 1404 specWithOpSizeName = mii->getName(instructionIDWithOpsize); 1405 1406 if (is16BitEquivalent(specName.data(), specWithOpSizeName.data()) && 1407 (insn->mode == MODE_16BIT) ^ insn->hasOpSize) { 1408 insn->instructionID = instructionIDWithOpsize; 1409 insn->spec = &INSTRUCTIONS_SYM[instructionIDWithOpsize]; 1410 } else { 1411 insn->instructionID = instructionID; 1412 insn->spec = spec; 1413 } 1414 return 0; 1415 } 1416 1417 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 && 1418 insn->rexPrefix & 0x01) { 1419 // NOOP shouldn't decode as NOOP if REX.b is set. Instead it should decode 1420 // as XCHG %r8, %eax. 1421 const struct InstructionSpecifier *spec; 1422 uint16_t instructionIDWithNewOpcode; 1423 const struct InstructionSpecifier *specWithNewOpcode; 1424 1425 spec = &INSTRUCTIONS_SYM[instructionID]; 1426 1427 // Borrow opcode from one of the other XCHGar opcodes 1428 insn->opcode = 0x91; 1429 1430 if (getInstructionIDWithAttrMask(&instructionIDWithNewOpcode, insn, 1431 attrMask)) { 1432 insn->opcode = 0x90; 1433 1434 insn->instructionID = instructionID; 1435 insn->spec = spec; 1436 return 0; 1437 } 1438 1439 specWithNewOpcode = &INSTRUCTIONS_SYM[instructionIDWithNewOpcode]; 1440 1441 // Change back 1442 insn->opcode = 0x90; 1443 1444 insn->instructionID = instructionIDWithNewOpcode; 1445 insn->spec = specWithNewOpcode; 1446 1447 return 0; 1448 } 1449 1450 insn->instructionID = instructionID; 1451 insn->spec = &INSTRUCTIONS_SYM[insn->instructionID]; 1452 1453 return 0; 1454 } 1455 1456 // Read an operand from the opcode field of an instruction and interprets it 1457 // appropriately given the operand width. Handles AddRegFrm instructions. 1458 // 1459 // @param insn - the instruction whose opcode field is to be read. 1460 // @param size - The width (in bytes) of the register being specified. 1461 // 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means 1462 // RAX. 1463 // @return - 0 on success; nonzero otherwise. 1464 static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size) { 1465 LLVM_DEBUG(dbgs() << "readOpcodeRegister()"); 1466 1467 if (size == 0) 1468 size = insn->registerSize; 1469 1470 auto setOpcodeRegister = [&](unsigned base) { 1471 insn->opcodeRegister = 1472 (Reg)(base + ((bFromREX(insn->rexPrefix) << 3) | 1473 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4) | 1474 (insn->opcode & 7))); 1475 }; 1476 1477 switch (size) { 1478 case 1: 1479 setOpcodeRegister(MODRM_REG_AL); 1480 if (insn->rexPrefix && insn->opcodeRegister >= MODRM_REG_AL + 0x4 && 1481 insn->opcodeRegister < MODRM_REG_AL + 0x8) { 1482 insn->opcodeRegister = 1483 (Reg)(MODRM_REG_SPL + (insn->opcodeRegister - MODRM_REG_AL - 4)); 1484 } 1485 1486 break; 1487 case 2: 1488 setOpcodeRegister(MODRM_REG_AX); 1489 break; 1490 case 4: 1491 setOpcodeRegister(MODRM_REG_EAX); 1492 break; 1493 case 8: 1494 setOpcodeRegister(MODRM_REG_RAX); 1495 break; 1496 } 1497 1498 return 0; 1499 } 1500 1501 // Consume an immediate operand from an instruction, given the desired operand 1502 // size. 1503 // 1504 // @param insn - The instruction whose operand is to be read. 1505 // @param size - The width (in bytes) of the operand. 1506 // @return - 0 if the immediate was successfully consumed; nonzero 1507 // otherwise. 1508 static int readImmediate(struct InternalInstruction *insn, uint8_t size) { 1509 uint8_t imm8; 1510 uint16_t imm16; 1511 uint32_t imm32; 1512 uint64_t imm64; 1513 1514 LLVM_DEBUG(dbgs() << "readImmediate()"); 1515 1516 assert(insn->numImmediatesConsumed < 2 && "Already consumed two immediates"); 1517 1518 insn->immediateSize = size; 1519 insn->immediateOffset = insn->readerCursor - insn->startLocation; 1520 1521 switch (size) { 1522 case 1: 1523 if (consume(insn, imm8)) 1524 return -1; 1525 insn->immediates[insn->numImmediatesConsumed] = imm8; 1526 break; 1527 case 2: 1528 if (consume(insn, imm16)) 1529 return -1; 1530 insn->immediates[insn->numImmediatesConsumed] = imm16; 1531 break; 1532 case 4: 1533 if (consume(insn, imm32)) 1534 return -1; 1535 insn->immediates[insn->numImmediatesConsumed] = imm32; 1536 break; 1537 case 8: 1538 if (consume(insn, imm64)) 1539 return -1; 1540 insn->immediates[insn->numImmediatesConsumed] = imm64; 1541 break; 1542 default: 1543 llvm_unreachable("invalid size"); 1544 } 1545 1546 insn->numImmediatesConsumed++; 1547 1548 return 0; 1549 } 1550 1551 // Consume vvvv from an instruction if it has a VEX prefix. 1552 static int readVVVV(struct InternalInstruction *insn) { 1553 LLVM_DEBUG(dbgs() << "readVVVV()"); 1554 1555 int vvvv; 1556 if (insn->vectorExtensionType == TYPE_EVEX) 1557 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | 1558 vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2])); 1559 else if (insn->vectorExtensionType == TYPE_VEX_3B) 1560 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); 1561 else if (insn->vectorExtensionType == TYPE_VEX_2B) 1562 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]); 1563 else if (insn->vectorExtensionType == TYPE_XOP) 1564 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]); 1565 else 1566 return -1; 1567 1568 if (insn->mode != MODE_64BIT) 1569 vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later. 1570 1571 insn->vvvv = static_cast<Reg>(vvvv); 1572 return 0; 1573 } 1574 1575 // Read an mask register from the opcode field of an instruction. 1576 // 1577 // @param insn - The instruction whose opcode field is to be read. 1578 // @return - 0 on success; nonzero otherwise. 1579 static int readMaskRegister(struct InternalInstruction *insn) { 1580 LLVM_DEBUG(dbgs() << "readMaskRegister()"); 1581 1582 if (insn->vectorExtensionType != TYPE_EVEX) 1583 return -1; 1584 1585 insn->writemask = 1586 static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])); 1587 return 0; 1588 } 1589 1590 // Consults the specifier for an instruction and consumes all 1591 // operands for that instruction, interpreting them as it goes. 1592 static int readOperands(struct InternalInstruction *insn) { 1593 int hasVVVV, needVVVV; 1594 int sawRegImm = 0; 1595 1596 LLVM_DEBUG(dbgs() << "readOperands()"); 1597 1598 // If non-zero vvvv specified, make sure one of the operands uses it. 1599 hasVVVV = !readVVVV(insn); 1600 needVVVV = hasVVVV && (insn->vvvv != 0); 1601 1602 for (const auto &Op : x86OperandSets[insn->spec->operands]) { 1603 switch (Op.encoding) { 1604 case ENCODING_NONE: 1605 case ENCODING_SI: 1606 case ENCODING_DI: 1607 break; 1608 CASE_ENCODING_VSIB: 1609 // VSIB can use the V2 bit so check only the other bits. 1610 if (needVVVV) 1611 needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0); 1612 if (readModRM(insn)) 1613 return -1; 1614 1615 // Reject if SIB wasn't used. 1616 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64) 1617 return -1; 1618 1619 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4. 1620 if (insn->sibIndex == SIB_INDEX_NONE) 1621 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + 4); 1622 1623 // If EVEX.v2 is set this is one of the 16-31 registers. 1624 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT && 1625 v2FromEVEX4of4(insn->vectorExtensionPrefix[3])) 1626 insn->sibIndex = (SIBIndex)(insn->sibIndex + 16); 1627 1628 // Adjust the index register to the correct size. 1629 switch ((OperandType)Op.type) { 1630 default: 1631 debug("Unhandled VSIB index type"); 1632 return -1; 1633 case TYPE_MVSIBX: 1634 insn->sibIndex = 1635 (SIBIndex)(SIB_INDEX_XMM0 + (insn->sibIndex - insn->sibIndexBase)); 1636 break; 1637 case TYPE_MVSIBY: 1638 insn->sibIndex = 1639 (SIBIndex)(SIB_INDEX_YMM0 + (insn->sibIndex - insn->sibIndexBase)); 1640 break; 1641 case TYPE_MVSIBZ: 1642 insn->sibIndex = 1643 (SIBIndex)(SIB_INDEX_ZMM0 + (insn->sibIndex - insn->sibIndexBase)); 1644 break; 1645 } 1646 1647 // Apply the AVX512 compressed displacement scaling factor. 1648 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) 1649 insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB); 1650 break; 1651 case ENCODING_SIB: 1652 // Reject if SIB wasn't used. 1653 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64) 1654 return -1; 1655 if (readModRM(insn)) 1656 return -1; 1657 if (fixupReg(insn, &Op)) 1658 return -1; 1659 break; 1660 case ENCODING_REG: 1661 CASE_ENCODING_RM: 1662 if (readModRM(insn)) 1663 return -1; 1664 if (fixupReg(insn, &Op)) 1665 return -1; 1666 // Apply the AVX512 compressed displacement scaling factor. 1667 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) 1668 insn->displacement *= 1 << (Op.encoding - ENCODING_RM); 1669 break; 1670 case ENCODING_IB: 1671 if (sawRegImm) { 1672 // Saw a register immediate so don't read again and instead split the 1673 // previous immediate. FIXME: This is a hack. 1674 insn->immediates[insn->numImmediatesConsumed] = 1675 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf; 1676 ++insn->numImmediatesConsumed; 1677 break; 1678 } 1679 if (readImmediate(insn, 1)) 1680 return -1; 1681 if (Op.type == TYPE_XMM || Op.type == TYPE_YMM) 1682 sawRegImm = 1; 1683 break; 1684 case ENCODING_IW: 1685 if (readImmediate(insn, 2)) 1686 return -1; 1687 break; 1688 case ENCODING_ID: 1689 if (readImmediate(insn, 4)) 1690 return -1; 1691 break; 1692 case ENCODING_IO: 1693 if (readImmediate(insn, 8)) 1694 return -1; 1695 break; 1696 case ENCODING_Iv: 1697 if (readImmediate(insn, insn->immediateSize)) 1698 return -1; 1699 break; 1700 case ENCODING_Ia: 1701 if (readImmediate(insn, insn->addressSize)) 1702 return -1; 1703 break; 1704 case ENCODING_IRC: 1705 insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) | 1706 lFromEVEX4of4(insn->vectorExtensionPrefix[3]); 1707 break; 1708 case ENCODING_RB: 1709 if (readOpcodeRegister(insn, 1)) 1710 return -1; 1711 break; 1712 case ENCODING_RW: 1713 if (readOpcodeRegister(insn, 2)) 1714 return -1; 1715 break; 1716 case ENCODING_RD: 1717 if (readOpcodeRegister(insn, 4)) 1718 return -1; 1719 break; 1720 case ENCODING_RO: 1721 if (readOpcodeRegister(insn, 8)) 1722 return -1; 1723 break; 1724 case ENCODING_Rv: 1725 if (readOpcodeRegister(insn, 0)) 1726 return -1; 1727 break; 1728 case ENCODING_CC: 1729 insn->immediates[1] = insn->opcode & 0xf; 1730 break; 1731 case ENCODING_FP: 1732 break; 1733 case ENCODING_VVVV: 1734 needVVVV = 0; // Mark that we have found a VVVV operand. 1735 if (!hasVVVV) 1736 return -1; 1737 if (insn->mode != MODE_64BIT) 1738 insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7); 1739 if (fixupReg(insn, &Op)) 1740 return -1; 1741 break; 1742 case ENCODING_WRITEMASK: 1743 if (readMaskRegister(insn)) 1744 return -1; 1745 break; 1746 case ENCODING_DUP: 1747 break; 1748 default: 1749 LLVM_DEBUG(dbgs() << "Encountered an operand with an unknown encoding."); 1750 return -1; 1751 } 1752 } 1753 1754 // If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail 1755 if (needVVVV) 1756 return -1; 1757 1758 return 0; 1759 } 1760 1761 namespace llvm { 1762 1763 // Fill-ins to make the compiler happy. These constants are never actually 1764 // assigned; they are just filler to make an automatically-generated switch 1765 // statement work. 1766 namespace X86 { 1767 enum { 1768 BX_SI = 500, 1769 BX_DI = 501, 1770 BP_SI = 502, 1771 BP_DI = 503, 1772 sib = 504, 1773 sib64 = 505 1774 }; 1775 } // namespace X86 1776 1777 } // namespace llvm 1778 1779 static bool translateInstruction(MCInst &target, 1780 InternalInstruction &source, 1781 const MCDisassembler *Dis); 1782 1783 namespace { 1784 1785 /// Generic disassembler for all X86 platforms. All each platform class should 1786 /// have to do is subclass the constructor, and provide a different 1787 /// disassemblerMode value. 1788 class X86GenericDisassembler : public MCDisassembler { 1789 std::unique_ptr<const MCInstrInfo> MII; 1790 public: 1791 X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 1792 std::unique_ptr<const MCInstrInfo> MII); 1793 public: 1794 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 1795 ArrayRef<uint8_t> Bytes, uint64_t Address, 1796 raw_ostream &cStream) const override; 1797 1798 private: 1799 DisassemblerMode fMode; 1800 }; 1801 1802 } // namespace 1803 1804 X86GenericDisassembler::X86GenericDisassembler( 1805 const MCSubtargetInfo &STI, 1806 MCContext &Ctx, 1807 std::unique_ptr<const MCInstrInfo> MII) 1808 : MCDisassembler(STI, Ctx), MII(std::move(MII)) { 1809 const FeatureBitset &FB = STI.getFeatureBits(); 1810 if (FB[X86::Is16Bit]) { 1811 fMode = MODE_16BIT; 1812 return; 1813 } else if (FB[X86::Is32Bit]) { 1814 fMode = MODE_32BIT; 1815 return; 1816 } else if (FB[X86::Is64Bit]) { 1817 fMode = MODE_64BIT; 1818 return; 1819 } 1820 1821 llvm_unreachable("Invalid CPU mode"); 1822 } 1823 1824 MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction( 1825 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, 1826 raw_ostream &CStream) const { 1827 CommentStream = &CStream; 1828 1829 InternalInstruction Insn; 1830 memset(&Insn, 0, sizeof(InternalInstruction)); 1831 Insn.bytes = Bytes; 1832 Insn.startLocation = Address; 1833 Insn.readerCursor = Address; 1834 Insn.mode = fMode; 1835 1836 if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) || 1837 getInstructionID(&Insn, MII.get()) || Insn.instructionID == 0 || 1838 readOperands(&Insn)) { 1839 Size = Insn.readerCursor - Address; 1840 return Fail; 1841 } 1842 1843 Insn.operands = x86OperandSets[Insn.spec->operands]; 1844 Insn.length = Insn.readerCursor - Insn.startLocation; 1845 Size = Insn.length; 1846 if (Size > 15) 1847 LLVM_DEBUG(dbgs() << "Instruction exceeds 15-byte limit"); 1848 1849 bool Ret = translateInstruction(Instr, Insn, this); 1850 if (!Ret) { 1851 unsigned Flags = X86::IP_NO_PREFIX; 1852 if (Insn.hasAdSize) 1853 Flags |= X86::IP_HAS_AD_SIZE; 1854 if (!Insn.mandatoryPrefix) { 1855 if (Insn.hasOpSize) 1856 Flags |= X86::IP_HAS_OP_SIZE; 1857 if (Insn.repeatPrefix == 0xf2) 1858 Flags |= X86::IP_HAS_REPEAT_NE; 1859 else if (Insn.repeatPrefix == 0xf3 && 1860 // It should not be 'pause' f3 90 1861 Insn.opcode != 0x90) 1862 Flags |= X86::IP_HAS_REPEAT; 1863 if (Insn.hasLockPrefix) 1864 Flags |= X86::IP_HAS_LOCK; 1865 } 1866 Instr.setFlags(Flags); 1867 } 1868 return (!Ret) ? Success : Fail; 1869 } 1870 1871 // 1872 // Private code that translates from struct InternalInstructions to MCInsts. 1873 // 1874 1875 /// translateRegister - Translates an internal register to the appropriate LLVM 1876 /// register, and appends it as an operand to an MCInst. 1877 /// 1878 /// @param mcInst - The MCInst to append to. 1879 /// @param reg - The Reg to append. 1880 static void translateRegister(MCInst &mcInst, Reg reg) { 1881 #define ENTRY(x) X86::x, 1882 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS}; 1883 #undef ENTRY 1884 1885 MCPhysReg llvmRegnum = llvmRegnums[reg]; 1886 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); 1887 } 1888 1889 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { 1890 0, // SEG_OVERRIDE_NONE 1891 X86::CS, 1892 X86::SS, 1893 X86::DS, 1894 X86::ES, 1895 X86::FS, 1896 X86::GS 1897 }; 1898 1899 /// translateSrcIndex - Appends a source index operand to an MCInst. 1900 /// 1901 /// @param mcInst - The MCInst to append to. 1902 /// @param insn - The internal instruction. 1903 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { 1904 unsigned baseRegNo; 1905 1906 if (insn.mode == MODE_64BIT) 1907 baseRegNo = insn.hasAdSize ? X86::ESI : X86::RSI; 1908 else if (insn.mode == MODE_32BIT) 1909 baseRegNo = insn.hasAdSize ? X86::SI : X86::ESI; 1910 else { 1911 assert(insn.mode == MODE_16BIT); 1912 baseRegNo = insn.hasAdSize ? X86::ESI : X86::SI; 1913 } 1914 MCOperand baseReg = MCOperand::createReg(baseRegNo); 1915 mcInst.addOperand(baseReg); 1916 1917 MCOperand segmentReg; 1918 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 1919 mcInst.addOperand(segmentReg); 1920 return false; 1921 } 1922 1923 /// translateDstIndex - Appends a destination index operand to an MCInst. 1924 /// 1925 /// @param mcInst - The MCInst to append to. 1926 /// @param insn - The internal instruction. 1927 1928 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) { 1929 unsigned baseRegNo; 1930 1931 if (insn.mode == MODE_64BIT) 1932 baseRegNo = insn.hasAdSize ? X86::EDI : X86::RDI; 1933 else if (insn.mode == MODE_32BIT) 1934 baseRegNo = insn.hasAdSize ? X86::DI : X86::EDI; 1935 else { 1936 assert(insn.mode == MODE_16BIT); 1937 baseRegNo = insn.hasAdSize ? X86::EDI : X86::DI; 1938 } 1939 MCOperand baseReg = MCOperand::createReg(baseRegNo); 1940 mcInst.addOperand(baseReg); 1941 return false; 1942 } 1943 1944 /// translateImmediate - Appends an immediate operand to an MCInst. 1945 /// 1946 /// @param mcInst - The MCInst to append to. 1947 /// @param immediate - The immediate value to append. 1948 /// @param operand - The operand, as stored in the descriptor table. 1949 /// @param insn - The internal instruction. 1950 static void translateImmediate(MCInst &mcInst, uint64_t immediate, 1951 const OperandSpecifier &operand, 1952 InternalInstruction &insn, 1953 const MCDisassembler *Dis) { 1954 // Sign-extend the immediate if necessary. 1955 1956 OperandType type = (OperandType)operand.type; 1957 1958 bool isBranch = false; 1959 uint64_t pcrel = 0; 1960 if (type == TYPE_REL) { 1961 isBranch = true; 1962 pcrel = insn.startLocation + insn.length; 1963 switch (operand.encoding) { 1964 default: 1965 break; 1966 case ENCODING_Iv: 1967 switch (insn.displacementSize) { 1968 default: 1969 break; 1970 case 1: 1971 if(immediate & 0x80) 1972 immediate |= ~(0xffull); 1973 break; 1974 case 2: 1975 if(immediate & 0x8000) 1976 immediate |= ~(0xffffull); 1977 break; 1978 case 4: 1979 if(immediate & 0x80000000) 1980 immediate |= ~(0xffffffffull); 1981 break; 1982 case 8: 1983 break; 1984 } 1985 break; 1986 case ENCODING_IB: 1987 if(immediate & 0x80) 1988 immediate |= ~(0xffull); 1989 break; 1990 case ENCODING_IW: 1991 if(immediate & 0x8000) 1992 immediate |= ~(0xffffull); 1993 break; 1994 case ENCODING_ID: 1995 if(immediate & 0x80000000) 1996 immediate |= ~(0xffffffffull); 1997 break; 1998 } 1999 } 2000 // By default sign-extend all X86 immediates based on their encoding. 2001 else if (type == TYPE_IMM) { 2002 switch (operand.encoding) { 2003 default: 2004 break; 2005 case ENCODING_IB: 2006 if(immediate & 0x80) 2007 immediate |= ~(0xffull); 2008 break; 2009 case ENCODING_IW: 2010 if(immediate & 0x8000) 2011 immediate |= ~(0xffffull); 2012 break; 2013 case ENCODING_ID: 2014 if(immediate & 0x80000000) 2015 immediate |= ~(0xffffffffull); 2016 break; 2017 case ENCODING_IO: 2018 break; 2019 } 2020 } 2021 2022 switch (type) { 2023 case TYPE_XMM: 2024 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); 2025 return; 2026 case TYPE_YMM: 2027 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); 2028 return; 2029 case TYPE_ZMM: 2030 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); 2031 return; 2032 default: 2033 // operand is 64 bits wide. Do nothing. 2034 break; 2035 } 2036 2037 if (!Dis->tryAddingSymbolicOperand( 2038 mcInst, immediate + pcrel, insn.startLocation, isBranch, 2039 insn.immediateOffset, insn.immediateSize, insn.length)) 2040 mcInst.addOperand(MCOperand::createImm(immediate)); 2041 2042 if (type == TYPE_MOFFS) { 2043 MCOperand segmentReg; 2044 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 2045 mcInst.addOperand(segmentReg); 2046 } 2047 } 2048 2049 /// translateRMRegister - Translates a register stored in the R/M field of the 2050 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. 2051 /// @param mcInst - The MCInst to append to. 2052 /// @param insn - The internal instruction to extract the R/M field 2053 /// from. 2054 /// @return - 0 on success; -1 otherwise 2055 static bool translateRMRegister(MCInst &mcInst, 2056 InternalInstruction &insn) { 2057 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 2058 debug("A R/M register operand may not have a SIB byte"); 2059 return true; 2060 } 2061 2062 switch (insn.eaBase) { 2063 default: 2064 debug("Unexpected EA base register"); 2065 return true; 2066 case EA_BASE_NONE: 2067 debug("EA_BASE_NONE for ModR/M base"); 2068 return true; 2069 #define ENTRY(x) case EA_BASE_##x: 2070 ALL_EA_BASES 2071 #undef ENTRY 2072 debug("A R/M register operand may not have a base; " 2073 "the operand must be a register."); 2074 return true; 2075 #define ENTRY(x) \ 2076 case EA_REG_##x: \ 2077 mcInst.addOperand(MCOperand::createReg(X86::x)); break; 2078 ALL_REGS 2079 #undef ENTRY 2080 } 2081 2082 return false; 2083 } 2084 2085 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M 2086 /// fields of an internal instruction (and possibly its SIB byte) to a memory 2087 /// operand in LLVM's format, and appends it to an MCInst. 2088 /// 2089 /// @param mcInst - The MCInst to append to. 2090 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 2091 /// from. 2092 /// @param ForceSIB - The instruction must use SIB. 2093 /// @return - 0 on success; nonzero otherwise 2094 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, 2095 const MCDisassembler *Dis, 2096 bool ForceSIB = false) { 2097 // Addresses in an MCInst are represented as five operands: 2098 // 1. basereg (register) The R/M base, or (if there is a SIB) the 2099 // SIB base 2100 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified 2101 // scale amount 2102 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) 2103 // the index (which is multiplied by the 2104 // scale amount) 2105 // 4. displacement (immediate) 0, or the displacement if there is one 2106 // 5. segmentreg (register) x86_registerNONE for now, but could be set 2107 // if we have segment overrides 2108 2109 MCOperand baseReg; 2110 MCOperand scaleAmount; 2111 MCOperand indexReg; 2112 MCOperand displacement; 2113 MCOperand segmentReg; 2114 uint64_t pcrel = 0; 2115 2116 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 2117 if (insn.sibBase != SIB_BASE_NONE) { 2118 switch (insn.sibBase) { 2119 default: 2120 debug("Unexpected sibBase"); 2121 return true; 2122 #define ENTRY(x) \ 2123 case SIB_BASE_##x: \ 2124 baseReg = MCOperand::createReg(X86::x); break; 2125 ALL_SIB_BASES 2126 #undef ENTRY 2127 } 2128 } else { 2129 baseReg = MCOperand::createReg(X86::NoRegister); 2130 } 2131 2132 if (insn.sibIndex != SIB_INDEX_NONE) { 2133 switch (insn.sibIndex) { 2134 default: 2135 debug("Unexpected sibIndex"); 2136 return true; 2137 #define ENTRY(x) \ 2138 case SIB_INDEX_##x: \ 2139 indexReg = MCOperand::createReg(X86::x); break; 2140 EA_BASES_32BIT 2141 EA_BASES_64BIT 2142 REGS_XMM 2143 REGS_YMM 2144 REGS_ZMM 2145 #undef ENTRY 2146 } 2147 } else { 2148 // Use EIZ/RIZ for a few ambiguous cases where the SIB byte is present, 2149 // but no index is used and modrm alone should have been enough. 2150 // -No base register in 32-bit mode. In 64-bit mode this is used to 2151 // avoid rip-relative addressing. 2152 // -Any base register used other than ESP/RSP/R12D/R12. Using these as a 2153 // base always requires a SIB byte. 2154 // -A scale other than 1 is used. 2155 if (!ForceSIB && 2156 (insn.sibScale != 1 || 2157 (insn.sibBase == SIB_BASE_NONE && insn.mode != MODE_64BIT) || 2158 (insn.sibBase != SIB_BASE_NONE && 2159 insn.sibBase != SIB_BASE_ESP && insn.sibBase != SIB_BASE_RSP && 2160 insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12))) { 2161 indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ : 2162 X86::RIZ); 2163 } else 2164 indexReg = MCOperand::createReg(X86::NoRegister); 2165 } 2166 2167 scaleAmount = MCOperand::createImm(insn.sibScale); 2168 } else { 2169 switch (insn.eaBase) { 2170 case EA_BASE_NONE: 2171 if (insn.eaDisplacement == EA_DISP_NONE) { 2172 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); 2173 return true; 2174 } 2175 if (insn.mode == MODE_64BIT){ 2176 pcrel = insn.startLocation + insn.length; 2177 Dis->tryAddingPcLoadReferenceComment(insn.displacement + pcrel, 2178 insn.startLocation + 2179 insn.displacementOffset); 2180 // Section 2.2.1.6 2181 baseReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIP : 2182 X86::RIP); 2183 } 2184 else 2185 baseReg = MCOperand::createReg(X86::NoRegister); 2186 2187 indexReg = MCOperand::createReg(X86::NoRegister); 2188 break; 2189 case EA_BASE_BX_SI: 2190 baseReg = MCOperand::createReg(X86::BX); 2191 indexReg = MCOperand::createReg(X86::SI); 2192 break; 2193 case EA_BASE_BX_DI: 2194 baseReg = MCOperand::createReg(X86::BX); 2195 indexReg = MCOperand::createReg(X86::DI); 2196 break; 2197 case EA_BASE_BP_SI: 2198 baseReg = MCOperand::createReg(X86::BP); 2199 indexReg = MCOperand::createReg(X86::SI); 2200 break; 2201 case EA_BASE_BP_DI: 2202 baseReg = MCOperand::createReg(X86::BP); 2203 indexReg = MCOperand::createReg(X86::DI); 2204 break; 2205 default: 2206 indexReg = MCOperand::createReg(X86::NoRegister); 2207 switch (insn.eaBase) { 2208 default: 2209 debug("Unexpected eaBase"); 2210 return true; 2211 // Here, we will use the fill-ins defined above. However, 2212 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and 2213 // sib and sib64 were handled in the top-level if, so they're only 2214 // placeholders to keep the compiler happy. 2215 #define ENTRY(x) \ 2216 case EA_BASE_##x: \ 2217 baseReg = MCOperand::createReg(X86::x); break; 2218 ALL_EA_BASES 2219 #undef ENTRY 2220 #define ENTRY(x) case EA_REG_##x: 2221 ALL_REGS 2222 #undef ENTRY 2223 debug("A R/M memory operand may not be a register; " 2224 "the base field must be a base."); 2225 return true; 2226 } 2227 } 2228 2229 scaleAmount = MCOperand::createImm(1); 2230 } 2231 2232 displacement = MCOperand::createImm(insn.displacement); 2233 2234 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 2235 2236 mcInst.addOperand(baseReg); 2237 mcInst.addOperand(scaleAmount); 2238 mcInst.addOperand(indexReg); 2239 2240 const uint8_t dispSize = 2241 (insn.eaDisplacement == EA_DISP_NONE) ? 0 : insn.displacementSize; 2242 2243 if (!Dis->tryAddingSymbolicOperand( 2244 mcInst, insn.displacement + pcrel, insn.startLocation, false, 2245 insn.displacementOffset, dispSize, insn.length)) 2246 mcInst.addOperand(displacement); 2247 mcInst.addOperand(segmentReg); 2248 return false; 2249 } 2250 2251 /// translateRM - Translates an operand stored in the R/M (and possibly SIB) 2252 /// byte of an instruction to LLVM form, and appends it to an MCInst. 2253 /// 2254 /// @param mcInst - The MCInst to append to. 2255 /// @param operand - The operand, as stored in the descriptor table. 2256 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 2257 /// from. 2258 /// @return - 0 on success; nonzero otherwise 2259 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, 2260 InternalInstruction &insn, const MCDisassembler *Dis) { 2261 switch (operand.type) { 2262 default: 2263 debug("Unexpected type for a R/M operand"); 2264 return true; 2265 case TYPE_R8: 2266 case TYPE_R16: 2267 case TYPE_R32: 2268 case TYPE_R64: 2269 case TYPE_Rv: 2270 case TYPE_MM64: 2271 case TYPE_XMM: 2272 case TYPE_YMM: 2273 case TYPE_ZMM: 2274 case TYPE_TMM: 2275 case TYPE_VK_PAIR: 2276 case TYPE_VK: 2277 case TYPE_DEBUGREG: 2278 case TYPE_CONTROLREG: 2279 case TYPE_BNDR: 2280 return translateRMRegister(mcInst, insn); 2281 case TYPE_M: 2282 case TYPE_MVSIBX: 2283 case TYPE_MVSIBY: 2284 case TYPE_MVSIBZ: 2285 return translateRMMemory(mcInst, insn, Dis); 2286 case TYPE_MSIB: 2287 return translateRMMemory(mcInst, insn, Dis, true); 2288 } 2289 } 2290 2291 /// translateFPRegister - Translates a stack position on the FPU stack to its 2292 /// LLVM form, and appends it to an MCInst. 2293 /// 2294 /// @param mcInst - The MCInst to append to. 2295 /// @param stackPos - The stack position to translate. 2296 static void translateFPRegister(MCInst &mcInst, 2297 uint8_t stackPos) { 2298 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos)); 2299 } 2300 2301 /// translateMaskRegister - Translates a 3-bit mask register number to 2302 /// LLVM form, and appends it to an MCInst. 2303 /// 2304 /// @param mcInst - The MCInst to append to. 2305 /// @param maskRegNum - Number of mask register from 0 to 7. 2306 /// @return - false on success; true otherwise. 2307 static bool translateMaskRegister(MCInst &mcInst, 2308 uint8_t maskRegNum) { 2309 if (maskRegNum >= 8) { 2310 debug("Invalid mask register number"); 2311 return true; 2312 } 2313 2314 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum)); 2315 return false; 2316 } 2317 2318 /// translateOperand - Translates an operand stored in an internal instruction 2319 /// to LLVM's format and appends it to an MCInst. 2320 /// 2321 /// @param mcInst - The MCInst to append to. 2322 /// @param operand - The operand, as stored in the descriptor table. 2323 /// @param insn - The internal instruction. 2324 /// @return - false on success; true otherwise. 2325 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, 2326 InternalInstruction &insn, 2327 const MCDisassembler *Dis) { 2328 switch (operand.encoding) { 2329 default: 2330 debug("Unhandled operand encoding during translation"); 2331 return true; 2332 case ENCODING_REG: 2333 translateRegister(mcInst, insn.reg); 2334 return false; 2335 case ENCODING_WRITEMASK: 2336 return translateMaskRegister(mcInst, insn.writemask); 2337 case ENCODING_SIB: 2338 CASE_ENCODING_RM: 2339 CASE_ENCODING_VSIB: 2340 return translateRM(mcInst, operand, insn, Dis); 2341 case ENCODING_IB: 2342 case ENCODING_IW: 2343 case ENCODING_ID: 2344 case ENCODING_IO: 2345 case ENCODING_Iv: 2346 case ENCODING_Ia: 2347 translateImmediate(mcInst, 2348 insn.immediates[insn.numImmediatesTranslated++], 2349 operand, 2350 insn, 2351 Dis); 2352 return false; 2353 case ENCODING_IRC: 2354 mcInst.addOperand(MCOperand::createImm(insn.RC)); 2355 return false; 2356 case ENCODING_SI: 2357 return translateSrcIndex(mcInst, insn); 2358 case ENCODING_DI: 2359 return translateDstIndex(mcInst, insn); 2360 case ENCODING_RB: 2361 case ENCODING_RW: 2362 case ENCODING_RD: 2363 case ENCODING_RO: 2364 case ENCODING_Rv: 2365 translateRegister(mcInst, insn.opcodeRegister); 2366 return false; 2367 case ENCODING_CC: 2368 mcInst.addOperand(MCOperand::createImm(insn.immediates[1])); 2369 return false; 2370 case ENCODING_FP: 2371 translateFPRegister(mcInst, insn.modRM & 7); 2372 return false; 2373 case ENCODING_VVVV: 2374 translateRegister(mcInst, insn.vvvv); 2375 return false; 2376 case ENCODING_DUP: 2377 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0], 2378 insn, Dis); 2379 } 2380 } 2381 2382 /// translateInstruction - Translates an internal instruction and all its 2383 /// operands to an MCInst. 2384 /// 2385 /// @param mcInst - The MCInst to populate with the instruction's data. 2386 /// @param insn - The internal instruction. 2387 /// @return - false on success; true otherwise. 2388 static bool translateInstruction(MCInst &mcInst, 2389 InternalInstruction &insn, 2390 const MCDisassembler *Dis) { 2391 if (!insn.spec) { 2392 debug("Instruction has no specification"); 2393 return true; 2394 } 2395 2396 mcInst.clear(); 2397 mcInst.setOpcode(insn.instructionID); 2398 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 2399 // prefix bytes should be disassembled as xrelease and xacquire then set the 2400 // opcode to those instead of the rep and repne opcodes. 2401 if (insn.xAcquireRelease) { 2402 if(mcInst.getOpcode() == X86::REP_PREFIX) 2403 mcInst.setOpcode(X86::XRELEASE_PREFIX); 2404 else if(mcInst.getOpcode() == X86::REPNE_PREFIX) 2405 mcInst.setOpcode(X86::XACQUIRE_PREFIX); 2406 } 2407 2408 insn.numImmediatesTranslated = 0; 2409 2410 for (const auto &Op : insn.operands) { 2411 if (Op.encoding != ENCODING_NONE) { 2412 if (translateOperand(mcInst, Op, insn, Dis)) { 2413 return true; 2414 } 2415 } 2416 } 2417 2418 return false; 2419 } 2420 2421 static MCDisassembler *createX86Disassembler(const Target &T, 2422 const MCSubtargetInfo &STI, 2423 MCContext &Ctx) { 2424 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo()); 2425 return new X86GenericDisassembler(STI, Ctx, std::move(MII)); 2426 } 2427 2428 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Disassembler() { 2429 // Register the disassembler. 2430 TargetRegistry::RegisterMCDisassembler(getTheX86_32Target(), 2431 createX86Disassembler); 2432 TargetRegistry::RegisterMCDisassembler(getTheX86_64Target(), 2433 createX86Disassembler); 2434 } 2435