1 //===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file defines the WebAssembly-specific TargetTransformInfo 11 /// implementation. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssemblyTargetTransformInfo.h" 16 #include "llvm/CodeGen/CostTable.h" 17 #include "llvm/Support/Debug.h" 18 using namespace llvm; 19 20 #define DEBUG_TYPE "wasmtti" 21 22 TargetTransformInfo::PopcntSupportKind 23 WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const { 24 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 25 return TargetTransformInfo::PSK_FastHardware; 26 } 27 28 unsigned WebAssemblyTTIImpl::getNumberOfRegisters(unsigned ClassID) const { 29 unsigned Result = BaseT::getNumberOfRegisters(ClassID); 30 31 // For SIMD, use at least 16 registers, as a rough guess. 32 bool Vector = (ClassID == 1); 33 if (Vector) 34 Result = std::max(Result, 16u); 35 36 return Result; 37 } 38 39 TypeSize WebAssemblyTTIImpl::getRegisterBitWidth( 40 TargetTransformInfo::RegisterKind K) const { 41 switch (K) { 42 case TargetTransformInfo::RGK_Scalar: 43 return TypeSize::getFixed(64); 44 case TargetTransformInfo::RGK_FixedWidthVector: 45 return TypeSize::getFixed(getST()->hasSIMD128() ? 128 : 64); 46 case TargetTransformInfo::RGK_ScalableVector: 47 return TypeSize::getScalable(0); 48 } 49 50 llvm_unreachable("Unsupported register kind"); 51 } 52 53 InstructionCost WebAssemblyTTIImpl::getArithmeticInstrCost( 54 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 55 TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, 56 TTI::OperandValueProperties Opd1PropInfo, 57 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 58 const Instruction *CxtI) { 59 60 const TTI::OperandValueInfo Op2Info = {Opd2Info, Opd2PropInfo}; 61 62 InstructionCost Cost = 63 BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost( 64 Opcode, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo); 65 66 if (auto *VTy = dyn_cast<VectorType>(Ty)) { 67 switch (Opcode) { 68 case Instruction::LShr: 69 case Instruction::AShr: 70 case Instruction::Shl: 71 // SIMD128's shifts currently only accept a scalar shift count. For each 72 // element, we'll need to extract, op, insert. The following is a rough 73 // approximation. 74 if (!Op2Info.isUniform()) 75 Cost = 76 cast<FixedVectorType>(VTy)->getNumElements() * 77 (TargetTransformInfo::TCC_Basic + 78 getArithmeticInstrCost(Opcode, VTy->getElementType(), CostKind) + 79 TargetTransformInfo::TCC_Basic); 80 break; 81 } 82 } 83 return Cost; 84 } 85 86 InstructionCost WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, 87 Type *Val, 88 unsigned Index) { 89 InstructionCost Cost = 90 BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index); 91 92 // SIMD128's insert/extract currently only take constant indices. 93 if (Index == -1u) 94 return Cost + 25 * TargetTransformInfo::TCC_Expensive; 95 96 return Cost; 97 } 98 99 bool WebAssemblyTTIImpl::areInlineCompatible(const Function *Caller, 100 const Function *Callee) const { 101 // Allow inlining only when the Callee has a subset of the Caller's 102 // features. In principle, we should be able to inline regardless of any 103 // features because WebAssembly supports features at module granularity, not 104 // function granularity, but without this restriction it would be possible for 105 // a module to "forget" about features if all the functions that used them 106 // were inlined. 107 const TargetMachine &TM = getTLI()->getTargetMachine(); 108 109 const FeatureBitset &CallerBits = 110 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 111 const FeatureBitset &CalleeBits = 112 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 113 114 return (CallerBits & CalleeBits) == CalleeBits; 115 } 116 117 void WebAssemblyTTIImpl::getUnrollingPreferences( 118 Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, 119 OptimizationRemarkEmitter *ORE) const { 120 // Scan the loop: don't unroll loops with calls. This is a standard approach 121 // for most (all?) targets. 122 for (BasicBlock *BB : L->blocks()) 123 for (Instruction &I : *BB) 124 if (isa<CallInst>(I) || isa<InvokeInst>(I)) 125 if (const Function *F = cast<CallBase>(I).getCalledFunction()) 126 if (isLoweredToCall(F)) 127 return; 128 129 // The chosen threshold is within the range of 'LoopMicroOpBufferSize' of 130 // the various microarchitectures that use the BasicTTI implementation and 131 // has been selected through heuristics across multiple cores and runtimes. 132 UP.Partial = UP.Runtime = UP.UpperBound = true; 133 UP.PartialThreshold = 30; 134 135 // Avoid unrolling when optimizing for size. 136 UP.OptSizeThreshold = 0; 137 UP.PartialOptSizeThreshold = 0; 138 139 // Set number of instructions optimized when "back edge" 140 // becomes "fall through" to default value of 2. 141 UP.BEInsns = 2; 142 } 143 144 bool WebAssemblyTTIImpl::supportsTailCalls() const { 145 return getST()->hasTailCall(); 146 } 147