1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssembly.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssemblyTargetMachine.h" 18 #include "WebAssemblyTargetObjectFile.h" 19 #include "WebAssemblyTargetTransformInfo.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/CodeGen/RegAllocRegistry.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/Support/CommandLine.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Transforms/Scalar.h" 28 using namespace llvm; 29 30 #define DEBUG_TYPE "wasm" 31 32 extern "C" void LLVMInitializeWebAssemblyTarget() { 33 // Register the target. 34 RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32); 35 RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64); 36 } 37 38 //===----------------------------------------------------------------------===// 39 // WebAssembly Lowering public interface. 40 //===----------------------------------------------------------------------===// 41 42 /// Create an WebAssembly architecture model. 43 /// 44 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 45 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 46 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 47 CodeGenOpt::Level OL) 48 : LLVMTargetMachine(T, 49 TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" 50 : "e-m:e-p:32:32-i64:64-n32:64-S128", 51 TT, CPU, FS, Options, RM, CM, OL), 52 TLOF(make_unique<WebAssemblyTargetObjectFile>()) { 53 // WebAssembly type-checks expressions, but a noreturn function with a return 54 // type that doesn't match the context will cause a check failure. So we lower 55 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 56 // 'unreachable' expression which is meant for that case. 57 this->Options.TrapUnreachable = true; 58 59 initAsmInfo(); 60 61 // Note that we don't use setRequiresStructuredCFG(true). It disables 62 // optimizations than we're ok with, and want, such as critical edge 63 // splitting and tail merging. 64 } 65 66 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 67 68 const WebAssemblySubtarget * 69 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 70 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 71 Attribute FSAttr = F.getFnAttribute("target-features"); 72 73 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 74 ? CPUAttr.getValueAsString().str() 75 : TargetCPU; 76 std::string FS = !FSAttr.hasAttribute(Attribute::None) 77 ? FSAttr.getValueAsString().str() 78 : TargetFS; 79 80 auto &I = SubtargetMap[CPU + FS]; 81 if (!I) { 82 // This needs to be done before we create a new subtarget since any 83 // creation will depend on the TM and the code generation flags on the 84 // function that reside in TargetOptions. 85 resetTargetOptions(F); 86 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 87 } 88 return I.get(); 89 } 90 91 namespace { 92 /// WebAssembly Code Generator Pass Configuration Options. 93 class WebAssemblyPassConfig final : public TargetPassConfig { 94 public: 95 WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM) 96 : TargetPassConfig(TM, PM) {} 97 98 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 99 return getTM<WebAssemblyTargetMachine>(); 100 } 101 102 FunctionPass *createTargetRegisterAllocator(bool) override; 103 104 void addIRPasses() override; 105 bool addInstSelector() override; 106 bool addILPOpts() override; 107 void addPreRegAlloc() override; 108 void addPostRegAlloc() override; 109 void addMachineLateOptimization() override; 110 bool addGCPasses() override { return false; } 111 void addPreEmitPass() override; 112 }; 113 } // end anonymous namespace 114 115 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() { 116 return TargetIRAnalysis([this](const Function &F) { 117 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 118 }); 119 } 120 121 TargetPassConfig * 122 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 123 return new WebAssemblyPassConfig(this, PM); 124 } 125 126 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 127 return nullptr; // No reg alloc 128 } 129 130 //===----------------------------------------------------------------------===// 131 // The following functions are called from lib/CodeGen/Passes.cpp to modify 132 // the CodeGen pass sequence. 133 //===----------------------------------------------------------------------===// 134 135 void WebAssemblyPassConfig::addIRPasses() { 136 if (TM->Options.ThreadModel == ThreadModel::Single) 137 // In "single" mode, atomics get lowered to non-atomics. 138 addPass(createLowerAtomicPass()); 139 else 140 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 141 // control specifically what gets lowered. 142 addPass(createAtomicExpandPass(TM)); 143 144 // Optimize "returned" function attributes. 145 if (getOptLevel() != CodeGenOpt::None) 146 addPass(createWebAssemblyOptimizeReturned()); 147 148 TargetPassConfig::addIRPasses(); 149 } 150 151 bool WebAssemblyPassConfig::addInstSelector() { 152 (void)TargetPassConfig::addInstSelector(); 153 addPass( 154 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 155 // Run the argument-move pass immediately after the ScheduleDAG scheduler 156 // so that we can fix up the ARGUMENT instructions before anything else 157 // sees them in the wrong place. 158 addPass(createWebAssemblyArgumentMove()); 159 // Set the p2align operands. This information is present during ISel, however 160 // it's inconvenient to collect. Collect it now, and update the immediate 161 // operands. 162 addPass(createWebAssemblySetP2AlignOperands()); 163 return false; 164 } 165 166 bool WebAssemblyPassConfig::addILPOpts() { 167 (void)TargetPassConfig::addILPOpts(); 168 return true; 169 } 170 171 void WebAssemblyPassConfig::addPreRegAlloc() { 172 TargetPassConfig::addPreRegAlloc(); 173 174 // Prepare store instructions for register stackifying. 175 if (getOptLevel() != CodeGenOpt::None) 176 addPass(createWebAssemblyStoreResults()); 177 } 178 179 void WebAssemblyPassConfig::addPostRegAlloc() { 180 // TODO: The following CodeGen passes don't currently support code containing 181 // virtual registers. Consider removing their restrictions and re-enabling 182 // them. 183 // 184 185 // Has no asserts of its own, but was not written to handle virtual regs. 186 disablePass(&ShrinkWrapID); 187 // We use our own PrologEpilogInserter which is very slightly modified to 188 // tolerate virtual registers. 189 disablePass(&PrologEpilogCodeInserterID); 190 // Fails with: should be run after register allocation. 191 disablePass(&MachineCopyPropagationID); 192 193 if (getOptLevel() != CodeGenOpt::None) { 194 // Mark registers as representing wasm's expression stack. 195 addPass(createWebAssemblyRegStackify()); 196 197 // Run the register coloring pass to reduce the total number of registers. 198 addPass(createWebAssemblyRegColoring()); 199 } 200 201 TargetPassConfig::addPostRegAlloc(); 202 203 // Run WebAssembly's version of the PrologEpilogInserter. Target-independent 204 // PEI runs after PostRegAlloc and after ShrinkWrap. Putting it here will run 205 // PEI before ShrinkWrap but otherwise in the same position in the order. 206 addPass(createWebAssemblyPEI()); 207 } 208 209 void WebAssemblyPassConfig::addMachineLateOptimization() { 210 disablePass(&MachineCopyPropagationID); 211 disablePass(&PostRASchedulerID); 212 TargetPassConfig::addMachineLateOptimization(); 213 } 214 215 void WebAssemblyPassConfig::addPreEmitPass() { 216 TargetPassConfig::addPreEmitPass(); 217 218 // Eliminate multiple-entry loops. 219 addPass(createWebAssemblyFixIrreducibleControlFlow()); 220 disablePass(&FuncletLayoutID); 221 disablePass(&StackMapLivenessID); 222 disablePass(&LiveDebugValuesID); 223 224 // Put the CFG in structured form; insert BLOCK and LOOP markers. 225 addPass(createWebAssemblyCFGStackify()); 226 227 // Lower br_unless into br_if. 228 addPass(createWebAssemblyLowerBrUnless()); 229 230 // Create a mapping from LLVM CodeGen virtual registers to wasm registers. 231 addPass(createWebAssemblyRegNumbering()); 232 233 // Perform the very last peephole optimizations on the code. 234 if (getOptLevel() != CodeGenOpt::None) 235 addPass(createWebAssemblyPeephole()); 236 } 237