1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssemblyTargetMachine.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssembly.h" 18 #include "WebAssemblyTargetObjectFile.h" 19 #include "WebAssemblyTargetTransformInfo.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/CodeGen/RegAllocRegistry.h" 23 #include "llvm/CodeGen/TargetPassConfig.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Transforms/Scalar.h" 28 using namespace llvm; 29 30 #define DEBUG_TYPE "wasm" 31 32 // Emscripten's asm.js-style exception handling 33 static cl::opt<bool> EnableEmException( 34 "enable-emscripten-cxx-exceptions", 35 cl::desc("WebAssembly Emscripten-style exception handling"), 36 cl::init(false)); 37 38 // Emscripten's asm.js-style setjmp/longjmp handling 39 static cl::opt<bool> EnableEmSjLj( 40 "enable-emscripten-sjlj", 41 cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"), 42 cl::init(false)); 43 44 extern "C" void LLVMInitializeWebAssemblyTarget() { 45 // Register the target. 46 RegisterTargetMachine<WebAssemblyTargetMachine> X( 47 getTheWebAssemblyTarget32()); 48 RegisterTargetMachine<WebAssemblyTargetMachine> Y( 49 getTheWebAssemblyTarget64()); 50 51 // Register exception handling pass to opt 52 initializeWebAssemblyLowerEmscriptenEHSjLjPass( 53 *PassRegistry::getPassRegistry()); 54 } 55 56 //===----------------------------------------------------------------------===// 57 // WebAssembly Lowering public interface. 58 //===----------------------------------------------------------------------===// 59 60 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 61 if (!RM.hasValue()) 62 return Reloc::PIC_; 63 return *RM; 64 } 65 66 /// Create an WebAssembly architecture model. 67 /// 68 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 69 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 70 const TargetOptions &Options, Optional<Reloc::Model> RM, 71 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) 72 : TargetMachine(T, TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" 73 : "e-m:e-p:32:32-i64:64-n32:64-S128", 74 TT, CPU, FS, Options, getEffectiveRelocModel(RM), 75 CM ? *CM : CodeModel::Large, OL), 76 TLOF(TT.isOSBinFormatELF() ? 77 static_cast<TargetLoweringObjectFile*>( 78 new WebAssemblyTargetObjectFileELF()) : 79 static_cast<TargetLoweringObjectFile*>( 80 new WebAssemblyTargetObjectFile())) { 81 // WebAssembly type-checks instructions, but a noreturn function with a return 82 // type that doesn't match the context will cause a check failure. So we lower 83 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 84 // 'unreachable' instructions which is meant for that case. 85 this->Options.TrapUnreachable = true; 86 87 // WebAssembly treats each function as an independent unit. Force 88 // -ffunction-sections, effectively, so that we can emit them independently. 89 if (!TT.isOSBinFormatELF()) { 90 this->Options.FunctionSections = true; 91 this->Options.DataSections = true; 92 this->Options.UniqueSectionNames = true; 93 } 94 95 initAsmInfo(); 96 97 // Note that we don't use setRequiresStructuredCFG(true). It disables 98 // optimizations than we're ok with, and want, such as critical edge 99 // splitting and tail merging. 100 } 101 102 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 103 104 const WebAssemblySubtarget * 105 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 106 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 107 Attribute FSAttr = F.getFnAttribute("target-features"); 108 109 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 110 ? CPUAttr.getValueAsString().str() 111 : TargetCPU; 112 std::string FS = !FSAttr.hasAttribute(Attribute::None) 113 ? FSAttr.getValueAsString().str() 114 : TargetFS; 115 116 auto &I = SubtargetMap[CPU + FS]; 117 if (!I) { 118 // This needs to be done before we create a new subtarget since any 119 // creation will depend on the TM and the code generation flags on the 120 // function that reside in TargetOptions. 121 resetTargetOptions(F); 122 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 123 } 124 return I.get(); 125 } 126 127 namespace { 128 /// WebAssembly Code Generator Pass Configuration Options. 129 class WebAssemblyPassConfig final : public TargetPassConfig { 130 public: 131 WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM) 132 : TargetPassConfig(TM, PM) {} 133 134 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 135 return getTM<WebAssemblyTargetMachine>(); 136 } 137 138 FunctionPass *createTargetRegisterAllocator(bool) override; 139 140 void addIRPasses() override; 141 bool addInstSelector() override; 142 void addPostRegAlloc() override; 143 bool addGCPasses() override { return false; } 144 void addPreEmitPass() override; 145 }; 146 } // end anonymous namespace 147 148 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() { 149 return TargetIRAnalysis([this](const Function &F) { 150 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 151 }); 152 } 153 154 TargetPassConfig * 155 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 156 return new WebAssemblyPassConfig(*this, PM); 157 } 158 159 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 160 return nullptr; // No reg alloc 161 } 162 163 //===----------------------------------------------------------------------===// 164 // The following functions are called from lib/CodeGen/Passes.cpp to modify 165 // the CodeGen pass sequence. 166 //===----------------------------------------------------------------------===// 167 168 void WebAssemblyPassConfig::addIRPasses() { 169 if (TM->Options.ThreadModel == ThreadModel::Single) 170 // In "single" mode, atomics get lowered to non-atomics. 171 addPass(createLowerAtomicPass()); 172 else 173 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 174 // control specifically what gets lowered. 175 addPass(createAtomicExpandPass()); 176 177 // Fix function bitcasts, as WebAssembly requires caller and callee signatures 178 // to match. 179 addPass(createWebAssemblyFixFunctionBitcasts()); 180 181 // Optimize "returned" function attributes. 182 if (getOptLevel() != CodeGenOpt::None) 183 addPass(createWebAssemblyOptimizeReturned()); 184 185 // If exception handling is not enabled and setjmp/longjmp handling is 186 // enabled, we lower invokes into calls and delete unreachable landingpad 187 // blocks. Lowering invokes when there is no EH support is done in 188 // TargetPassConfig::addPassesToHandleExceptions, but this runs after this 189 // function and SjLj handling expects all invokes to be lowered before. 190 if (!EnableEmException) { 191 addPass(createLowerInvokePass()); 192 // The lower invoke pass may create unreachable code. Remove it in order not 193 // to process dead blocks in setjmp/longjmp handling. 194 addPass(createUnreachableBlockEliminationPass()); 195 } 196 197 // Handle exceptions and setjmp/longjmp if enabled. 198 if (EnableEmException || EnableEmSjLj) 199 addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException, 200 EnableEmSjLj)); 201 202 TargetPassConfig::addIRPasses(); 203 } 204 205 bool WebAssemblyPassConfig::addInstSelector() { 206 (void)TargetPassConfig::addInstSelector(); 207 addPass( 208 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 209 // Run the argument-move pass immediately after the ScheduleDAG scheduler 210 // so that we can fix up the ARGUMENT instructions before anything else 211 // sees them in the wrong place. 212 addPass(createWebAssemblyArgumentMove()); 213 // Set the p2align operands. This information is present during ISel, however 214 // it's inconvenient to collect. Collect it now, and update the immediate 215 // operands. 216 addPass(createWebAssemblySetP2AlignOperands()); 217 return false; 218 } 219 220 void WebAssemblyPassConfig::addPostRegAlloc() { 221 // TODO: The following CodeGen passes don't currently support code containing 222 // virtual registers. Consider removing their restrictions and re-enabling 223 // them. 224 225 // Has no asserts of its own, but was not written to handle virtual regs. 226 disablePass(&ShrinkWrapID); 227 228 // These functions all require the NoVRegs property. 229 disablePass(&MachineCopyPropagationID); 230 disablePass(&PostRASchedulerID); 231 disablePass(&FuncletLayoutID); 232 disablePass(&StackMapLivenessID); 233 disablePass(&LiveDebugValuesID); 234 disablePass(&PatchableFunctionID); 235 236 TargetPassConfig::addPostRegAlloc(); 237 } 238 239 void WebAssemblyPassConfig::addPreEmitPass() { 240 TargetPassConfig::addPreEmitPass(); 241 242 // Now that we have a prologue and epilogue and all frame indices are 243 // rewritten, eliminate SP and FP. This allows them to be stackified, 244 // colored, and numbered with the rest of the registers. 245 addPass(createWebAssemblyReplacePhysRegs()); 246 247 // Rewrite pseudo call_indirect instructions as real instructions. 248 // This needs to run before register stackification, because we change the 249 // order of the arguments. 250 addPass(createWebAssemblyCallIndirectFixup()); 251 252 if (getOptLevel() != CodeGenOpt::None) { 253 // LiveIntervals isn't commonly run this late. Re-establish preconditions. 254 addPass(createWebAssemblyPrepareForLiveIntervals()); 255 256 // Depend on LiveIntervals and perform some optimizations on it. 257 addPass(createWebAssemblyOptimizeLiveIntervals()); 258 259 // Prepare store instructions for register stackifying. 260 addPass(createWebAssemblyStoreResults()); 261 262 // Mark registers as representing wasm's value stack. This is a key 263 // code-compression technique in WebAssembly. We run this pass (and 264 // StoreResults above) very late, so that it sees as much code as possible, 265 // including code emitted by PEI and expanded by late tail duplication. 266 addPass(createWebAssemblyRegStackify()); 267 268 // Run the register coloring pass to reduce the total number of registers. 269 // This runs after stackification so that it doesn't consider registers 270 // that become stackified. 271 addPass(createWebAssemblyRegColoring()); 272 } 273 274 // Eliminate multiple-entry loops. Do this before inserting explicit get_local 275 // and set_local operators because we create a new variable that we want 276 // converted into a local. 277 addPass(createWebAssemblyFixIrreducibleControlFlow()); 278 279 // Insert explicit get_local and set_local operators. 280 addPass(createWebAssemblyExplicitLocals()); 281 282 // Sort the blocks of the CFG into topological order, a prerequisite for 283 // BLOCK and LOOP markers. 284 addPass(createWebAssemblyCFGSort()); 285 286 // Insert BLOCK and LOOP markers. 287 addPass(createWebAssemblyCFGStackify()); 288 289 // Lower br_unless into br_if. 290 addPass(createWebAssemblyLowerBrUnless()); 291 292 // Perform the very last peephole optimizations on the code. 293 if (getOptLevel() != CodeGenOpt::None) 294 addPass(createWebAssemblyPeephole()); 295 296 // Create a mapping from LLVM CodeGen virtual registers to wasm registers. 297 addPass(createWebAssemblyRegNumbering()); 298 } 299