1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file defines the WebAssembly-specific subclass of TargetMachine. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #include "WebAssemblyTargetMachine.h" 15 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 16 #include "WebAssembly.h" 17 #include "WebAssemblyTargetObjectFile.h" 18 #include "WebAssemblyTargetTransformInfo.h" 19 #include "llvm/CodeGen/MachineFunctionPass.h" 20 #include "llvm/CodeGen/Passes.h" 21 #include "llvm/CodeGen/RegAllocRegistry.h" 22 #include "llvm/CodeGen/TargetPassConfig.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Target/TargetOptions.h" 26 #include "llvm/Transforms/Scalar.h" 27 #include "llvm/Transforms/Utils.h" 28 using namespace llvm; 29 30 #define DEBUG_TYPE "wasm" 31 32 // Emscripten's asm.js-style exception handling 33 static cl::opt<bool> EnableEmException( 34 "enable-emscripten-cxx-exceptions", 35 cl::desc("WebAssembly Emscripten-style exception handling"), 36 cl::init(false)); 37 38 // Emscripten's asm.js-style setjmp/longjmp handling 39 static cl::opt<bool> EnableEmSjLj( 40 "enable-emscripten-sjlj", 41 cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"), 42 cl::init(false)); 43 44 extern "C" void LLVMInitializeWebAssemblyTarget() { 45 // Register the target. 46 RegisterTargetMachine<WebAssemblyTargetMachine> X( 47 getTheWebAssemblyTarget32()); 48 RegisterTargetMachine<WebAssemblyTargetMachine> Y( 49 getTheWebAssemblyTarget64()); 50 51 // Register backend passes 52 auto &PR = *PassRegistry::getPassRegistry(); 53 initializeWebAssemblyAddMissingPrototypesPass(PR); 54 initializeWebAssemblyLowerEmscriptenEHSjLjPass(PR); 55 initializeLowerGlobalDtorsPass(PR); 56 initializeFixFunctionBitcastsPass(PR); 57 initializeOptimizeReturnedPass(PR); 58 initializeWebAssemblyArgumentMovePass(PR); 59 initializeWebAssemblySetP2AlignOperandsPass(PR); 60 initializeWebAssemblyReplacePhysRegsPass(PR); 61 initializeWebAssemblyPrepareForLiveIntervalsPass(PR); 62 initializeWebAssemblyOptimizeLiveIntervalsPass(PR); 63 initializeWebAssemblyMemIntrinsicResultsPass(PR); 64 initializeWebAssemblyRegStackifyPass(PR); 65 initializeWebAssemblyRegColoringPass(PR); 66 initializeWebAssemblyExplicitLocalsPass(PR); 67 initializeWebAssemblyFixIrreducibleControlFlowPass(PR); 68 initializeWebAssemblyLateEHPreparePass(PR); 69 initializeWebAssemblyExceptionInfoPass(PR); 70 initializeWebAssemblyCFGSortPass(PR); 71 initializeWebAssemblyCFGStackifyPass(PR); 72 initializeWebAssemblyLowerBrUnlessPass(PR); 73 initializeWebAssemblyRegNumberingPass(PR); 74 initializeWebAssemblyPeepholePass(PR); 75 initializeWebAssemblyCallIndirectFixupPass(PR); 76 } 77 78 //===----------------------------------------------------------------------===// 79 // WebAssembly Lowering public interface. 80 //===----------------------------------------------------------------------===// 81 82 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 83 if (!RM.hasValue()) { 84 // Default to static relocation model. This should always be more optimial 85 // than PIC since the static linker can determine all global addresses and 86 // assume direct function calls. 87 return Reloc::Static; 88 } 89 return *RM; 90 } 91 92 /// Create an WebAssembly architecture model. 93 /// 94 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 95 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 96 const TargetOptions &Options, Optional<Reloc::Model> RM, 97 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) 98 : LLVMTargetMachine(T, 99 TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" 100 : "e-m:e-p:32:32-i64:64-n32:64-S128", 101 TT, CPU, FS, Options, getEffectiveRelocModel(RM), 102 getEffectiveCodeModel(CM, CodeModel::Large), OL), 103 TLOF(new WebAssemblyTargetObjectFile()) { 104 // WebAssembly type-checks instructions, but a noreturn function with a return 105 // type that doesn't match the context will cause a check failure. So we lower 106 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 107 // 'unreachable' instructions which is meant for that case. 108 this->Options.TrapUnreachable = true; 109 110 // WebAssembly treats each function as an independent unit. Force 111 // -ffunction-sections, effectively, so that we can emit them independently. 112 this->Options.FunctionSections = true; 113 this->Options.DataSections = true; 114 this->Options.UniqueSectionNames = true; 115 116 initAsmInfo(); 117 118 // Note that we don't use setRequiresStructuredCFG(true). It disables 119 // optimizations than we're ok with, and want, such as critical edge 120 // splitting and tail merging. 121 } 122 123 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 124 125 const WebAssemblySubtarget * 126 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 127 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 128 Attribute FSAttr = F.getFnAttribute("target-features"); 129 130 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 131 ? CPUAttr.getValueAsString().str() 132 : TargetCPU; 133 std::string FS = !FSAttr.hasAttribute(Attribute::None) 134 ? FSAttr.getValueAsString().str() 135 : TargetFS; 136 137 auto &I = SubtargetMap[CPU + FS]; 138 if (!I) { 139 // This needs to be done before we create a new subtarget since any 140 // creation will depend on the TM and the code generation flags on the 141 // function that reside in TargetOptions. 142 resetTargetOptions(F); 143 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 144 } 145 return I.get(); 146 } 147 148 namespace { 149 class StripThreadLocal final : public ModulePass { 150 // The default thread model for wasm is single, where thread-local variables 151 // are identical to regular globals and should be treated the same. So this 152 // pass just converts all GlobalVariables to NotThreadLocal 153 static char ID; 154 155 public: 156 StripThreadLocal() : ModulePass(ID) {} 157 bool runOnModule(Module &M) override { 158 for (auto &GV : M.globals()) 159 GV.setThreadLocalMode(GlobalValue::ThreadLocalMode::NotThreadLocal); 160 return true; 161 } 162 }; 163 char StripThreadLocal::ID = 0; 164 165 /// WebAssembly Code Generator Pass Configuration Options. 166 class WebAssemblyPassConfig final : public TargetPassConfig { 167 public: 168 WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM) 169 : TargetPassConfig(TM, PM) {} 170 171 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 172 return getTM<WebAssemblyTargetMachine>(); 173 } 174 175 FunctionPass *createTargetRegisterAllocator(bool) override; 176 177 void addIRPasses() override; 178 bool addInstSelector() override; 179 void addPostRegAlloc() override; 180 bool addGCPasses() override { return false; } 181 void addPreEmitPass() override; 182 }; 183 } // end anonymous namespace 184 185 TargetTransformInfo 186 WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) { 187 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 188 } 189 190 TargetPassConfig * 191 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 192 return new WebAssemblyPassConfig(*this, PM); 193 } 194 195 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 196 return nullptr; // No reg alloc 197 } 198 199 //===----------------------------------------------------------------------===// 200 // The following functions are called from lib/CodeGen/Passes.cpp to modify 201 // the CodeGen pass sequence. 202 //===----------------------------------------------------------------------===// 203 204 void WebAssemblyPassConfig::addIRPasses() { 205 if (TM->Options.ThreadModel == ThreadModel::Single) { 206 // In "single" mode, atomics get lowered to non-atomics. 207 addPass(createLowerAtomicPass()); 208 addPass(new StripThreadLocal()); 209 } else { 210 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 211 // control specifically what gets lowered. 212 addPass(createAtomicExpandPass()); 213 } 214 215 // Add signatures to prototype-less function declarations 216 addPass(createWebAssemblyAddMissingPrototypes()); 217 218 // Lower .llvm.global_dtors into .llvm_global_ctors with __cxa_atexit calls. 219 addPass(createWebAssemblyLowerGlobalDtors()); 220 221 // Fix function bitcasts, as WebAssembly requires caller and callee signatures 222 // to match. 223 addPass(createWebAssemblyFixFunctionBitcasts()); 224 225 // Optimize "returned" function attributes. 226 if (getOptLevel() != CodeGenOpt::None) 227 addPass(createWebAssemblyOptimizeReturned()); 228 229 // If exception handling is not enabled and setjmp/longjmp handling is 230 // enabled, we lower invokes into calls and delete unreachable landingpad 231 // blocks. Lowering invokes when there is no EH support is done in 232 // TargetPassConfig::addPassesToHandleExceptions, but this runs after this 233 // function and SjLj handling expects all invokes to be lowered before. 234 if (!EnableEmException && 235 TM->Options.ExceptionModel == ExceptionHandling::None) { 236 addPass(createLowerInvokePass()); 237 // The lower invoke pass may create unreachable code. Remove it in order not 238 // to process dead blocks in setjmp/longjmp handling. 239 addPass(createUnreachableBlockEliminationPass()); 240 } 241 242 // Handle exceptions and setjmp/longjmp if enabled. 243 if (EnableEmException || EnableEmSjLj) 244 addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException, 245 EnableEmSjLj)); 246 247 TargetPassConfig::addIRPasses(); 248 } 249 250 bool WebAssemblyPassConfig::addInstSelector() { 251 (void)TargetPassConfig::addInstSelector(); 252 addPass( 253 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 254 // Run the argument-move pass immediately after the ScheduleDAG scheduler 255 // so that we can fix up the ARGUMENT instructions before anything else 256 // sees them in the wrong place. 257 addPass(createWebAssemblyArgumentMove()); 258 // Set the p2align operands. This information is present during ISel, however 259 // it's inconvenient to collect. Collect it now, and update the immediate 260 // operands. 261 addPass(createWebAssemblySetP2AlignOperands()); 262 return false; 263 } 264 265 void WebAssemblyPassConfig::addPostRegAlloc() { 266 // TODO: The following CodeGen passes don't currently support code containing 267 // virtual registers. Consider removing their restrictions and re-enabling 268 // them. 269 270 // These functions all require the NoVRegs property. 271 disablePass(&MachineCopyPropagationID); 272 disablePass(&PostRAMachineSinkingID); 273 disablePass(&PostRASchedulerID); 274 disablePass(&FuncletLayoutID); 275 disablePass(&StackMapLivenessID); 276 disablePass(&LiveDebugValuesID); 277 disablePass(&PatchableFunctionID); 278 disablePass(&ShrinkWrapID); 279 280 TargetPassConfig::addPostRegAlloc(); 281 } 282 283 void WebAssemblyPassConfig::addPreEmitPass() { 284 TargetPassConfig::addPreEmitPass(); 285 286 // Rewrite pseudo call_indirect instructions as real instructions. 287 // This needs to run before register stackification, because we change the 288 // order of the arguments. 289 addPass(createWebAssemblyCallIndirectFixup()); 290 291 // Eliminate multiple-entry loops. 292 addPass(createWebAssemblyFixIrreducibleControlFlow()); 293 294 // Do various transformations for exception handling. 295 // Every CFG-changing optimizations should come before this. 296 addPass(createWebAssemblyLateEHPrepare()); 297 298 // Now that we have a prologue and epilogue and all frame indices are 299 // rewritten, eliminate SP and FP. This allows them to be stackified, 300 // colored, and numbered with the rest of the registers. 301 addPass(createWebAssemblyReplacePhysRegs()); 302 303 // Preparations and optimizations related to register stackification. 304 if (getOptLevel() != CodeGenOpt::None) { 305 // LiveIntervals isn't commonly run this late. Re-establish preconditions. 306 addPass(createWebAssemblyPrepareForLiveIntervals()); 307 308 // Depend on LiveIntervals and perform some optimizations on it. 309 addPass(createWebAssemblyOptimizeLiveIntervals()); 310 311 // Prepare memory intrinsic calls for register stackifying. 312 addPass(createWebAssemblyMemIntrinsicResults()); 313 314 // Mark registers as representing wasm's value stack. This is a key 315 // code-compression technique in WebAssembly. We run this pass (and 316 // MemIntrinsicResults above) very late, so that it sees as much code as 317 // possible, including code emitted by PEI and expanded by late tail 318 // duplication. 319 addPass(createWebAssemblyRegStackify()); 320 321 // Run the register coloring pass to reduce the total number of registers. 322 // This runs after stackification so that it doesn't consider registers 323 // that become stackified. 324 addPass(createWebAssemblyRegColoring()); 325 } 326 327 // Insert explicit local.get and local.set operators. 328 addPass(createWebAssemblyExplicitLocals()); 329 330 // Sort the blocks of the CFG into topological order, a prerequisite for 331 // BLOCK and LOOP markers. 332 addPass(createWebAssemblyCFGSort()); 333 334 // Insert BLOCK and LOOP markers. 335 addPass(createWebAssemblyCFGStackify()); 336 337 // Lower br_unless into br_if. 338 addPass(createWebAssemblyLowerBrUnless()); 339 340 // Perform the very last peephole optimizations on the code. 341 if (getOptLevel() != CodeGenOpt::None) 342 addPass(createWebAssemblyPeephole()); 343 344 // Create a mapping from LLVM CodeGen virtual registers to wasm registers. 345 addPass(createWebAssemblyRegNumbering()); 346 } 347