1 //===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the VE Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/VEMCTargetDesc.h" 14 #include "TargetInfo/VETargetInfo.h" 15 #include "VE.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/Support/TargetRegistry.h" 22 23 using namespace llvm; 24 25 #define DEBUG_TYPE "ve-disassembler" 26 27 typedef MCDisassembler::DecodeStatus DecodeStatus; 28 29 namespace { 30 31 /// A disassembler class for VE. 32 class VEDisassembler : public MCDisassembler { 33 public: 34 VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 35 : MCDisassembler(STI, Ctx) {} 36 virtual ~VEDisassembler() {} 37 38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 39 ArrayRef<uint8_t> Bytes, uint64_t Address, 40 raw_ostream &CStream) const override; 41 }; 42 } // namespace 43 44 static MCDisassembler *createVEDisassembler(const Target &T, 45 const MCSubtargetInfo &STI, 46 MCContext &Ctx) { 47 return new VEDisassembler(STI, Ctx); 48 } 49 50 extern "C" void LLVMInitializeVEDisassembler() { 51 // Register the disassembler. 52 TargetRegistry::RegisterMCDisassembler(getTheVETarget(), 53 createVEDisassembler); 54 } 55 56 static const unsigned I32RegDecoderTable[] = { 57 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6, 58 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13, 59 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20, 60 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27, 61 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34, 62 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41, 63 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48, 64 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55, 65 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62, 66 VE::SW63}; 67 68 static const unsigned I64RegDecoderTable[] = { 69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, 70 VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, 71 VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, 72 VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, 73 VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, 74 VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, 75 VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, 76 VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, 77 VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62, 78 VE::SX63}; 79 80 static const unsigned F32RegDecoderTable[] = { 81 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6, 82 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13, 83 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20, 84 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27, 85 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34, 86 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41, 87 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48, 88 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55, 89 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62, 90 VE::SF63}; 91 92 static const unsigned F128RegDecoderTable[] = { 93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7, 94 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15, 95 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23, 96 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31}; 97 98 static const unsigned MiscRegDecoderTable[] = { 99 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister, 100 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR, 101 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3, 102 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister, 103 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3, 104 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7, 105 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, 106 VE::PMC12, VE::PMC13, VE::PMC14}; 107 108 static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder) { 111 if (RegNo > 63) 112 return MCDisassembler::Fail; 113 unsigned Reg = I32RegDecoderTable[RegNo]; 114 Inst.addOperand(MCOperand::createReg(Reg)); 115 return MCDisassembler::Success; 116 } 117 118 static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder) { 121 if (RegNo > 63) 122 return MCDisassembler::Fail; 123 unsigned Reg = I64RegDecoderTable[RegNo]; 124 Inst.addOperand(MCOperand::createReg(Reg)); 125 return MCDisassembler::Success; 126 } 127 128 static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder) { 131 if (RegNo > 63) 132 return MCDisassembler::Fail; 133 unsigned Reg = F32RegDecoderTable[RegNo]; 134 Inst.addOperand(MCOperand::createReg(Reg)); 135 return MCDisassembler::Success; 136 } 137 138 static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder) { 141 if (RegNo % 2 || RegNo > 63) 142 return MCDisassembler::Fail; 143 unsigned Reg = F128RegDecoderTable[RegNo / 2]; 144 Inst.addOperand(MCOperand::createReg(Reg)); 145 return MCDisassembler::Success; 146 } 147 148 static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder) { 151 if (RegNo > 30) 152 return MCDisassembler::Fail; 153 unsigned Reg = MiscRegDecoderTable[RegNo]; 154 if (Reg == VE::NoRegister) 155 return MCDisassembler::Fail; 156 Inst.addOperand(MCOperand::createReg(Reg)); 157 return MCDisassembler::Success; 158 } 159 160 static DecodeStatus DecodeASX(MCInst &Inst, uint64_t insn, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, 167 const void *Decoder); 168 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, 171 const void *Decoder); 172 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCASI64(MCInst &Inst, uint64_t insn, uint64_t Address, 183 const void *Decoder); 184 static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address, 185 const void *Decoder); 186 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, 187 const void *Decoder); 188 static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address, 189 const void *Decoder); 190 static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeRDOperand(MCInst &Inst, uint64_t insn, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn, 195 uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn, 198 uint64_t Address, 199 const void *Decoder); 200 201 #include "VEGenDisassemblerTables.inc" 202 203 /// Read four bytes from the ArrayRef and return 32 bit word. 204 static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address, 205 uint64_t &Size, uint64_t &Insn, 206 bool IsLittleEndian) { 207 // We want to read exactly 8 Bytes of data. 208 if (Bytes.size() < 8) { 209 Size = 0; 210 return MCDisassembler::Fail; 211 } 212 213 Insn = IsLittleEndian 214 ? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | 215 ((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) | 216 ((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) | 217 ((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56) 218 : ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) | 219 ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) | 220 ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) | 221 ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56); 222 223 return MCDisassembler::Success; 224 } 225 226 DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 227 ArrayRef<uint8_t> Bytes, 228 uint64_t Address, 229 raw_ostream &CStream) const { 230 uint64_t Insn; 231 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); 232 DecodeStatus Result = 233 readInstruction64(Bytes, Address, Size, Insn, isLittleEndian); 234 if (Result == MCDisassembler::Fail) 235 return MCDisassembler::Fail; 236 237 // Calling the auto-generated decoder function. 238 239 Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI); 240 241 if (Result != MCDisassembler::Fail) { 242 Size = 8; 243 return Result; 244 } 245 246 return MCDisassembler::Fail; 247 } 248 249 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address, 250 const void *Decoder); 251 252 static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address, 253 const void *Decoder) { 254 unsigned sy = fieldFromInstruction(insn, 40, 7); 255 bool cy = fieldFromInstruction(insn, 47, 1); 256 unsigned sz = fieldFromInstruction(insn, 32, 7); 257 bool cz = fieldFromInstruction(insn, 39, 1); 258 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); 259 DecodeStatus status; 260 261 // Decode sz. 262 if (cz) { 263 status = DecodeI64RegisterClass(MI, sz, Address, Decoder); 264 if (status != MCDisassembler::Success) 265 return status; 266 } else { 267 MI.addOperand(MCOperand::createImm(0)); 268 } 269 270 // Decode sy. 271 if (cy) { 272 status = DecodeI64RegisterClass(MI, sy, Address, Decoder); 273 if (status != MCDisassembler::Success) 274 return status; 275 } else { 276 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 277 } 278 279 // Decode simm32. 280 MI.addOperand(MCOperand::createImm(simm32)); 281 282 return MCDisassembler::Success; 283 } 284 285 static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address, 286 const void *Decoder) { 287 unsigned sz = fieldFromInstruction(insn, 32, 7); 288 bool cz = fieldFromInstruction(insn, 39, 1); 289 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); 290 DecodeStatus status; 291 292 // Decode sz. 293 if (cz) { 294 status = DecodeI64RegisterClass(MI, sz, Address, Decoder); 295 if (status != MCDisassembler::Success) 296 return status; 297 } else { 298 MI.addOperand(MCOperand::createImm(0)); 299 } 300 301 // Decode simm32. 302 MI.addOperand(MCOperand::createImm(simm32)); 303 304 return MCDisassembler::Success; 305 } 306 307 static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address, 308 const void *Decoder, bool isLoad, 309 DecodeFunc DecodeSX) { 310 unsigned sx = fieldFromInstruction(insn, 48, 7); 311 312 DecodeStatus status; 313 if (isLoad) { 314 status = DecodeSX(MI, sx, Address, Decoder); 315 if (status != MCDisassembler::Success) 316 return status; 317 } 318 319 status = DecodeASX(MI, insn, Address, Decoder); 320 if (status != MCDisassembler::Success) 321 return status; 322 323 if (!isLoad) { 324 status = DecodeSX(MI, sx, Address, Decoder); 325 if (status != MCDisassembler::Success) 326 return status; 327 } 328 return MCDisassembler::Success; 329 } 330 331 static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address, 332 const void *Decoder, bool isLoad, 333 DecodeFunc DecodeSX) { 334 unsigned sx = fieldFromInstruction(insn, 48, 7); 335 336 DecodeStatus status; 337 if (isLoad) { 338 status = DecodeSX(MI, sx, Address, Decoder); 339 if (status != MCDisassembler::Success) 340 return status; 341 } 342 343 status = DecodeAS(MI, insn, Address, Decoder); 344 if (status != MCDisassembler::Success) 345 return status; 346 347 if (!isLoad) { 348 status = DecodeSX(MI, sx, Address, Decoder); 349 if (status != MCDisassembler::Success) 350 return status; 351 } 352 return MCDisassembler::Success; 353 } 354 355 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, 356 const void *Decoder) { 357 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass); 358 } 359 360 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, 361 uint64_t Address, const void *Decoder) { 362 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass); 363 } 364 365 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, 366 const void *Decoder) { 367 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); 368 } 369 370 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, 371 uint64_t Address, const void *Decoder) { 372 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass); 373 } 374 375 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, 376 const void *Decoder) { 377 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass); 378 } 379 380 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, 381 uint64_t Address, const void *Decoder) { 382 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass); 383 } 384 385 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, 386 uint64_t Address, const void *Decoder) { 387 return DecodeMemAS(Inst, insn, Address, Decoder, true, 388 DecodeI64RegisterClass); 389 } 390 391 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, 392 uint64_t Address, const void *Decoder) { 393 return DecodeMemAS(Inst, insn, Address, Decoder, false, 394 DecodeI64RegisterClass); 395 } 396 397 static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address, 398 const void *Decoder, bool isImmOnly, bool isUImm, 399 DecodeFunc DecodeSX) { 400 unsigned sx = fieldFromInstruction(insn, 48, 7); 401 bool cy = fieldFromInstruction(insn, 47, 1); 402 unsigned sy = fieldFromInstruction(insn, 40, 7); 403 404 // Add $sx. 405 DecodeStatus status; 406 status = DecodeSX(MI, sx, Address, Decoder); 407 if (status != MCDisassembler::Success) 408 return status; 409 410 // Add $disp($sz). 411 status = DecodeAS(MI, insn, Address, Decoder); 412 if (status != MCDisassembler::Success) 413 return status; 414 415 // Add $sy. 416 if (cy && !isImmOnly) { 417 status = DecodeSX(MI, sy, Address, Decoder); 418 if (status != MCDisassembler::Success) 419 return status; 420 } else { 421 if (isUImm) 422 MI.addOperand(MCOperand::createImm(sy)); 423 else 424 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 425 } 426 427 // Add $sd. 428 status = DecodeSX(MI, sx, Address, Decoder); 429 if (status != MCDisassembler::Success) 430 return status; 431 432 return MCDisassembler::Success; 433 } 434 435 static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address, 436 const void *Decoder) { 437 return DecodeCAS(MI, insn, Address, Decoder, false, true, 438 DecodeI64RegisterClass); 439 } 440 441 static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address, 442 const void *Decoder) { 443 return DecodeCAS(MI, insn, Address, Decoder, false, true, 444 DecodeI32RegisterClass); 445 } 446 447 static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address, 448 const void *Decoder) { 449 return DecodeCAS(MI, insn, Address, Decoder, false, false, 450 DecodeI64RegisterClass); 451 } 452 453 static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address, 454 const void *Decoder) { 455 return DecodeCAS(MI, insn, Address, Decoder, false, false, 456 DecodeI32RegisterClass); 457 } 458 459 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, 460 const void *Decoder) { 461 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); 462 } 463 464 static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address, 465 const void *Decoder) { 466 uint64_t tgt = SignExtend64<7>(insn); 467 MI.addOperand(MCOperand::createImm(tgt)); 468 return MCDisassembler::Success; 469 } 470 471 static bool isIntegerBCKind(MCInst &MI) { 472 473 #define BCm_kind(NAME) \ 474 case NAME##rri: \ 475 case NAME##rzi: \ 476 case NAME##iri: \ 477 case NAME##izi: \ 478 case NAME##rri_nt: \ 479 case NAME##rzi_nt: \ 480 case NAME##iri_nt: \ 481 case NAME##izi_nt: \ 482 case NAME##rri_t: \ 483 case NAME##rzi_t: \ 484 case NAME##iri_t: \ 485 case NAME##izi_t: 486 487 #define BCRm_kind(NAME) \ 488 case NAME##rr: \ 489 case NAME##ir: \ 490 case NAME##rr_nt: \ 491 case NAME##ir_nt: \ 492 case NAME##rr_t: \ 493 case NAME##ir_t: 494 495 { 496 using namespace llvm::VE; 497 switch (MI.getOpcode()) { 498 BCm_kind(BCFL) BCm_kind(BCFW) BCRm_kind(BRCFL) 499 BCRm_kind(BRCFW) return true; 500 } 501 } 502 #undef BCm_kind 503 504 return false; 505 } 506 507 // Decode CC Operand field. 508 static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address, 509 const void *Decoder) { 510 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); 511 return MCDisassembler::Success; 512 } 513 514 // Decode RD Operand field. 515 static DecodeStatus DecodeRDOperand(MCInst &MI, uint64_t cf, uint64_t Address, 516 const void *Decoder) { 517 MI.addOperand(MCOperand::createImm(VEValToRD(cf))); 518 return MCDisassembler::Success; 519 } 520 521 // Decode branch condition instruction and CCOperand field in it. 522 static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn, 523 uint64_t Address, 524 const void *Decoder) { 525 unsigned cf = fieldFromInstruction(insn, 48, 4); 526 bool cy = fieldFromInstruction(insn, 47, 1); 527 unsigned sy = fieldFromInstruction(insn, 40, 7); 528 529 // Decode cf. 530 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); 531 532 // Decode sy. 533 DecodeStatus status; 534 if (cy) { 535 status = DecodeI64RegisterClass(MI, sy, Address, Decoder); 536 if (status != MCDisassembler::Success) 537 return status; 538 } else { 539 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); 540 } 541 542 // Decode MEMri. 543 return DecodeAS(MI, insn, Address, Decoder); 544 } 545 546 static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn, 547 uint64_t Address, 548 const void *Decoder) { 549 // Decode MEMri. 550 return DecodeAS(MI, insn, Address, Decoder); 551 } 552