1 //===- SPIRVModuleAnalysis.cpp - analysis of global instrs & regs - C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // The analysis collects instructions that should be output at the module level 10 // and performs the global register numbering. 11 // 12 // The results of this analysis are used in AsmPrinter to rename registers 13 // globally and to output required instructions at the module level. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "SPIRVModuleAnalysis.h" 18 #include "MCTargetDesc/SPIRVBaseInfo.h" 19 #include "MCTargetDesc/SPIRVMCTargetDesc.h" 20 #include "SPIRV.h" 21 #include "SPIRVSubtarget.h" 22 #include "SPIRVTargetMachine.h" 23 #include "SPIRVUtils.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/CodeGen/MachineModuleInfo.h" 26 #include "llvm/CodeGen/TargetPassConfig.h" 27 28 using namespace llvm; 29 30 #define DEBUG_TYPE "spirv-module-analysis" 31 32 static cl::opt<bool> 33 SPVDumpDeps("spv-dump-deps", 34 cl::desc("Dump MIR with SPIR-V dependencies info"), 35 cl::Optional, cl::init(false)); 36 37 static cl::list<SPIRV::Capability::Capability> 38 AvoidCapabilities("avoid-spirv-capabilities", 39 cl::desc("SPIR-V capabilities to avoid if there are " 40 "other options enabling a feature"), 41 cl::ZeroOrMore, cl::Hidden, 42 cl::values(clEnumValN(SPIRV::Capability::Shader, "Shader", 43 "SPIR-V Shader capability"))); 44 // Use sets instead of cl::list to check "if contains" condition 45 struct AvoidCapabilitiesSet { 46 SmallSet<SPIRV::Capability::Capability, 4> S; 47 AvoidCapabilitiesSet() { 48 for (auto Cap : AvoidCapabilities) 49 S.insert(Cap); 50 } 51 }; 52 53 char llvm::SPIRVModuleAnalysis::ID = 0; 54 55 namespace llvm { 56 void initializeSPIRVModuleAnalysisPass(PassRegistry &); 57 } // namespace llvm 58 59 INITIALIZE_PASS(SPIRVModuleAnalysis, DEBUG_TYPE, "SPIRV module analysis", true, 60 true) 61 62 // Retrieve an unsigned from an MDNode with a list of them as operands. 63 static unsigned getMetadataUInt(MDNode *MdNode, unsigned OpIndex, 64 unsigned DefaultVal = 0) { 65 if (MdNode && OpIndex < MdNode->getNumOperands()) { 66 const auto &Op = MdNode->getOperand(OpIndex); 67 return mdconst::extract<ConstantInt>(Op)->getZExtValue(); 68 } 69 return DefaultVal; 70 } 71 72 static SPIRV::Requirements 73 getSymbolicOperandRequirements(SPIRV::OperandCategory::OperandCategory Category, 74 unsigned i, const SPIRVSubtarget &ST, 75 SPIRV::RequirementHandler &Reqs) { 76 static AvoidCapabilitiesSet 77 AvoidCaps; // contains capabilities to avoid if there is another option 78 79 VersionTuple ReqMinVer = getSymbolicOperandMinVersion(Category, i); 80 VersionTuple ReqMaxVer = getSymbolicOperandMaxVersion(Category, i); 81 VersionTuple SPIRVVersion = ST.getSPIRVVersion(); 82 bool MinVerOK = SPIRVVersion.empty() || SPIRVVersion >= ReqMinVer; 83 bool MaxVerOK = 84 ReqMaxVer.empty() || SPIRVVersion.empty() || SPIRVVersion <= ReqMaxVer; 85 CapabilityList ReqCaps = getSymbolicOperandCapabilities(Category, i); 86 ExtensionList ReqExts = getSymbolicOperandExtensions(Category, i); 87 if (ReqCaps.empty()) { 88 if (ReqExts.empty()) { 89 if (MinVerOK && MaxVerOK) 90 return {true, {}, {}, ReqMinVer, ReqMaxVer}; 91 return {false, {}, {}, VersionTuple(), VersionTuple()}; 92 } 93 } else if (MinVerOK && MaxVerOK) { 94 if (ReqCaps.size() == 1) { 95 auto Cap = ReqCaps[0]; 96 if (Reqs.isCapabilityAvailable(Cap)) 97 return {true, {Cap}, ReqExts, ReqMinVer, ReqMaxVer}; 98 } else { 99 // By SPIR-V specification: "If an instruction, enumerant, or other 100 // feature specifies multiple enabling capabilities, only one such 101 // capability needs to be declared to use the feature." However, one 102 // capability may be preferred over another. We use command line 103 // argument(s) and AvoidCapabilities to avoid selection of certain 104 // capabilities if there are other options. 105 CapabilityList UseCaps; 106 for (auto Cap : ReqCaps) 107 if (Reqs.isCapabilityAvailable(Cap)) 108 UseCaps.push_back(Cap); 109 for (size_t i = 0, Sz = UseCaps.size(); i < Sz; ++i) { 110 auto Cap = UseCaps[i]; 111 if (i == Sz - 1 || !AvoidCaps.S.contains(Cap)) 112 return {true, {Cap}, ReqExts, ReqMinVer, ReqMaxVer}; 113 } 114 } 115 } 116 // If there are no capabilities, or we can't satisfy the version or 117 // capability requirements, use the list of extensions (if the subtarget 118 // can handle them all). 119 if (llvm::all_of(ReqExts, [&ST](const SPIRV::Extension::Extension &Ext) { 120 return ST.canUseExtension(Ext); 121 })) { 122 return {true, 123 {}, 124 ReqExts, 125 VersionTuple(), 126 VersionTuple()}; // TODO: add versions to extensions. 127 } 128 return {false, {}, {}, VersionTuple(), VersionTuple()}; 129 } 130 131 void SPIRVModuleAnalysis::setBaseInfo(const Module &M) { 132 MAI.MaxID = 0; 133 for (int i = 0; i < SPIRV::NUM_MODULE_SECTIONS; i++) 134 MAI.MS[i].clear(); 135 MAI.RegisterAliasTable.clear(); 136 MAI.InstrsToDelete.clear(); 137 MAI.FuncMap.clear(); 138 MAI.GlobalVarList.clear(); 139 MAI.ExtInstSetMap.clear(); 140 MAI.Reqs.clear(); 141 MAI.Reqs.initAvailableCapabilities(*ST); 142 143 // TODO: determine memory model and source language from the configuratoin. 144 if (auto MemModel = M.getNamedMetadata("spirv.MemoryModel")) { 145 auto MemMD = MemModel->getOperand(0); 146 MAI.Addr = static_cast<SPIRV::AddressingModel::AddressingModel>( 147 getMetadataUInt(MemMD, 0)); 148 MAI.Mem = 149 static_cast<SPIRV::MemoryModel::MemoryModel>(getMetadataUInt(MemMD, 1)); 150 } else { 151 // TODO: Add support for VulkanMemoryModel. 152 MAI.Mem = ST->isOpenCLEnv() ? SPIRV::MemoryModel::OpenCL 153 : SPIRV::MemoryModel::GLSL450; 154 if (MAI.Mem == SPIRV::MemoryModel::OpenCL) { 155 unsigned PtrSize = ST->getPointerSize(); 156 MAI.Addr = PtrSize == 32 ? SPIRV::AddressingModel::Physical32 157 : PtrSize == 64 ? SPIRV::AddressingModel::Physical64 158 : SPIRV::AddressingModel::Logical; 159 } else { 160 // TODO: Add support for PhysicalStorageBufferAddress. 161 MAI.Addr = SPIRV::AddressingModel::Logical; 162 } 163 } 164 // Get the OpenCL version number from metadata. 165 // TODO: support other source languages. 166 if (auto VerNode = M.getNamedMetadata("opencl.ocl.version")) { 167 MAI.SrcLang = SPIRV::SourceLanguage::OpenCL_C; 168 // Construct version literal in accordance with SPIRV-LLVM-Translator. 169 // TODO: support multiple OCL version metadata. 170 assert(VerNode->getNumOperands() > 0 && "Invalid SPIR"); 171 auto VersionMD = VerNode->getOperand(0); 172 unsigned MajorNum = getMetadataUInt(VersionMD, 0, 2); 173 unsigned MinorNum = getMetadataUInt(VersionMD, 1); 174 unsigned RevNum = getMetadataUInt(VersionMD, 2); 175 // Prevent Major part of OpenCL version to be 0 176 MAI.SrcLangVersion = 177 (std::max(1U, MajorNum) * 100 + MinorNum) * 1000 + RevNum; 178 } else { 179 // If there is no information about OpenCL version we are forced to generate 180 // OpenCL 1.0 by default for the OpenCL environment to avoid puzzling 181 // run-times with Unknown/0.0 version output. For a reference, LLVM-SPIRV 182 // Translator avoids potential issues with run-times in a similar manner. 183 if (ST->isOpenCLEnv()) { 184 MAI.SrcLang = SPIRV::SourceLanguage::OpenCL_CPP; 185 MAI.SrcLangVersion = 100000; 186 } else { 187 MAI.SrcLang = SPIRV::SourceLanguage::Unknown; 188 MAI.SrcLangVersion = 0; 189 } 190 } 191 192 if (auto ExtNode = M.getNamedMetadata("opencl.used.extensions")) { 193 for (unsigned I = 0, E = ExtNode->getNumOperands(); I != E; ++I) { 194 MDNode *MD = ExtNode->getOperand(I); 195 if (!MD || MD->getNumOperands() == 0) 196 continue; 197 for (unsigned J = 0, N = MD->getNumOperands(); J != N; ++J) 198 MAI.SrcExt.insert(cast<MDString>(MD->getOperand(J))->getString()); 199 } 200 } 201 202 // Update required capabilities for this memory model, addressing model and 203 // source language. 204 MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::MemoryModelOperand, 205 MAI.Mem, *ST); 206 MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::SourceLanguageOperand, 207 MAI.SrcLang, *ST); 208 MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::AddressingModelOperand, 209 MAI.Addr, *ST); 210 211 if (ST->isOpenCLEnv()) { 212 // TODO: check if it's required by default. 213 MAI.ExtInstSetMap[static_cast<unsigned>( 214 SPIRV::InstructionSet::OpenCL_std)] = 215 Register::index2VirtReg(MAI.getNextID()); 216 } 217 } 218 219 // Collect MI which defines the register in the given machine function. 220 static void collectDefInstr(Register Reg, const MachineFunction *MF, 221 SPIRV::ModuleAnalysisInfo *MAI, 222 SPIRV::ModuleSectionType MSType, 223 bool DoInsert = true) { 224 assert(MAI->hasRegisterAlias(MF, Reg) && "Cannot find register alias"); 225 MachineInstr *MI = MF->getRegInfo().getUniqueVRegDef(Reg); 226 assert(MI && "There should be an instruction that defines the register"); 227 MAI->setSkipEmission(MI); 228 if (DoInsert) 229 MAI->MS[MSType].push_back(MI); 230 } 231 232 void SPIRVModuleAnalysis::collectGlobalEntities( 233 const std::vector<SPIRV::DTSortableEntry *> &DepsGraph, 234 SPIRV::ModuleSectionType MSType, 235 std::function<bool(const SPIRV::DTSortableEntry *)> Pred, 236 bool UsePreOrder = false) { 237 DenseSet<const SPIRV::DTSortableEntry *> Visited; 238 for (const auto *E : DepsGraph) { 239 std::function<void(const SPIRV::DTSortableEntry *)> RecHoistUtil; 240 // NOTE: here we prefer recursive approach over iterative because 241 // we don't expect depchains long enough to cause SO. 242 RecHoistUtil = [MSType, UsePreOrder, &Visited, &Pred, 243 &RecHoistUtil](const SPIRV::DTSortableEntry *E) { 244 if (Visited.count(E) || !Pred(E)) 245 return; 246 Visited.insert(E); 247 248 // Traversing deps graph in post-order allows us to get rid of 249 // register aliases preprocessing. 250 // But pre-order is required for correct processing of function 251 // declaration and arguments processing. 252 if (!UsePreOrder) 253 for (auto *S : E->getDeps()) 254 RecHoistUtil(S); 255 256 Register GlobalReg = Register::index2VirtReg(MAI.getNextID()); 257 bool IsFirst = true; 258 for (auto &U : *E) { 259 const MachineFunction *MF = U.first; 260 Register Reg = U.second; 261 MAI.setRegisterAlias(MF, Reg, GlobalReg); 262 if (!MF->getRegInfo().getUniqueVRegDef(Reg)) 263 continue; 264 collectDefInstr(Reg, MF, &MAI, MSType, IsFirst); 265 IsFirst = false; 266 if (E->getIsGV()) 267 MAI.GlobalVarList.push_back(MF->getRegInfo().getUniqueVRegDef(Reg)); 268 } 269 270 if (UsePreOrder) 271 for (auto *S : E->getDeps()) 272 RecHoistUtil(S); 273 }; 274 RecHoistUtil(E); 275 } 276 } 277 278 // The function initializes global register alias table for types, consts, 279 // global vars and func decls and collects these instruction for output 280 // at module level. Also it collects explicit OpExtension/OpCapability 281 // instructions. 282 void SPIRVModuleAnalysis::processDefInstrs(const Module &M) { 283 std::vector<SPIRV::DTSortableEntry *> DepsGraph; 284 285 GR->buildDepsGraph(DepsGraph, TII, SPVDumpDeps ? MMI : nullptr); 286 287 collectGlobalEntities( 288 DepsGraph, SPIRV::MB_TypeConstVars, 289 [](const SPIRV::DTSortableEntry *E) { return !E->getIsFunc(); }); 290 291 for (auto F = M.begin(), E = M.end(); F != E; ++F) { 292 MachineFunction *MF = MMI->getMachineFunction(*F); 293 if (!MF) 294 continue; 295 // Iterate through and collect OpExtension/OpCapability instructions. 296 for (MachineBasicBlock &MBB : *MF) { 297 for (MachineInstr &MI : MBB) { 298 if (MI.getOpcode() == SPIRV::OpExtension) { 299 // Here, OpExtension just has a single enum operand, not a string. 300 auto Ext = SPIRV::Extension::Extension(MI.getOperand(0).getImm()); 301 MAI.Reqs.addExtension(Ext); 302 MAI.setSkipEmission(&MI); 303 } else if (MI.getOpcode() == SPIRV::OpCapability) { 304 auto Cap = SPIRV::Capability::Capability(MI.getOperand(0).getImm()); 305 MAI.Reqs.addCapability(Cap); 306 MAI.setSkipEmission(&MI); 307 } 308 } 309 } 310 } 311 312 collectGlobalEntities( 313 DepsGraph, SPIRV::MB_ExtFuncDecls, 314 [](const SPIRV::DTSortableEntry *E) { return E->getIsFunc(); }, true); 315 } 316 317 // Look for IDs declared with Import linkage, and map the corresponding function 318 // to the register defining that variable (which will usually be the result of 319 // an OpFunction). This lets us call externally imported functions using 320 // the correct ID registers. 321 void SPIRVModuleAnalysis::collectFuncNames(MachineInstr &MI, 322 const Function *F) { 323 if (MI.getOpcode() == SPIRV::OpDecorate) { 324 // If it's got Import linkage. 325 auto Dec = MI.getOperand(1).getImm(); 326 if (Dec == static_cast<unsigned>(SPIRV::Decoration::LinkageAttributes)) { 327 auto Lnk = MI.getOperand(MI.getNumOperands() - 1).getImm(); 328 if (Lnk == static_cast<unsigned>(SPIRV::LinkageType::Import)) { 329 // Map imported function name to function ID register. 330 const Function *ImportedFunc = 331 F->getParent()->getFunction(getStringImm(MI, 2)); 332 Register Target = MI.getOperand(0).getReg(); 333 MAI.FuncMap[ImportedFunc] = MAI.getRegisterAlias(MI.getMF(), Target); 334 } 335 } 336 } else if (MI.getOpcode() == SPIRV::OpFunction) { 337 // Record all internal OpFunction declarations. 338 Register Reg = MI.defs().begin()->getReg(); 339 Register GlobalReg = MAI.getRegisterAlias(MI.getMF(), Reg); 340 assert(GlobalReg.isValid()); 341 MAI.FuncMap[F] = GlobalReg; 342 } 343 } 344 345 // References to a function via function pointers generate virtual 346 // registers without a definition. We are able to resolve this 347 // reference using Globar Register info into an OpFunction instruction 348 // and replace dummy operands by the corresponding global register references. 349 void SPIRVModuleAnalysis::collectFuncPtrs() { 350 for (auto &MI : MAI.MS[SPIRV::MB_TypeConstVars]) 351 if (MI->getOpcode() == SPIRV::OpConstantFunctionPointerINTEL) 352 collectFuncPtrs(MI); 353 } 354 355 void SPIRVModuleAnalysis::collectFuncPtrs(MachineInstr *MI) { 356 const MachineOperand *FunUse = &MI->getOperand(2); 357 if (const MachineOperand *FunDef = GR->getFunctionDefinitionByUse(FunUse)) { 358 const MachineInstr *FunDefMI = FunDef->getParent(); 359 assert(FunDefMI->getOpcode() == SPIRV::OpFunction && 360 "Constant function pointer must refer to function definition"); 361 Register FunDefReg = FunDef->getReg(); 362 Register GlobalFunDefReg = 363 MAI.getRegisterAlias(FunDefMI->getMF(), FunDefReg); 364 assert(GlobalFunDefReg.isValid() && 365 "Function definition must refer to a global register"); 366 Register FunPtrReg = FunUse->getReg(); 367 MAI.setRegisterAlias(MI->getMF(), FunPtrReg, GlobalFunDefReg); 368 } 369 } 370 371 using InstrSignature = SmallVector<size_t>; 372 using InstrTraces = std::set<InstrSignature>; 373 374 // Returns a representation of an instruction as a vector of MachineOperand 375 // hash values, see llvm::hash_value(const MachineOperand &MO) for details. 376 // This creates a signature of the instruction with the same content 377 // that MachineOperand::isIdenticalTo uses for comparison. 378 static InstrSignature instrToSignature(MachineInstr &MI, 379 SPIRV::ModuleAnalysisInfo &MAI) { 380 InstrSignature Signature; 381 for (unsigned i = 0; i < MI.getNumOperands(); ++i) { 382 const MachineOperand &MO = MI.getOperand(i); 383 size_t h; 384 if (MO.isReg()) { 385 Register RegAlias = MAI.getRegisterAlias(MI.getMF(), MO.getReg()); 386 // mimic llvm::hash_value(const MachineOperand &MO) 387 h = hash_combine(MO.getType(), (unsigned)RegAlias, MO.getSubReg(), 388 MO.isDef()); 389 } else { 390 h = hash_value(MO); 391 } 392 Signature.push_back(h); 393 } 394 return Signature; 395 } 396 397 // Collect the given instruction in the specified MS. We assume global register 398 // numbering has already occurred by this point. We can directly compare reg 399 // arguments when detecting duplicates. 400 static void collectOtherInstr(MachineInstr &MI, SPIRV::ModuleAnalysisInfo &MAI, 401 SPIRV::ModuleSectionType MSType, InstrTraces &IS, 402 bool Append = true) { 403 MAI.setSkipEmission(&MI); 404 InstrSignature MISign = instrToSignature(MI, MAI); 405 auto FoundMI = IS.insert(MISign); 406 if (!FoundMI.second) 407 return; // insert failed, so we found a duplicate; don't add it to MAI.MS 408 // No duplicates, so add it. 409 if (Append) 410 MAI.MS[MSType].push_back(&MI); 411 else 412 MAI.MS[MSType].insert(MAI.MS[MSType].begin(), &MI); 413 } 414 415 // Some global instructions make reference to function-local ID regs, so cannot 416 // be correctly collected until these registers are globally numbered. 417 void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) { 418 InstrTraces IS; 419 for (auto F = M.begin(), E = M.end(); F != E; ++F) { 420 if ((*F).isDeclaration()) 421 continue; 422 MachineFunction *MF = MMI->getMachineFunction(*F); 423 assert(MF); 424 for (MachineBasicBlock &MBB : *MF) 425 for (MachineInstr &MI : MBB) { 426 if (MAI.getSkipEmission(&MI)) 427 continue; 428 const unsigned OpCode = MI.getOpcode(); 429 if (OpCode == SPIRV::OpString) { 430 collectOtherInstr(MI, MAI, SPIRV::MB_DebugStrings, IS); 431 } else if (OpCode == SPIRV::OpExtInst && MI.getOperand(2).isImm() && 432 MI.getOperand(2).getImm() == 433 SPIRV::InstructionSet:: 434 NonSemantic_Shader_DebugInfo_100) { 435 MachineOperand Ins = MI.getOperand(3); 436 namespace NS = SPIRV::NonSemanticExtInst; 437 static constexpr int64_t GlobalNonSemanticDITy[] = { 438 NS::DebugSource, NS::DebugCompilationUnit, NS::DebugInfoNone, 439 NS::DebugTypeBasic, NS::DebugTypePointer}; 440 bool IsGlobalDI = false; 441 for (unsigned Idx = 0; Idx < std::size(GlobalNonSemanticDITy); ++Idx) 442 IsGlobalDI |= Ins.getImm() == GlobalNonSemanticDITy[Idx]; 443 if (IsGlobalDI) 444 collectOtherInstr(MI, MAI, SPIRV::MB_NonSemanticGlobalDI, IS); 445 } else if (OpCode == SPIRV::OpName || OpCode == SPIRV::OpMemberName) { 446 collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames, IS); 447 } else if (OpCode == SPIRV::OpEntryPoint) { 448 collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints, IS); 449 } else if (TII->isDecorationInstr(MI)) { 450 collectOtherInstr(MI, MAI, SPIRV::MB_Annotations, IS); 451 collectFuncNames(MI, &*F); 452 } else if (TII->isConstantInstr(MI)) { 453 // Now OpSpecConstant*s are not in DT, 454 // but they need to be collected anyway. 455 collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS); 456 } else if (OpCode == SPIRV::OpFunction) { 457 collectFuncNames(MI, &*F); 458 } else if (OpCode == SPIRV::OpTypeForwardPointer) { 459 collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS, false); 460 } 461 } 462 } 463 } 464 465 // Number registers in all functions globally from 0 onwards and store 466 // the result in global register alias table. Some registers are already 467 // numbered in collectGlobalEntities. 468 void SPIRVModuleAnalysis::numberRegistersGlobally(const Module &M) { 469 for (auto F = M.begin(), E = M.end(); F != E; ++F) { 470 if ((*F).isDeclaration()) 471 continue; 472 MachineFunction *MF = MMI->getMachineFunction(*F); 473 assert(MF); 474 for (MachineBasicBlock &MBB : *MF) { 475 for (MachineInstr &MI : MBB) { 476 for (MachineOperand &Op : MI.operands()) { 477 if (!Op.isReg()) 478 continue; 479 Register Reg = Op.getReg(); 480 if (MAI.hasRegisterAlias(MF, Reg)) 481 continue; 482 Register NewReg = Register::index2VirtReg(MAI.getNextID()); 483 MAI.setRegisterAlias(MF, Reg, NewReg); 484 } 485 if (MI.getOpcode() != SPIRV::OpExtInst) 486 continue; 487 auto Set = MI.getOperand(2).getImm(); 488 if (!MAI.ExtInstSetMap.contains(Set)) 489 MAI.ExtInstSetMap[Set] = Register::index2VirtReg(MAI.getNextID()); 490 } 491 } 492 } 493 } 494 495 // RequirementHandler implementations. 496 void SPIRV::RequirementHandler::getAndAddRequirements( 497 SPIRV::OperandCategory::OperandCategory Category, uint32_t i, 498 const SPIRVSubtarget &ST) { 499 addRequirements(getSymbolicOperandRequirements(Category, i, ST, *this)); 500 } 501 502 void SPIRV::RequirementHandler::recursiveAddCapabilities( 503 const CapabilityList &ToPrune) { 504 for (const auto &Cap : ToPrune) { 505 AllCaps.insert(Cap); 506 CapabilityList ImplicitDecls = 507 getSymbolicOperandCapabilities(OperandCategory::CapabilityOperand, Cap); 508 recursiveAddCapabilities(ImplicitDecls); 509 } 510 } 511 512 void SPIRV::RequirementHandler::addCapabilities(const CapabilityList &ToAdd) { 513 for (const auto &Cap : ToAdd) { 514 bool IsNewlyInserted = AllCaps.insert(Cap).second; 515 if (!IsNewlyInserted) // Don't re-add if it's already been declared. 516 continue; 517 CapabilityList ImplicitDecls = 518 getSymbolicOperandCapabilities(OperandCategory::CapabilityOperand, Cap); 519 recursiveAddCapabilities(ImplicitDecls); 520 MinimalCaps.push_back(Cap); 521 } 522 } 523 524 void SPIRV::RequirementHandler::addRequirements( 525 const SPIRV::Requirements &Req) { 526 if (!Req.IsSatisfiable) 527 report_fatal_error("Adding SPIR-V requirements this target can't satisfy."); 528 529 if (Req.Cap.has_value()) 530 addCapabilities({Req.Cap.value()}); 531 532 addExtensions(Req.Exts); 533 534 if (!Req.MinVer.empty()) { 535 if (!MaxVersion.empty() && Req.MinVer > MaxVersion) { 536 LLVM_DEBUG(dbgs() << "Conflicting version requirements: >= " << Req.MinVer 537 << " and <= " << MaxVersion << "\n"); 538 report_fatal_error("Adding SPIR-V requirements that can't be satisfied."); 539 } 540 541 if (MinVersion.empty() || Req.MinVer > MinVersion) 542 MinVersion = Req.MinVer; 543 } 544 545 if (!Req.MaxVer.empty()) { 546 if (!MinVersion.empty() && Req.MaxVer < MinVersion) { 547 LLVM_DEBUG(dbgs() << "Conflicting version requirements: <= " << Req.MaxVer 548 << " and >= " << MinVersion << "\n"); 549 report_fatal_error("Adding SPIR-V requirements that can't be satisfied."); 550 } 551 552 if (MaxVersion.empty() || Req.MaxVer < MaxVersion) 553 MaxVersion = Req.MaxVer; 554 } 555 } 556 557 void SPIRV::RequirementHandler::checkSatisfiable( 558 const SPIRVSubtarget &ST) const { 559 // Report as many errors as possible before aborting the compilation. 560 bool IsSatisfiable = true; 561 auto TargetVer = ST.getSPIRVVersion(); 562 563 if (!MaxVersion.empty() && !TargetVer.empty() && MaxVersion < TargetVer) { 564 LLVM_DEBUG( 565 dbgs() << "Target SPIR-V version too high for required features\n" 566 << "Required max version: " << MaxVersion << " target version " 567 << TargetVer << "\n"); 568 IsSatisfiable = false; 569 } 570 571 if (!MinVersion.empty() && !TargetVer.empty() && MinVersion > TargetVer) { 572 LLVM_DEBUG(dbgs() << "Target SPIR-V version too low for required features\n" 573 << "Required min version: " << MinVersion 574 << " target version " << TargetVer << "\n"); 575 IsSatisfiable = false; 576 } 577 578 if (!MinVersion.empty() && !MaxVersion.empty() && MinVersion > MaxVersion) { 579 LLVM_DEBUG( 580 dbgs() 581 << "Version is too low for some features and too high for others.\n" 582 << "Required SPIR-V min version: " << MinVersion 583 << " required SPIR-V max version " << MaxVersion << "\n"); 584 IsSatisfiable = false; 585 } 586 587 for (auto Cap : MinimalCaps) { 588 if (AvailableCaps.contains(Cap)) 589 continue; 590 LLVM_DEBUG(dbgs() << "Capability not supported: " 591 << getSymbolicOperandMnemonic( 592 OperandCategory::CapabilityOperand, Cap) 593 << "\n"); 594 IsSatisfiable = false; 595 } 596 597 for (auto Ext : AllExtensions) { 598 if (ST.canUseExtension(Ext)) 599 continue; 600 LLVM_DEBUG(dbgs() << "Extension not supported: " 601 << getSymbolicOperandMnemonic( 602 OperandCategory::ExtensionOperand, Ext) 603 << "\n"); 604 IsSatisfiable = false; 605 } 606 607 if (!IsSatisfiable) 608 report_fatal_error("Unable to meet SPIR-V requirements for this target."); 609 } 610 611 // Add the given capabilities and all their implicitly defined capabilities too. 612 void SPIRV::RequirementHandler::addAvailableCaps(const CapabilityList &ToAdd) { 613 for (const auto Cap : ToAdd) 614 if (AvailableCaps.insert(Cap).second) 615 addAvailableCaps(getSymbolicOperandCapabilities( 616 SPIRV::OperandCategory::CapabilityOperand, Cap)); 617 } 618 619 void SPIRV::RequirementHandler::removeCapabilityIf( 620 const Capability::Capability ToRemove, 621 const Capability::Capability IfPresent) { 622 if (AllCaps.contains(IfPresent)) 623 AllCaps.erase(ToRemove); 624 } 625 626 namespace llvm { 627 namespace SPIRV { 628 void RequirementHandler::initAvailableCapabilities(const SPIRVSubtarget &ST) { 629 // Provided by both all supported Vulkan versions and OpenCl. 630 addAvailableCaps({Capability::Shader, Capability::Linkage, Capability::Int8, 631 Capability::Int16}); 632 633 if (ST.isAtLeastSPIRVVer(VersionTuple(1, 6))) 634 addAvailableCaps({Capability::DotProduct, Capability::DotProductInputAll, 635 Capability::DotProductInput4x8Bit, 636 Capability::DotProductInput4x8BitPacked, 637 Capability::DemoteToHelperInvocation}); 638 639 // Add capabilities enabled by extensions. 640 for (auto Extension : ST.getAllAvailableExtensions()) { 641 CapabilityList EnabledCapabilities = 642 getCapabilitiesEnabledByExtension(Extension); 643 addAvailableCaps(EnabledCapabilities); 644 } 645 646 if (ST.isOpenCLEnv()) { 647 initAvailableCapabilitiesForOpenCL(ST); 648 return; 649 } 650 651 if (ST.isVulkanEnv()) { 652 initAvailableCapabilitiesForVulkan(ST); 653 return; 654 } 655 656 report_fatal_error("Unimplemented environment for SPIR-V generation."); 657 } 658 659 void RequirementHandler::initAvailableCapabilitiesForOpenCL( 660 const SPIRVSubtarget &ST) { 661 // Add the min requirements for different OpenCL and SPIR-V versions. 662 addAvailableCaps({Capability::Addresses, Capability::Float16Buffer, 663 Capability::Kernel, Capability::Vector16, 664 Capability::Groups, Capability::GenericPointer, 665 Capability::StorageImageReadWithoutFormat}); 666 if (ST.hasOpenCLFullProfile()) 667 addAvailableCaps({Capability::Int64, Capability::Int64Atomics}); 668 if (ST.hasOpenCLImageSupport()) { 669 addAvailableCaps({Capability::ImageBasic, Capability::LiteralSampler, 670 Capability::Image1D, Capability::SampledBuffer, 671 Capability::ImageBuffer}); 672 if (ST.isAtLeastOpenCLVer(VersionTuple(2, 0))) 673 addAvailableCaps({Capability::ImageReadWrite}); 674 } 675 if (ST.isAtLeastSPIRVVer(VersionTuple(1, 1)) && 676 ST.isAtLeastOpenCLVer(VersionTuple(2, 2))) 677 addAvailableCaps({Capability::SubgroupDispatch, Capability::PipeStorage}); 678 if (ST.isAtLeastSPIRVVer(VersionTuple(1, 3))) 679 addAvailableCaps({Capability::GroupNonUniform, 680 Capability::GroupNonUniformVote, 681 Capability::GroupNonUniformArithmetic, 682 Capability::GroupNonUniformBallot, 683 Capability::GroupNonUniformClustered, 684 Capability::GroupNonUniformShuffle, 685 Capability::GroupNonUniformShuffleRelative}); 686 if (ST.isAtLeastSPIRVVer(VersionTuple(1, 4))) 687 addAvailableCaps({Capability::DenormPreserve, Capability::DenormFlushToZero, 688 Capability::SignedZeroInfNanPreserve, 689 Capability::RoundingModeRTE, 690 Capability::RoundingModeRTZ}); 691 // TODO: verify if this needs some checks. 692 addAvailableCaps({Capability::Float16, Capability::Float64}); 693 694 // TODO: add OpenCL extensions. 695 } 696 697 void RequirementHandler::initAvailableCapabilitiesForVulkan( 698 const SPIRVSubtarget &ST) { 699 700 // Core in Vulkan 1.1 and earlier. 701 addAvailableCaps({Capability::Int64, Capability::Float16, Capability::Float64, 702 Capability::GroupNonUniform, Capability::Image1D, 703 Capability::SampledBuffer, Capability::ImageBuffer, 704 Capability::UniformBufferArrayDynamicIndexing, 705 Capability::SampledImageArrayDynamicIndexing, 706 Capability::StorageBufferArrayDynamicIndexing, 707 Capability::StorageImageArrayDynamicIndexing}); 708 709 // Became core in Vulkan 1.2 710 if (ST.isAtLeastSPIRVVer(VersionTuple(1, 5))) { 711 addAvailableCaps( 712 {Capability::ShaderNonUniformEXT, Capability::RuntimeDescriptorArrayEXT, 713 Capability::InputAttachmentArrayDynamicIndexingEXT, 714 Capability::UniformTexelBufferArrayDynamicIndexingEXT, 715 Capability::StorageTexelBufferArrayDynamicIndexingEXT, 716 Capability::UniformBufferArrayNonUniformIndexingEXT, 717 Capability::SampledImageArrayNonUniformIndexingEXT, 718 Capability::StorageBufferArrayNonUniformIndexingEXT, 719 Capability::StorageImageArrayNonUniformIndexingEXT, 720 Capability::InputAttachmentArrayNonUniformIndexingEXT, 721 Capability::UniformTexelBufferArrayNonUniformIndexingEXT, 722 Capability::StorageTexelBufferArrayNonUniformIndexingEXT}); 723 } 724 725 // Became core in Vulkan 1.3 726 if (ST.isAtLeastSPIRVVer(VersionTuple(1, 6))) 727 addAvailableCaps({Capability::StorageImageReadWithoutFormat}); 728 } 729 730 } // namespace SPIRV 731 } // namespace llvm 732 733 // Add the required capabilities from a decoration instruction (including 734 // BuiltIns). 735 static void addOpDecorateReqs(const MachineInstr &MI, unsigned DecIndex, 736 SPIRV::RequirementHandler &Reqs, 737 const SPIRVSubtarget &ST) { 738 int64_t DecOp = MI.getOperand(DecIndex).getImm(); 739 auto Dec = static_cast<SPIRV::Decoration::Decoration>(DecOp); 740 Reqs.addRequirements(getSymbolicOperandRequirements( 741 SPIRV::OperandCategory::DecorationOperand, Dec, ST, Reqs)); 742 743 if (Dec == SPIRV::Decoration::BuiltIn) { 744 int64_t BuiltInOp = MI.getOperand(DecIndex + 1).getImm(); 745 auto BuiltIn = static_cast<SPIRV::BuiltIn::BuiltIn>(BuiltInOp); 746 Reqs.addRequirements(getSymbolicOperandRequirements( 747 SPIRV::OperandCategory::BuiltInOperand, BuiltIn, ST, Reqs)); 748 } else if (Dec == SPIRV::Decoration::LinkageAttributes) { 749 int64_t LinkageOp = MI.getOperand(MI.getNumOperands() - 1).getImm(); 750 SPIRV::LinkageType::LinkageType LnkType = 751 static_cast<SPIRV::LinkageType::LinkageType>(LinkageOp); 752 if (LnkType == SPIRV::LinkageType::LinkOnceODR) 753 Reqs.addExtension(SPIRV::Extension::SPV_KHR_linkonce_odr); 754 } else if (Dec == SPIRV::Decoration::CacheControlLoadINTEL || 755 Dec == SPIRV::Decoration::CacheControlStoreINTEL) { 756 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_cache_controls); 757 } else if (Dec == SPIRV::Decoration::HostAccessINTEL) { 758 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_global_variable_host_access); 759 } else if (Dec == SPIRV::Decoration::InitModeINTEL || 760 Dec == SPIRV::Decoration::ImplementInRegisterMapINTEL) { 761 Reqs.addExtension( 762 SPIRV::Extension::SPV_INTEL_global_variable_fpga_decorations); 763 } else if (Dec == SPIRV::Decoration::NonUniformEXT) { 764 Reqs.addRequirements(SPIRV::Capability::ShaderNonUniformEXT); 765 } 766 } 767 768 // Add requirements for image handling. 769 static void addOpTypeImageReqs(const MachineInstr &MI, 770 SPIRV::RequirementHandler &Reqs, 771 const SPIRVSubtarget &ST) { 772 assert(MI.getNumOperands() >= 8 && "Insufficient operands for OpTypeImage"); 773 // The operand indices used here are based on the OpTypeImage layout, which 774 // the MachineInstr follows as well. 775 int64_t ImgFormatOp = MI.getOperand(7).getImm(); 776 auto ImgFormat = static_cast<SPIRV::ImageFormat::ImageFormat>(ImgFormatOp); 777 Reqs.getAndAddRequirements(SPIRV::OperandCategory::ImageFormatOperand, 778 ImgFormat, ST); 779 780 bool IsArrayed = MI.getOperand(4).getImm() == 1; 781 bool IsMultisampled = MI.getOperand(5).getImm() == 1; 782 bool NoSampler = MI.getOperand(6).getImm() == 2; 783 // Add dimension requirements. 784 assert(MI.getOperand(2).isImm()); 785 switch (MI.getOperand(2).getImm()) { 786 case SPIRV::Dim::DIM_1D: 787 Reqs.addRequirements(NoSampler ? SPIRV::Capability::Image1D 788 : SPIRV::Capability::Sampled1D); 789 break; 790 case SPIRV::Dim::DIM_2D: 791 if (IsMultisampled && NoSampler) 792 Reqs.addRequirements(SPIRV::Capability::ImageMSArray); 793 break; 794 case SPIRV::Dim::DIM_Cube: 795 Reqs.addRequirements(SPIRV::Capability::Shader); 796 if (IsArrayed) 797 Reqs.addRequirements(NoSampler ? SPIRV::Capability::ImageCubeArray 798 : SPIRV::Capability::SampledCubeArray); 799 break; 800 case SPIRV::Dim::DIM_Rect: 801 Reqs.addRequirements(NoSampler ? SPIRV::Capability::ImageRect 802 : SPIRV::Capability::SampledRect); 803 break; 804 case SPIRV::Dim::DIM_Buffer: 805 Reqs.addRequirements(NoSampler ? SPIRV::Capability::ImageBuffer 806 : SPIRV::Capability::SampledBuffer); 807 break; 808 case SPIRV::Dim::DIM_SubpassData: 809 Reqs.addRequirements(SPIRV::Capability::InputAttachment); 810 break; 811 } 812 813 // Has optional access qualifier. 814 if (ST.isOpenCLEnv()) { 815 if (MI.getNumOperands() > 8 && 816 MI.getOperand(8).getImm() == SPIRV::AccessQualifier::ReadWrite) 817 Reqs.addRequirements(SPIRV::Capability::ImageReadWrite); 818 else 819 Reqs.addRequirements(SPIRV::Capability::ImageBasic); 820 } 821 } 822 823 // Add requirements for handling atomic float instructions 824 #define ATOM_FLT_REQ_EXT_MSG(ExtName) \ 825 "The atomic float instruction requires the following SPIR-V " \ 826 "extension: SPV_EXT_shader_atomic_float" ExtName 827 static void AddAtomicFloatRequirements(const MachineInstr &MI, 828 SPIRV::RequirementHandler &Reqs, 829 const SPIRVSubtarget &ST) { 830 assert(MI.getOperand(1).isReg() && 831 "Expect register operand in atomic float instruction"); 832 Register TypeReg = MI.getOperand(1).getReg(); 833 SPIRVType *TypeDef = MI.getMF()->getRegInfo().getVRegDef(TypeReg); 834 if (TypeDef->getOpcode() != SPIRV::OpTypeFloat) 835 report_fatal_error("Result type of an atomic float instruction must be a " 836 "floating-point type scalar"); 837 838 unsigned BitWidth = TypeDef->getOperand(1).getImm(); 839 unsigned Op = MI.getOpcode(); 840 if (Op == SPIRV::OpAtomicFAddEXT) { 841 if (!ST.canUseExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float_add)) 842 report_fatal_error(ATOM_FLT_REQ_EXT_MSG("_add"), false); 843 Reqs.addExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float_add); 844 switch (BitWidth) { 845 case 16: 846 if (!ST.canUseExtension( 847 SPIRV::Extension::SPV_EXT_shader_atomic_float16_add)) 848 report_fatal_error(ATOM_FLT_REQ_EXT_MSG("16_add"), false); 849 Reqs.addExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float16_add); 850 Reqs.addCapability(SPIRV::Capability::AtomicFloat16AddEXT); 851 break; 852 case 32: 853 Reqs.addCapability(SPIRV::Capability::AtomicFloat32AddEXT); 854 break; 855 case 64: 856 Reqs.addCapability(SPIRV::Capability::AtomicFloat64AddEXT); 857 break; 858 default: 859 report_fatal_error( 860 "Unexpected floating-point type width in atomic float instruction"); 861 } 862 } else { 863 if (!ST.canUseExtension( 864 SPIRV::Extension::SPV_EXT_shader_atomic_float_min_max)) 865 report_fatal_error(ATOM_FLT_REQ_EXT_MSG("_min_max"), false); 866 Reqs.addExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float_min_max); 867 switch (BitWidth) { 868 case 16: 869 Reqs.addCapability(SPIRV::Capability::AtomicFloat16MinMaxEXT); 870 break; 871 case 32: 872 Reqs.addCapability(SPIRV::Capability::AtomicFloat32MinMaxEXT); 873 break; 874 case 64: 875 Reqs.addCapability(SPIRV::Capability::AtomicFloat64MinMaxEXT); 876 break; 877 default: 878 report_fatal_error( 879 "Unexpected floating-point type width in atomic float instruction"); 880 } 881 } 882 } 883 884 bool isUniformTexelBuffer(MachineInstr *ImageInst) { 885 if (ImageInst->getOpcode() != SPIRV::OpTypeImage) 886 return false; 887 uint32_t Dim = ImageInst->getOperand(2).getImm(); 888 uint32_t Sampled = ImageInst->getOperand(6).getImm(); 889 return Dim == SPIRV::Dim::DIM_Buffer && Sampled == 1; 890 } 891 892 bool isStorageTexelBuffer(MachineInstr *ImageInst) { 893 if (ImageInst->getOpcode() != SPIRV::OpTypeImage) 894 return false; 895 uint32_t Dim = ImageInst->getOperand(2).getImm(); 896 uint32_t Sampled = ImageInst->getOperand(6).getImm(); 897 return Dim == SPIRV::Dim::DIM_Buffer && Sampled == 2; 898 } 899 900 bool isSampledImage(MachineInstr *ImageInst) { 901 if (ImageInst->getOpcode() != SPIRV::OpTypeImage) 902 return false; 903 uint32_t Dim = ImageInst->getOperand(2).getImm(); 904 uint32_t Sampled = ImageInst->getOperand(6).getImm(); 905 return Dim != SPIRV::Dim::DIM_Buffer && Sampled == 1; 906 } 907 908 bool isInputAttachment(MachineInstr *ImageInst) { 909 if (ImageInst->getOpcode() != SPIRV::OpTypeImage) 910 return false; 911 uint32_t Dim = ImageInst->getOperand(2).getImm(); 912 uint32_t Sampled = ImageInst->getOperand(6).getImm(); 913 return Dim == SPIRV::Dim::DIM_SubpassData && Sampled == 2; 914 } 915 916 bool isStorageImage(MachineInstr *ImageInst) { 917 if (ImageInst->getOpcode() != SPIRV::OpTypeImage) 918 return false; 919 uint32_t Dim = ImageInst->getOperand(2).getImm(); 920 uint32_t Sampled = ImageInst->getOperand(6).getImm(); 921 return Dim != SPIRV::Dim::DIM_Buffer && Sampled == 2; 922 } 923 924 bool isCombinedImageSampler(MachineInstr *SampledImageInst) { 925 if (SampledImageInst->getOpcode() != SPIRV::OpTypeSampledImage) 926 return false; 927 928 const MachineRegisterInfo &MRI = SampledImageInst->getMF()->getRegInfo(); 929 Register ImageReg = SampledImageInst->getOperand(1).getReg(); 930 auto *ImageInst = MRI.getUniqueVRegDef(ImageReg); 931 return isSampledImage(ImageInst); 932 } 933 934 bool hasNonUniformDecoration(Register Reg, const MachineRegisterInfo &MRI) { 935 for (const auto &MI : MRI.reg_instructions(Reg)) { 936 if (MI.getOpcode() != SPIRV::OpDecorate) 937 continue; 938 939 uint32_t Dec = MI.getOperand(1).getImm(); 940 if (Dec == SPIRV::Decoration::NonUniformEXT) 941 return true; 942 } 943 return false; 944 } 945 946 void addOpAccessChainReqs(const MachineInstr &Instr, 947 SPIRV::RequirementHandler &Handler, 948 const SPIRVSubtarget &Subtarget) { 949 const MachineRegisterInfo &MRI = Instr.getMF()->getRegInfo(); 950 // Get the result type. If it is an image type, then the shader uses 951 // descriptor indexing. The appropriate capabilities will be added based 952 // on the specifics of the image. 953 Register ResTypeReg = Instr.getOperand(1).getReg(); 954 MachineInstr *ResTypeInst = MRI.getUniqueVRegDef(ResTypeReg); 955 956 assert(ResTypeInst->getOpcode() == SPIRV::OpTypePointer); 957 uint32_t StorageClass = ResTypeInst->getOperand(1).getImm(); 958 if (StorageClass != SPIRV::StorageClass::StorageClass::UniformConstant && 959 StorageClass != SPIRV::StorageClass::StorageClass::Uniform && 960 StorageClass != SPIRV::StorageClass::StorageClass::StorageBuffer) { 961 return; 962 } 963 964 Register PointeeTypeReg = ResTypeInst->getOperand(2).getReg(); 965 MachineInstr *PointeeType = MRI.getUniqueVRegDef(PointeeTypeReg); 966 if (PointeeType->getOpcode() != SPIRV::OpTypeImage && 967 PointeeType->getOpcode() != SPIRV::OpTypeSampledImage && 968 PointeeType->getOpcode() != SPIRV::OpTypeSampler) { 969 return; 970 } 971 972 bool IsNonUniform = 973 hasNonUniformDecoration(Instr.getOperand(0).getReg(), MRI); 974 if (isUniformTexelBuffer(PointeeType)) { 975 if (IsNonUniform) 976 Handler.addRequirements( 977 SPIRV::Capability::UniformTexelBufferArrayNonUniformIndexingEXT); 978 else 979 Handler.addRequirements( 980 SPIRV::Capability::UniformTexelBufferArrayDynamicIndexingEXT); 981 } else if (isInputAttachment(PointeeType)) { 982 if (IsNonUniform) 983 Handler.addRequirements( 984 SPIRV::Capability::InputAttachmentArrayNonUniformIndexingEXT); 985 else 986 Handler.addRequirements( 987 SPIRV::Capability::InputAttachmentArrayDynamicIndexingEXT); 988 } else if (isStorageTexelBuffer(PointeeType)) { 989 if (IsNonUniform) 990 Handler.addRequirements( 991 SPIRV::Capability::StorageTexelBufferArrayNonUniformIndexingEXT); 992 else 993 Handler.addRequirements( 994 SPIRV::Capability::StorageTexelBufferArrayDynamicIndexingEXT); 995 } else if (isSampledImage(PointeeType) || 996 isCombinedImageSampler(PointeeType) || 997 PointeeType->getOpcode() == SPIRV::OpTypeSampler) { 998 if (IsNonUniform) 999 Handler.addRequirements( 1000 SPIRV::Capability::SampledImageArrayNonUniformIndexingEXT); 1001 else 1002 Handler.addRequirements( 1003 SPIRV::Capability::SampledImageArrayDynamicIndexing); 1004 } else if (isStorageImage(PointeeType)) { 1005 if (IsNonUniform) 1006 Handler.addRequirements( 1007 SPIRV::Capability::StorageImageArrayNonUniformIndexingEXT); 1008 else 1009 Handler.addRequirements( 1010 SPIRV::Capability::StorageImageArrayDynamicIndexing); 1011 } 1012 } 1013 1014 static bool isImageTypeWithUnknownFormat(SPIRVType *TypeInst) { 1015 if (TypeInst->getOpcode() != SPIRV::OpTypeImage) 1016 return false; 1017 assert(TypeInst->getOperand(7).isImm() && "The image format must be an imm."); 1018 return TypeInst->getOperand(7).getImm() == 0; 1019 } 1020 1021 static void AddDotProductRequirements(const MachineInstr &MI, 1022 SPIRV::RequirementHandler &Reqs, 1023 const SPIRVSubtarget &ST) { 1024 if (ST.canUseExtension(SPIRV::Extension::SPV_KHR_integer_dot_product)) 1025 Reqs.addExtension(SPIRV::Extension::SPV_KHR_integer_dot_product); 1026 Reqs.addCapability(SPIRV::Capability::DotProduct); 1027 1028 const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo(); 1029 const MachineInstr *InstrPtr = &MI; 1030 assert(MI.getOperand(1).isReg() && "Unexpected operand in dot"); 1031 1032 Register TypeReg = InstrPtr->getOperand(1).getReg(); 1033 SPIRVType *TypeDef = MRI.getVRegDef(TypeReg); 1034 if (TypeDef->getOpcode() == SPIRV::OpTypeInt) { 1035 assert(TypeDef->getOperand(1).getImm() == 32); 1036 Reqs.addCapability(SPIRV::Capability::DotProductInput4x8BitPacked); 1037 } else if (TypeDef->getOpcode() == SPIRV::OpTypeVector) { 1038 SPIRVType *ScalarTypeDef = MRI.getVRegDef(TypeDef->getOperand(1).getReg()); 1039 assert(ScalarTypeDef->getOpcode() == SPIRV::OpTypeInt); 1040 auto Capability = ScalarTypeDef->getOperand(1).getImm() == 8 1041 ? SPIRV::Capability::DotProductInput4x8Bit 1042 : SPIRV::Capability::DotProductInputAll; 1043 Reqs.addCapability(Capability); 1044 } 1045 } 1046 1047 void addInstrRequirements(const MachineInstr &MI, 1048 SPIRV::RequirementHandler &Reqs, 1049 const SPIRVSubtarget &ST) { 1050 switch (MI.getOpcode()) { 1051 case SPIRV::OpMemoryModel: { 1052 int64_t Addr = MI.getOperand(0).getImm(); 1053 Reqs.getAndAddRequirements(SPIRV::OperandCategory::AddressingModelOperand, 1054 Addr, ST); 1055 int64_t Mem = MI.getOperand(1).getImm(); 1056 Reqs.getAndAddRequirements(SPIRV::OperandCategory::MemoryModelOperand, Mem, 1057 ST); 1058 break; 1059 } 1060 case SPIRV::OpEntryPoint: { 1061 int64_t Exe = MI.getOperand(0).getImm(); 1062 Reqs.getAndAddRequirements(SPIRV::OperandCategory::ExecutionModelOperand, 1063 Exe, ST); 1064 break; 1065 } 1066 case SPIRV::OpExecutionMode: 1067 case SPIRV::OpExecutionModeId: { 1068 int64_t Exe = MI.getOperand(1).getImm(); 1069 Reqs.getAndAddRequirements(SPIRV::OperandCategory::ExecutionModeOperand, 1070 Exe, ST); 1071 break; 1072 } 1073 case SPIRV::OpTypeMatrix: 1074 Reqs.addCapability(SPIRV::Capability::Matrix); 1075 break; 1076 case SPIRV::OpTypeInt: { 1077 unsigned BitWidth = MI.getOperand(1).getImm(); 1078 if (BitWidth == 64) 1079 Reqs.addCapability(SPIRV::Capability::Int64); 1080 else if (BitWidth == 16) 1081 Reqs.addCapability(SPIRV::Capability::Int16); 1082 else if (BitWidth == 8) 1083 Reqs.addCapability(SPIRV::Capability::Int8); 1084 break; 1085 } 1086 case SPIRV::OpTypeFloat: { 1087 unsigned BitWidth = MI.getOperand(1).getImm(); 1088 if (BitWidth == 64) 1089 Reqs.addCapability(SPIRV::Capability::Float64); 1090 else if (BitWidth == 16) 1091 Reqs.addCapability(SPIRV::Capability::Float16); 1092 break; 1093 } 1094 case SPIRV::OpTypeVector: { 1095 unsigned NumComponents = MI.getOperand(2).getImm(); 1096 if (NumComponents == 8 || NumComponents == 16) 1097 Reqs.addCapability(SPIRV::Capability::Vector16); 1098 break; 1099 } 1100 case SPIRV::OpTypePointer: { 1101 auto SC = MI.getOperand(1).getImm(); 1102 Reqs.getAndAddRequirements(SPIRV::OperandCategory::StorageClassOperand, SC, 1103 ST); 1104 // If it's a type of pointer to float16 targeting OpenCL, add Float16Buffer 1105 // capability. 1106 if (!ST.isOpenCLEnv()) 1107 break; 1108 assert(MI.getOperand(2).isReg()); 1109 const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo(); 1110 SPIRVType *TypeDef = MRI.getVRegDef(MI.getOperand(2).getReg()); 1111 if (TypeDef->getOpcode() == SPIRV::OpTypeFloat && 1112 TypeDef->getOperand(1).getImm() == 16) 1113 Reqs.addCapability(SPIRV::Capability::Float16Buffer); 1114 break; 1115 } 1116 case SPIRV::OpExtInst: { 1117 if (MI.getOperand(2).getImm() == 1118 static_cast<int64_t>( 1119 SPIRV::InstructionSet::NonSemantic_Shader_DebugInfo_100)) { 1120 Reqs.addExtension(SPIRV::Extension::SPV_KHR_non_semantic_info); 1121 } 1122 break; 1123 } 1124 case SPIRV::OpBitReverse: 1125 case SPIRV::OpBitFieldInsert: 1126 case SPIRV::OpBitFieldSExtract: 1127 case SPIRV::OpBitFieldUExtract: 1128 if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions)) { 1129 Reqs.addCapability(SPIRV::Capability::Shader); 1130 break; 1131 } 1132 Reqs.addExtension(SPIRV::Extension::SPV_KHR_bit_instructions); 1133 Reqs.addCapability(SPIRV::Capability::BitInstructions); 1134 break; 1135 case SPIRV::OpTypeRuntimeArray: 1136 Reqs.addCapability(SPIRV::Capability::Shader); 1137 break; 1138 case SPIRV::OpTypeOpaque: 1139 case SPIRV::OpTypeEvent: 1140 Reqs.addCapability(SPIRV::Capability::Kernel); 1141 break; 1142 case SPIRV::OpTypePipe: 1143 case SPIRV::OpTypeReserveId: 1144 Reqs.addCapability(SPIRV::Capability::Pipes); 1145 break; 1146 case SPIRV::OpTypeDeviceEvent: 1147 case SPIRV::OpTypeQueue: 1148 case SPIRV::OpBuildNDRange: 1149 Reqs.addCapability(SPIRV::Capability::DeviceEnqueue); 1150 break; 1151 case SPIRV::OpDecorate: 1152 case SPIRV::OpDecorateId: 1153 case SPIRV::OpDecorateString: 1154 addOpDecorateReqs(MI, 1, Reqs, ST); 1155 break; 1156 case SPIRV::OpMemberDecorate: 1157 case SPIRV::OpMemberDecorateString: 1158 addOpDecorateReqs(MI, 2, Reqs, ST); 1159 break; 1160 case SPIRV::OpInBoundsPtrAccessChain: 1161 Reqs.addCapability(SPIRV::Capability::Addresses); 1162 break; 1163 case SPIRV::OpConstantSampler: 1164 Reqs.addCapability(SPIRV::Capability::LiteralSampler); 1165 break; 1166 case SPIRV::OpInBoundsAccessChain: 1167 case SPIRV::OpAccessChain: 1168 addOpAccessChainReqs(MI, Reqs, ST); 1169 break; 1170 case SPIRV::OpTypeImage: 1171 addOpTypeImageReqs(MI, Reqs, ST); 1172 break; 1173 case SPIRV::OpTypeSampler: 1174 if (!ST.isVulkanEnv()) { 1175 Reqs.addCapability(SPIRV::Capability::ImageBasic); 1176 } 1177 break; 1178 case SPIRV::OpTypeForwardPointer: 1179 // TODO: check if it's OpenCL's kernel. 1180 Reqs.addCapability(SPIRV::Capability::Addresses); 1181 break; 1182 case SPIRV::OpAtomicFlagTestAndSet: 1183 case SPIRV::OpAtomicLoad: 1184 case SPIRV::OpAtomicStore: 1185 case SPIRV::OpAtomicExchange: 1186 case SPIRV::OpAtomicCompareExchange: 1187 case SPIRV::OpAtomicIIncrement: 1188 case SPIRV::OpAtomicIDecrement: 1189 case SPIRV::OpAtomicIAdd: 1190 case SPIRV::OpAtomicISub: 1191 case SPIRV::OpAtomicUMin: 1192 case SPIRV::OpAtomicUMax: 1193 case SPIRV::OpAtomicSMin: 1194 case SPIRV::OpAtomicSMax: 1195 case SPIRV::OpAtomicAnd: 1196 case SPIRV::OpAtomicOr: 1197 case SPIRV::OpAtomicXor: { 1198 const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo(); 1199 const MachineInstr *InstrPtr = &MI; 1200 if (MI.getOpcode() == SPIRV::OpAtomicStore) { 1201 assert(MI.getOperand(3).isReg()); 1202 InstrPtr = MRI.getVRegDef(MI.getOperand(3).getReg()); 1203 assert(InstrPtr && "Unexpected type instruction for OpAtomicStore"); 1204 } 1205 assert(InstrPtr->getOperand(1).isReg() && "Unexpected operand in atomic"); 1206 Register TypeReg = InstrPtr->getOperand(1).getReg(); 1207 SPIRVType *TypeDef = MRI.getVRegDef(TypeReg); 1208 if (TypeDef->getOpcode() == SPIRV::OpTypeInt) { 1209 unsigned BitWidth = TypeDef->getOperand(1).getImm(); 1210 if (BitWidth == 64) 1211 Reqs.addCapability(SPIRV::Capability::Int64Atomics); 1212 } 1213 break; 1214 } 1215 case SPIRV::OpGroupNonUniformIAdd: 1216 case SPIRV::OpGroupNonUniformFAdd: 1217 case SPIRV::OpGroupNonUniformIMul: 1218 case SPIRV::OpGroupNonUniformFMul: 1219 case SPIRV::OpGroupNonUniformSMin: 1220 case SPIRV::OpGroupNonUniformUMin: 1221 case SPIRV::OpGroupNonUniformFMin: 1222 case SPIRV::OpGroupNonUniformSMax: 1223 case SPIRV::OpGroupNonUniformUMax: 1224 case SPIRV::OpGroupNonUniformFMax: 1225 case SPIRV::OpGroupNonUniformBitwiseAnd: 1226 case SPIRV::OpGroupNonUniformBitwiseOr: 1227 case SPIRV::OpGroupNonUniformBitwiseXor: 1228 case SPIRV::OpGroupNonUniformLogicalAnd: 1229 case SPIRV::OpGroupNonUniformLogicalOr: 1230 case SPIRV::OpGroupNonUniformLogicalXor: { 1231 assert(MI.getOperand(3).isImm()); 1232 int64_t GroupOp = MI.getOperand(3).getImm(); 1233 switch (GroupOp) { 1234 case SPIRV::GroupOperation::Reduce: 1235 case SPIRV::GroupOperation::InclusiveScan: 1236 case SPIRV::GroupOperation::ExclusiveScan: 1237 Reqs.addCapability(SPIRV::Capability::Kernel); 1238 Reqs.addCapability(SPIRV::Capability::GroupNonUniformArithmetic); 1239 Reqs.addCapability(SPIRV::Capability::GroupNonUniformBallot); 1240 break; 1241 case SPIRV::GroupOperation::ClusteredReduce: 1242 Reqs.addCapability(SPIRV::Capability::GroupNonUniformClustered); 1243 break; 1244 case SPIRV::GroupOperation::PartitionedReduceNV: 1245 case SPIRV::GroupOperation::PartitionedInclusiveScanNV: 1246 case SPIRV::GroupOperation::PartitionedExclusiveScanNV: 1247 Reqs.addCapability(SPIRV::Capability::GroupNonUniformPartitionedNV); 1248 break; 1249 } 1250 break; 1251 } 1252 case SPIRV::OpGroupNonUniformShuffle: 1253 case SPIRV::OpGroupNonUniformShuffleXor: 1254 Reqs.addCapability(SPIRV::Capability::GroupNonUniformShuffle); 1255 break; 1256 case SPIRV::OpGroupNonUniformShuffleUp: 1257 case SPIRV::OpGroupNonUniformShuffleDown: 1258 Reqs.addCapability(SPIRV::Capability::GroupNonUniformShuffleRelative); 1259 break; 1260 case SPIRV::OpGroupAll: 1261 case SPIRV::OpGroupAny: 1262 case SPIRV::OpGroupBroadcast: 1263 case SPIRV::OpGroupIAdd: 1264 case SPIRV::OpGroupFAdd: 1265 case SPIRV::OpGroupFMin: 1266 case SPIRV::OpGroupUMin: 1267 case SPIRV::OpGroupSMin: 1268 case SPIRV::OpGroupFMax: 1269 case SPIRV::OpGroupUMax: 1270 case SPIRV::OpGroupSMax: 1271 Reqs.addCapability(SPIRV::Capability::Groups); 1272 break; 1273 case SPIRV::OpGroupNonUniformElect: 1274 Reqs.addCapability(SPIRV::Capability::GroupNonUniform); 1275 break; 1276 case SPIRV::OpGroupNonUniformAll: 1277 case SPIRV::OpGroupNonUniformAny: 1278 case SPIRV::OpGroupNonUniformAllEqual: 1279 Reqs.addCapability(SPIRV::Capability::GroupNonUniformVote); 1280 break; 1281 case SPIRV::OpGroupNonUniformBroadcast: 1282 case SPIRV::OpGroupNonUniformBroadcastFirst: 1283 case SPIRV::OpGroupNonUniformBallot: 1284 case SPIRV::OpGroupNonUniformInverseBallot: 1285 case SPIRV::OpGroupNonUniformBallotBitExtract: 1286 case SPIRV::OpGroupNonUniformBallotBitCount: 1287 case SPIRV::OpGroupNonUniformBallotFindLSB: 1288 case SPIRV::OpGroupNonUniformBallotFindMSB: 1289 Reqs.addCapability(SPIRV::Capability::GroupNonUniformBallot); 1290 break; 1291 case SPIRV::OpSubgroupShuffleINTEL: 1292 case SPIRV::OpSubgroupShuffleDownINTEL: 1293 case SPIRV::OpSubgroupShuffleUpINTEL: 1294 case SPIRV::OpSubgroupShuffleXorINTEL: 1295 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) { 1296 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_subgroups); 1297 Reqs.addCapability(SPIRV::Capability::SubgroupShuffleINTEL); 1298 } 1299 break; 1300 case SPIRV::OpSubgroupBlockReadINTEL: 1301 case SPIRV::OpSubgroupBlockWriteINTEL: 1302 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) { 1303 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_subgroups); 1304 Reqs.addCapability(SPIRV::Capability::SubgroupBufferBlockIOINTEL); 1305 } 1306 break; 1307 case SPIRV::OpSubgroupImageBlockReadINTEL: 1308 case SPIRV::OpSubgroupImageBlockWriteINTEL: 1309 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) { 1310 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_subgroups); 1311 Reqs.addCapability(SPIRV::Capability::SubgroupImageBlockIOINTEL); 1312 } 1313 break; 1314 case SPIRV::OpAssumeTrueKHR: 1315 case SPIRV::OpExpectKHR: 1316 if (ST.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) { 1317 Reqs.addExtension(SPIRV::Extension::SPV_KHR_expect_assume); 1318 Reqs.addCapability(SPIRV::Capability::ExpectAssumeKHR); 1319 } 1320 break; 1321 case SPIRV::OpPtrCastToCrossWorkgroupINTEL: 1322 case SPIRV::OpCrossWorkgroupCastToPtrINTEL: 1323 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_usm_storage_classes)) { 1324 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_usm_storage_classes); 1325 Reqs.addCapability(SPIRV::Capability::USMStorageClassesINTEL); 1326 } 1327 break; 1328 case SPIRV::OpConstantFunctionPointerINTEL: 1329 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers)) { 1330 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_function_pointers); 1331 Reqs.addCapability(SPIRV::Capability::FunctionPointersINTEL); 1332 } 1333 break; 1334 case SPIRV::OpGroupNonUniformRotateKHR: 1335 if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_subgroup_rotate)) 1336 report_fatal_error("OpGroupNonUniformRotateKHR instruction requires the " 1337 "following SPIR-V extension: SPV_KHR_subgroup_rotate", 1338 false); 1339 Reqs.addExtension(SPIRV::Extension::SPV_KHR_subgroup_rotate); 1340 Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR); 1341 Reqs.addCapability(SPIRV::Capability::GroupNonUniform); 1342 break; 1343 case SPIRV::OpGroupIMulKHR: 1344 case SPIRV::OpGroupFMulKHR: 1345 case SPIRV::OpGroupBitwiseAndKHR: 1346 case SPIRV::OpGroupBitwiseOrKHR: 1347 case SPIRV::OpGroupBitwiseXorKHR: 1348 case SPIRV::OpGroupLogicalAndKHR: 1349 case SPIRV::OpGroupLogicalOrKHR: 1350 case SPIRV::OpGroupLogicalXorKHR: 1351 if (ST.canUseExtension( 1352 SPIRV::Extension::SPV_KHR_uniform_group_instructions)) { 1353 Reqs.addExtension(SPIRV::Extension::SPV_KHR_uniform_group_instructions); 1354 Reqs.addCapability(SPIRV::Capability::GroupUniformArithmeticKHR); 1355 } 1356 break; 1357 case SPIRV::OpReadClockKHR: 1358 if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_shader_clock)) 1359 report_fatal_error("OpReadClockKHR instruction requires the " 1360 "following SPIR-V extension: SPV_KHR_shader_clock", 1361 false); 1362 Reqs.addExtension(SPIRV::Extension::SPV_KHR_shader_clock); 1363 Reqs.addCapability(SPIRV::Capability::ShaderClockKHR); 1364 break; 1365 case SPIRV::OpFunctionPointerCallINTEL: 1366 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers)) { 1367 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_function_pointers); 1368 Reqs.addCapability(SPIRV::Capability::FunctionPointersINTEL); 1369 } 1370 break; 1371 case SPIRV::OpAtomicFAddEXT: 1372 case SPIRV::OpAtomicFMinEXT: 1373 case SPIRV::OpAtomicFMaxEXT: 1374 AddAtomicFloatRequirements(MI, Reqs, ST); 1375 break; 1376 case SPIRV::OpConvertBF16ToFINTEL: 1377 case SPIRV::OpConvertFToBF16INTEL: 1378 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_bfloat16_conversion)) { 1379 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_bfloat16_conversion); 1380 Reqs.addCapability(SPIRV::Capability::BFloat16ConversionINTEL); 1381 } 1382 break; 1383 case SPIRV::OpVariableLengthArrayINTEL: 1384 case SPIRV::OpSaveMemoryINTEL: 1385 case SPIRV::OpRestoreMemoryINTEL: 1386 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array)) { 1387 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_variable_length_array); 1388 Reqs.addCapability(SPIRV::Capability::VariableLengthArrayINTEL); 1389 } 1390 break; 1391 case SPIRV::OpAsmTargetINTEL: 1392 case SPIRV::OpAsmINTEL: 1393 case SPIRV::OpAsmCallINTEL: 1394 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_inline_assembly)) { 1395 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_inline_assembly); 1396 Reqs.addCapability(SPIRV::Capability::AsmINTEL); 1397 } 1398 break; 1399 case SPIRV::OpTypeCooperativeMatrixKHR: 1400 if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_cooperative_matrix)) 1401 report_fatal_error( 1402 "OpTypeCooperativeMatrixKHR type requires the " 1403 "following SPIR-V extension: SPV_KHR_cooperative_matrix", 1404 false); 1405 Reqs.addExtension(SPIRV::Extension::SPV_KHR_cooperative_matrix); 1406 Reqs.addCapability(SPIRV::Capability::CooperativeMatrixKHR); 1407 break; 1408 case SPIRV::OpArithmeticFenceEXT: 1409 if (!ST.canUseExtension(SPIRV::Extension::SPV_EXT_arithmetic_fence)) 1410 report_fatal_error("OpArithmeticFenceEXT requires the " 1411 "following SPIR-V extension: SPV_EXT_arithmetic_fence", 1412 false); 1413 Reqs.addExtension(SPIRV::Extension::SPV_EXT_arithmetic_fence); 1414 Reqs.addCapability(SPIRV::Capability::ArithmeticFenceEXT); 1415 break; 1416 case SPIRV::OpControlBarrierArriveINTEL: 1417 case SPIRV::OpControlBarrierWaitINTEL: 1418 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_split_barrier)) { 1419 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_split_barrier); 1420 Reqs.addCapability(SPIRV::Capability::SplitBarrierINTEL); 1421 } 1422 break; 1423 case SPIRV::OpKill: { 1424 Reqs.addCapability(SPIRV::Capability::Shader); 1425 } break; 1426 case SPIRV::OpDemoteToHelperInvocation: 1427 Reqs.addCapability(SPIRV::Capability::DemoteToHelperInvocation); 1428 1429 if (ST.canUseExtension( 1430 SPIRV::Extension::SPV_EXT_demote_to_helper_invocation)) { 1431 if (!ST.isAtLeastSPIRVVer(llvm::VersionTuple(1, 6))) 1432 Reqs.addExtension( 1433 SPIRV::Extension::SPV_EXT_demote_to_helper_invocation); 1434 } 1435 break; 1436 case SPIRV::OpSDot: 1437 case SPIRV::OpUDot: 1438 AddDotProductRequirements(MI, Reqs, ST); 1439 break; 1440 case SPIRV::OpImageRead: { 1441 Register ImageReg = MI.getOperand(2).getReg(); 1442 SPIRVType *TypeDef = ST.getSPIRVGlobalRegistry()->getResultType(ImageReg); 1443 if (isImageTypeWithUnknownFormat(TypeDef)) 1444 Reqs.addCapability(SPIRV::Capability::StorageImageReadWithoutFormat); 1445 break; 1446 } 1447 1448 default: 1449 break; 1450 } 1451 1452 // If we require capability Shader, then we can remove the requirement for 1453 // the BitInstructions capability, since Shader is a superset capability 1454 // of BitInstructions. 1455 Reqs.removeCapabilityIf(SPIRV::Capability::BitInstructions, 1456 SPIRV::Capability::Shader); 1457 } 1458 1459 static void collectReqs(const Module &M, SPIRV::ModuleAnalysisInfo &MAI, 1460 MachineModuleInfo *MMI, const SPIRVSubtarget &ST) { 1461 // Collect requirements for existing instructions. 1462 for (auto F = M.begin(), E = M.end(); F != E; ++F) { 1463 MachineFunction *MF = MMI->getMachineFunction(*F); 1464 if (!MF) 1465 continue; 1466 for (const MachineBasicBlock &MBB : *MF) 1467 for (const MachineInstr &MI : MBB) 1468 addInstrRequirements(MI, MAI.Reqs, ST); 1469 } 1470 // Collect requirements for OpExecutionMode instructions. 1471 auto Node = M.getNamedMetadata("spirv.ExecutionMode"); 1472 if (Node) { 1473 // SPV_KHR_float_controls is not available until v1.4 1474 bool RequireFloatControls = false, 1475 VerLower14 = !ST.isAtLeastSPIRVVer(VersionTuple(1, 4)); 1476 for (unsigned i = 0; i < Node->getNumOperands(); i++) { 1477 MDNode *MDN = cast<MDNode>(Node->getOperand(i)); 1478 const MDOperand &MDOp = MDN->getOperand(1); 1479 if (auto *CMeta = dyn_cast<ConstantAsMetadata>(MDOp)) { 1480 Constant *C = CMeta->getValue(); 1481 if (ConstantInt *Const = dyn_cast<ConstantInt>(C)) { 1482 auto EM = Const->getZExtValue(); 1483 MAI.Reqs.getAndAddRequirements( 1484 SPIRV::OperandCategory::ExecutionModeOperand, EM, ST); 1485 // add SPV_KHR_float_controls if the version is too low 1486 switch (EM) { 1487 case SPIRV::ExecutionMode::DenormPreserve: 1488 case SPIRV::ExecutionMode::DenormFlushToZero: 1489 case SPIRV::ExecutionMode::SignedZeroInfNanPreserve: 1490 case SPIRV::ExecutionMode::RoundingModeRTE: 1491 case SPIRV::ExecutionMode::RoundingModeRTZ: 1492 RequireFloatControls = VerLower14; 1493 break; 1494 } 1495 } 1496 } 1497 } 1498 if (RequireFloatControls && 1499 ST.canUseExtension(SPIRV::Extension::SPV_KHR_float_controls)) 1500 MAI.Reqs.addExtension(SPIRV::Extension::SPV_KHR_float_controls); 1501 } 1502 for (auto FI = M.begin(), E = M.end(); FI != E; ++FI) { 1503 const Function &F = *FI; 1504 if (F.isDeclaration()) 1505 continue; 1506 if (F.getMetadata("reqd_work_group_size")) 1507 MAI.Reqs.getAndAddRequirements( 1508 SPIRV::OperandCategory::ExecutionModeOperand, 1509 SPIRV::ExecutionMode::LocalSize, ST); 1510 if (F.getFnAttribute("hlsl.numthreads").isValid()) { 1511 MAI.Reqs.getAndAddRequirements( 1512 SPIRV::OperandCategory::ExecutionModeOperand, 1513 SPIRV::ExecutionMode::LocalSize, ST); 1514 } 1515 if (F.getMetadata("work_group_size_hint")) 1516 MAI.Reqs.getAndAddRequirements( 1517 SPIRV::OperandCategory::ExecutionModeOperand, 1518 SPIRV::ExecutionMode::LocalSizeHint, ST); 1519 if (F.getMetadata("intel_reqd_sub_group_size")) 1520 MAI.Reqs.getAndAddRequirements( 1521 SPIRV::OperandCategory::ExecutionModeOperand, 1522 SPIRV::ExecutionMode::SubgroupSize, ST); 1523 if (F.getMetadata("vec_type_hint")) 1524 MAI.Reqs.getAndAddRequirements( 1525 SPIRV::OperandCategory::ExecutionModeOperand, 1526 SPIRV::ExecutionMode::VecTypeHint, ST); 1527 1528 if (F.hasOptNone() && 1529 ST.canUseExtension(SPIRV::Extension::SPV_INTEL_optnone)) { 1530 // Output OpCapability OptNoneINTEL. 1531 MAI.Reqs.addExtension(SPIRV::Extension::SPV_INTEL_optnone); 1532 MAI.Reqs.addCapability(SPIRV::Capability::OptNoneINTEL); 1533 } 1534 } 1535 } 1536 1537 static unsigned getFastMathFlags(const MachineInstr &I) { 1538 unsigned Flags = SPIRV::FPFastMathMode::None; 1539 if (I.getFlag(MachineInstr::MIFlag::FmNoNans)) 1540 Flags |= SPIRV::FPFastMathMode::NotNaN; 1541 if (I.getFlag(MachineInstr::MIFlag::FmNoInfs)) 1542 Flags |= SPIRV::FPFastMathMode::NotInf; 1543 if (I.getFlag(MachineInstr::MIFlag::FmNsz)) 1544 Flags |= SPIRV::FPFastMathMode::NSZ; 1545 if (I.getFlag(MachineInstr::MIFlag::FmArcp)) 1546 Flags |= SPIRV::FPFastMathMode::AllowRecip; 1547 if (I.getFlag(MachineInstr::MIFlag::FmReassoc)) 1548 Flags |= SPIRV::FPFastMathMode::Fast; 1549 return Flags; 1550 } 1551 1552 static void handleMIFlagDecoration(MachineInstr &I, const SPIRVSubtarget &ST, 1553 const SPIRVInstrInfo &TII, 1554 SPIRV::RequirementHandler &Reqs) { 1555 if (I.getFlag(MachineInstr::MIFlag::NoSWrap) && TII.canUseNSW(I) && 1556 getSymbolicOperandRequirements(SPIRV::OperandCategory::DecorationOperand, 1557 SPIRV::Decoration::NoSignedWrap, ST, Reqs) 1558 .IsSatisfiable) { 1559 buildOpDecorate(I.getOperand(0).getReg(), I, TII, 1560 SPIRV::Decoration::NoSignedWrap, {}); 1561 } 1562 if (I.getFlag(MachineInstr::MIFlag::NoUWrap) && TII.canUseNUW(I) && 1563 getSymbolicOperandRequirements(SPIRV::OperandCategory::DecorationOperand, 1564 SPIRV::Decoration::NoUnsignedWrap, ST, 1565 Reqs) 1566 .IsSatisfiable) { 1567 buildOpDecorate(I.getOperand(0).getReg(), I, TII, 1568 SPIRV::Decoration::NoUnsignedWrap, {}); 1569 } 1570 if (!TII.canUseFastMathFlags(I)) 1571 return; 1572 unsigned FMFlags = getFastMathFlags(I); 1573 if (FMFlags == SPIRV::FPFastMathMode::None) 1574 return; 1575 Register DstReg = I.getOperand(0).getReg(); 1576 buildOpDecorate(DstReg, I, TII, SPIRV::Decoration::FPFastMathMode, {FMFlags}); 1577 } 1578 1579 // Walk all functions and add decorations related to MI flags. 1580 static void addDecorations(const Module &M, const SPIRVInstrInfo &TII, 1581 MachineModuleInfo *MMI, const SPIRVSubtarget &ST, 1582 SPIRV::ModuleAnalysisInfo &MAI) { 1583 for (auto F = M.begin(), E = M.end(); F != E; ++F) { 1584 MachineFunction *MF = MMI->getMachineFunction(*F); 1585 if (!MF) 1586 continue; 1587 for (auto &MBB : *MF) 1588 for (auto &MI : MBB) 1589 handleMIFlagDecoration(MI, ST, TII, MAI.Reqs); 1590 } 1591 } 1592 1593 struct SPIRV::ModuleAnalysisInfo SPIRVModuleAnalysis::MAI; 1594 1595 void SPIRVModuleAnalysis::getAnalysisUsage(AnalysisUsage &AU) const { 1596 AU.addRequired<TargetPassConfig>(); 1597 AU.addRequired<MachineModuleInfoWrapperPass>(); 1598 } 1599 1600 bool SPIRVModuleAnalysis::runOnModule(Module &M) { 1601 SPIRVTargetMachine &TM = 1602 getAnalysis<TargetPassConfig>().getTM<SPIRVTargetMachine>(); 1603 ST = TM.getSubtargetImpl(); 1604 GR = ST->getSPIRVGlobalRegistry(); 1605 TII = ST->getInstrInfo(); 1606 1607 MMI = &getAnalysis<MachineModuleInfoWrapperPass>().getMMI(); 1608 1609 setBaseInfo(M); 1610 1611 addDecorations(M, *TII, MMI, *ST, MAI); 1612 1613 collectReqs(M, MAI, MMI, *ST); 1614 1615 // Process type/const/global var/func decl instructions, number their 1616 // destination registers from 0 to N, collect Extensions and Capabilities. 1617 processDefInstrs(M); 1618 1619 // Number rest of registers from N+1 onwards. 1620 numberRegistersGlobally(M); 1621 1622 // Update references to OpFunction instructions to use Global Registers 1623 if (GR->hasConstFunPtr()) 1624 collectFuncPtrs(); 1625 1626 // Collect OpName, OpEntryPoint, OpDecorate etc, process other instructions. 1627 processOtherInstrs(M); 1628 1629 // If there are no entry points, we need the Linkage capability. 1630 if (MAI.MS[SPIRV::MB_EntryPoints].empty()) 1631 MAI.Reqs.addCapability(SPIRV::Capability::Linkage); 1632 1633 // Set maximum ID used. 1634 GR->setBound(MAI.MaxID); 1635 1636 return false; 1637 } 1638