xref: /llvm-project/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp (revision 62da359ce7a7ae09e6afa96227eb556be54aabb1) 
1 //===- SPIRVModuleAnalysis.cpp - analysis of global instrs & regs - C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The analysis collects instructions that should be output at the module level
10 // and performs the global register numbering.
11 //
12 // The results of this analysis are used in AsmPrinter to rename registers
13 // globally and to output required instructions at the module level.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "SPIRVModuleAnalysis.h"
18 #include "MCTargetDesc/SPIRVBaseInfo.h"
19 #include "MCTargetDesc/SPIRVMCTargetDesc.h"
20 #include "SPIRV.h"
21 #include "SPIRVSubtarget.h"
22 #include "SPIRVTargetMachine.h"
23 #include "SPIRVUtils.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "spirv-module-analysis"
31 
32 static cl::opt<bool>
33     SPVDumpDeps("spv-dump-deps",
34                 cl::desc("Dump MIR with SPIR-V dependencies info"),
35                 cl::Optional, cl::init(false));
36 
37 static cl::list<SPIRV::Capability::Capability>
38     AvoidCapabilities("avoid-spirv-capabilities",
39                       cl::desc("SPIR-V capabilities to avoid if there are "
40                                "other options enabling a feature"),
41                       cl::ZeroOrMore, cl::Hidden,
42                       cl::values(clEnumValN(SPIRV::Capability::Shader, "Shader",
43                                             "SPIR-V Shader capability")));
44 // Use sets instead of cl::list to check "if contains" condition
45 struct AvoidCapabilitiesSet {
46   SmallSet<SPIRV::Capability::Capability, 4> S;
47   AvoidCapabilitiesSet() {
48     for (auto Cap : AvoidCapabilities)
49       S.insert(Cap);
50   }
51 };
52 
53 char llvm::SPIRVModuleAnalysis::ID = 0;
54 
55 namespace llvm {
56 void initializeSPIRVModuleAnalysisPass(PassRegistry &);
57 } // namespace llvm
58 
59 INITIALIZE_PASS(SPIRVModuleAnalysis, DEBUG_TYPE, "SPIRV module analysis", true,
60                 true)
61 
62 // Retrieve an unsigned from an MDNode with a list of them as operands.
63 static unsigned getMetadataUInt(MDNode *MdNode, unsigned OpIndex,
64                                 unsigned DefaultVal = 0) {
65   if (MdNode && OpIndex < MdNode->getNumOperands()) {
66     const auto &Op = MdNode->getOperand(OpIndex);
67     return mdconst::extract<ConstantInt>(Op)->getZExtValue();
68   }
69   return DefaultVal;
70 }
71 
72 static SPIRV::Requirements
73 getSymbolicOperandRequirements(SPIRV::OperandCategory::OperandCategory Category,
74                                unsigned i, const SPIRVSubtarget &ST,
75                                SPIRV::RequirementHandler &Reqs) {
76   static AvoidCapabilitiesSet
77       AvoidCaps; // contains capabilities to avoid if there is another option
78 
79   VersionTuple ReqMinVer = getSymbolicOperandMinVersion(Category, i);
80   VersionTuple ReqMaxVer = getSymbolicOperandMaxVersion(Category, i);
81   VersionTuple SPIRVVersion = ST.getSPIRVVersion();
82   bool MinVerOK = SPIRVVersion.empty() || SPIRVVersion >= ReqMinVer;
83   bool MaxVerOK =
84       ReqMaxVer.empty() || SPIRVVersion.empty() || SPIRVVersion <= ReqMaxVer;
85   CapabilityList ReqCaps = getSymbolicOperandCapabilities(Category, i);
86   ExtensionList ReqExts = getSymbolicOperandExtensions(Category, i);
87   if (ReqCaps.empty()) {
88     if (ReqExts.empty()) {
89       if (MinVerOK && MaxVerOK)
90         return {true, {}, {}, ReqMinVer, ReqMaxVer};
91       return {false, {}, {}, VersionTuple(), VersionTuple()};
92     }
93   } else if (MinVerOK && MaxVerOK) {
94     if (ReqCaps.size() == 1) {
95       auto Cap = ReqCaps[0];
96       if (Reqs.isCapabilityAvailable(Cap))
97         return {true, {Cap}, ReqExts, ReqMinVer, ReqMaxVer};
98     } else {
99       // By SPIR-V specification: "If an instruction, enumerant, or other
100       // feature specifies multiple enabling capabilities, only one such
101       // capability needs to be declared to use the feature." However, one
102       // capability may be preferred over another. We use command line
103       // argument(s) and AvoidCapabilities to avoid selection of certain
104       // capabilities if there are other options.
105       CapabilityList UseCaps;
106       for (auto Cap : ReqCaps)
107         if (Reqs.isCapabilityAvailable(Cap))
108           UseCaps.push_back(Cap);
109       for (size_t i = 0, Sz = UseCaps.size(); i < Sz; ++i) {
110         auto Cap = UseCaps[i];
111         if (i == Sz - 1 || !AvoidCaps.S.contains(Cap))
112           return {true, {Cap}, ReqExts, ReqMinVer, ReqMaxVer};
113       }
114     }
115   }
116   // If there are no capabilities, or we can't satisfy the version or
117   // capability requirements, use the list of extensions (if the subtarget
118   // can handle them all).
119   if (llvm::all_of(ReqExts, [&ST](const SPIRV::Extension::Extension &Ext) {
120         return ST.canUseExtension(Ext);
121       })) {
122     return {true,
123             {},
124             ReqExts,
125             VersionTuple(),
126             VersionTuple()}; // TODO: add versions to extensions.
127   }
128   return {false, {}, {}, VersionTuple(), VersionTuple()};
129 }
130 
131 void SPIRVModuleAnalysis::setBaseInfo(const Module &M) {
132   MAI.MaxID = 0;
133   for (int i = 0; i < SPIRV::NUM_MODULE_SECTIONS; i++)
134     MAI.MS[i].clear();
135   MAI.RegisterAliasTable.clear();
136   MAI.InstrsToDelete.clear();
137   MAI.FuncMap.clear();
138   MAI.GlobalVarList.clear();
139   MAI.ExtInstSetMap.clear();
140   MAI.Reqs.clear();
141   MAI.Reqs.initAvailableCapabilities(*ST);
142 
143   // TODO: determine memory model and source language from the configuratoin.
144   if (auto MemModel = M.getNamedMetadata("spirv.MemoryModel")) {
145     auto MemMD = MemModel->getOperand(0);
146     MAI.Addr = static_cast<SPIRV::AddressingModel::AddressingModel>(
147         getMetadataUInt(MemMD, 0));
148     MAI.Mem =
149         static_cast<SPIRV::MemoryModel::MemoryModel>(getMetadataUInt(MemMD, 1));
150   } else {
151     // TODO: Add support for VulkanMemoryModel.
152     MAI.Mem = ST->isOpenCLEnv() ? SPIRV::MemoryModel::OpenCL
153                                 : SPIRV::MemoryModel::GLSL450;
154     if (MAI.Mem == SPIRV::MemoryModel::OpenCL) {
155       unsigned PtrSize = ST->getPointerSize();
156       MAI.Addr = PtrSize == 32   ? SPIRV::AddressingModel::Physical32
157                  : PtrSize == 64 ? SPIRV::AddressingModel::Physical64
158                                  : SPIRV::AddressingModel::Logical;
159     } else {
160       // TODO: Add support for PhysicalStorageBufferAddress.
161       MAI.Addr = SPIRV::AddressingModel::Logical;
162     }
163   }
164   // Get the OpenCL version number from metadata.
165   // TODO: support other source languages.
166   if (auto VerNode = M.getNamedMetadata("opencl.ocl.version")) {
167     MAI.SrcLang = SPIRV::SourceLanguage::OpenCL_C;
168     // Construct version literal in accordance with SPIRV-LLVM-Translator.
169     // TODO: support multiple OCL version metadata.
170     assert(VerNode->getNumOperands() > 0 && "Invalid SPIR");
171     auto VersionMD = VerNode->getOperand(0);
172     unsigned MajorNum = getMetadataUInt(VersionMD, 0, 2);
173     unsigned MinorNum = getMetadataUInt(VersionMD, 1);
174     unsigned RevNum = getMetadataUInt(VersionMD, 2);
175     // Prevent Major part of OpenCL version to be 0
176     MAI.SrcLangVersion =
177         (std::max(1U, MajorNum) * 100 + MinorNum) * 1000 + RevNum;
178   } else {
179     // If there is no information about OpenCL version we are forced to generate
180     // OpenCL 1.0 by default for the OpenCL environment to avoid puzzling
181     // run-times with Unknown/0.0 version output. For a reference, LLVM-SPIRV
182     // Translator avoids potential issues with run-times in a similar manner.
183     if (ST->isOpenCLEnv()) {
184       MAI.SrcLang = SPIRV::SourceLanguage::OpenCL_CPP;
185       MAI.SrcLangVersion = 100000;
186     } else {
187       MAI.SrcLang = SPIRV::SourceLanguage::Unknown;
188       MAI.SrcLangVersion = 0;
189     }
190   }
191 
192   if (auto ExtNode = M.getNamedMetadata("opencl.used.extensions")) {
193     for (unsigned I = 0, E = ExtNode->getNumOperands(); I != E; ++I) {
194       MDNode *MD = ExtNode->getOperand(I);
195       if (!MD || MD->getNumOperands() == 0)
196         continue;
197       for (unsigned J = 0, N = MD->getNumOperands(); J != N; ++J)
198         MAI.SrcExt.insert(cast<MDString>(MD->getOperand(J))->getString());
199     }
200   }
201 
202   // Update required capabilities for this memory model, addressing model and
203   // source language.
204   MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::MemoryModelOperand,
205                                  MAI.Mem, *ST);
206   MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::SourceLanguageOperand,
207                                  MAI.SrcLang, *ST);
208   MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::AddressingModelOperand,
209                                  MAI.Addr, *ST);
210 
211   if (ST->isOpenCLEnv()) {
212     // TODO: check if it's required by default.
213     MAI.ExtInstSetMap[static_cast<unsigned>(
214         SPIRV::InstructionSet::OpenCL_std)] =
215         Register::index2VirtReg(MAI.getNextID());
216   }
217 }
218 
219 // Collect MI which defines the register in the given machine function.
220 static void collectDefInstr(Register Reg, const MachineFunction *MF,
221                             SPIRV::ModuleAnalysisInfo *MAI,
222                             SPIRV::ModuleSectionType MSType,
223                             bool DoInsert = true) {
224   assert(MAI->hasRegisterAlias(MF, Reg) && "Cannot find register alias");
225   MachineInstr *MI = MF->getRegInfo().getUniqueVRegDef(Reg);
226   assert(MI && "There should be an instruction that defines the register");
227   MAI->setSkipEmission(MI);
228   if (DoInsert)
229     MAI->MS[MSType].push_back(MI);
230 }
231 
232 void SPIRVModuleAnalysis::collectGlobalEntities(
233     const std::vector<SPIRV::DTSortableEntry *> &DepsGraph,
234     SPIRV::ModuleSectionType MSType,
235     std::function<bool(const SPIRV::DTSortableEntry *)> Pred,
236     bool UsePreOrder = false) {
237   DenseSet<const SPIRV::DTSortableEntry *> Visited;
238   for (const auto *E : DepsGraph) {
239     std::function<void(const SPIRV::DTSortableEntry *)> RecHoistUtil;
240     // NOTE: here we prefer recursive approach over iterative because
241     // we don't expect depchains long enough to cause SO.
242     RecHoistUtil = [MSType, UsePreOrder, &Visited, &Pred,
243                     &RecHoistUtil](const SPIRV::DTSortableEntry *E) {
244       if (Visited.count(E) || !Pred(E))
245         return;
246       Visited.insert(E);
247 
248       // Traversing deps graph in post-order allows us to get rid of
249       // register aliases preprocessing.
250       // But pre-order is required for correct processing of function
251       // declaration and arguments processing.
252       if (!UsePreOrder)
253         for (auto *S : E->getDeps())
254           RecHoistUtil(S);
255 
256       Register GlobalReg = Register::index2VirtReg(MAI.getNextID());
257       bool IsFirst = true;
258       for (auto &U : *E) {
259         const MachineFunction *MF = U.first;
260         Register Reg = U.second;
261         MAI.setRegisterAlias(MF, Reg, GlobalReg);
262         if (!MF->getRegInfo().getUniqueVRegDef(Reg))
263           continue;
264         collectDefInstr(Reg, MF, &MAI, MSType, IsFirst);
265         IsFirst = false;
266         if (E->getIsGV())
267           MAI.GlobalVarList.push_back(MF->getRegInfo().getUniqueVRegDef(Reg));
268       }
269 
270       if (UsePreOrder)
271         for (auto *S : E->getDeps())
272           RecHoistUtil(S);
273     };
274     RecHoistUtil(E);
275   }
276 }
277 
278 // The function initializes global register alias table for types, consts,
279 // global vars and func decls and collects these instruction for output
280 // at module level. Also it collects explicit OpExtension/OpCapability
281 // instructions.
282 void SPIRVModuleAnalysis::processDefInstrs(const Module &M) {
283   std::vector<SPIRV::DTSortableEntry *> DepsGraph;
284 
285   GR->buildDepsGraph(DepsGraph, SPVDumpDeps ? MMI : nullptr);
286 
287   collectGlobalEntities(
288       DepsGraph, SPIRV::MB_TypeConstVars,
289       [](const SPIRV::DTSortableEntry *E) { return !E->getIsFunc(); });
290 
291   for (auto F = M.begin(), E = M.end(); F != E; ++F) {
292     MachineFunction *MF = MMI->getMachineFunction(*F);
293     if (!MF)
294       continue;
295     // Iterate through and collect OpExtension/OpCapability instructions.
296     for (MachineBasicBlock &MBB : *MF) {
297       for (MachineInstr &MI : MBB) {
298         if (MI.getOpcode() == SPIRV::OpExtension) {
299           // Here, OpExtension just has a single enum operand, not a string.
300           auto Ext = SPIRV::Extension::Extension(MI.getOperand(0).getImm());
301           MAI.Reqs.addExtension(Ext);
302           MAI.setSkipEmission(&MI);
303         } else if (MI.getOpcode() == SPIRV::OpCapability) {
304           auto Cap = SPIRV::Capability::Capability(MI.getOperand(0).getImm());
305           MAI.Reqs.addCapability(Cap);
306           MAI.setSkipEmission(&MI);
307         }
308       }
309     }
310   }
311 
312   collectGlobalEntities(
313       DepsGraph, SPIRV::MB_ExtFuncDecls,
314       [](const SPIRV::DTSortableEntry *E) { return E->getIsFunc(); }, true);
315 }
316 
317 // Look for IDs declared with Import linkage, and map the corresponding function
318 // to the register defining that variable (which will usually be the result of
319 // an OpFunction). This lets us call externally imported functions using
320 // the correct ID registers.
321 void SPIRVModuleAnalysis::collectFuncNames(MachineInstr &MI,
322                                            const Function *F) {
323   if (MI.getOpcode() == SPIRV::OpDecorate) {
324     // If it's got Import linkage.
325     auto Dec = MI.getOperand(1).getImm();
326     if (Dec == static_cast<unsigned>(SPIRV::Decoration::LinkageAttributes)) {
327       auto Lnk = MI.getOperand(MI.getNumOperands() - 1).getImm();
328       if (Lnk == static_cast<unsigned>(SPIRV::LinkageType::Import)) {
329         // Map imported function name to function ID register.
330         const Function *ImportedFunc =
331             F->getParent()->getFunction(getStringImm(MI, 2));
332         Register Target = MI.getOperand(0).getReg();
333         MAI.FuncMap[ImportedFunc] = MAI.getRegisterAlias(MI.getMF(), Target);
334       }
335     }
336   } else if (MI.getOpcode() == SPIRV::OpFunction) {
337     // Record all internal OpFunction declarations.
338     Register Reg = MI.defs().begin()->getReg();
339     Register GlobalReg = MAI.getRegisterAlias(MI.getMF(), Reg);
340     assert(GlobalReg.isValid());
341     MAI.FuncMap[F] = GlobalReg;
342   }
343 }
344 
345 // References to a function via function pointers generate virtual
346 // registers without a definition. We are able to resolve this
347 // reference using Globar Register info into an OpFunction instruction
348 // and replace dummy operands by the corresponding global register references.
349 void SPIRVModuleAnalysis::collectFuncPtrs() {
350   for (auto &MI : MAI.MS[SPIRV::MB_TypeConstVars])
351     if (MI->getOpcode() == SPIRV::OpConstantFunctionPointerINTEL)
352       collectFuncPtrs(MI);
353 }
354 
355 void SPIRVModuleAnalysis::collectFuncPtrs(MachineInstr *MI) {
356   const MachineOperand *FunUse = &MI->getOperand(2);
357   if (const MachineOperand *FunDef = GR->getFunctionDefinitionByUse(FunUse)) {
358     const MachineInstr *FunDefMI = FunDef->getParent();
359     assert(FunDefMI->getOpcode() == SPIRV::OpFunction &&
360            "Constant function pointer must refer to function definition");
361     Register FunDefReg = FunDef->getReg();
362     Register GlobalFunDefReg =
363         MAI.getRegisterAlias(FunDefMI->getMF(), FunDefReg);
364     assert(GlobalFunDefReg.isValid() &&
365            "Function definition must refer to a global register");
366     Register FunPtrReg = FunUse->getReg();
367     MAI.setRegisterAlias(MI->getMF(), FunPtrReg, GlobalFunDefReg);
368   }
369 }
370 
371 using InstrSignature = SmallVector<size_t>;
372 using InstrTraces = std::set<InstrSignature>;
373 
374 // Returns a representation of an instruction as a vector of MachineOperand
375 // hash values, see llvm::hash_value(const MachineOperand &MO) for details.
376 // This creates a signature of the instruction with the same content
377 // that MachineOperand::isIdenticalTo uses for comparison.
378 static InstrSignature instrToSignature(MachineInstr &MI,
379                                        SPIRV::ModuleAnalysisInfo &MAI) {
380   InstrSignature Signature;
381   for (unsigned i = 0; i < MI.getNumOperands(); ++i) {
382     const MachineOperand &MO = MI.getOperand(i);
383     size_t h;
384     if (MO.isReg()) {
385       Register RegAlias = MAI.getRegisterAlias(MI.getMF(), MO.getReg());
386       // mimic llvm::hash_value(const MachineOperand &MO)
387       h = hash_combine(MO.getType(), (unsigned)RegAlias, MO.getSubReg(),
388                        MO.isDef());
389     } else {
390       h = hash_value(MO);
391     }
392     Signature.push_back(h);
393   }
394   return Signature;
395 }
396 
397 // Collect the given instruction in the specified MS. We assume global register
398 // numbering has already occurred by this point. We can directly compare reg
399 // arguments when detecting duplicates.
400 static void collectOtherInstr(MachineInstr &MI, SPIRV::ModuleAnalysisInfo &MAI,
401                               SPIRV::ModuleSectionType MSType, InstrTraces &IS,
402                               bool Append = true) {
403   MAI.setSkipEmission(&MI);
404   InstrSignature MISign = instrToSignature(MI, MAI);
405   auto FoundMI = IS.insert(MISign);
406   if (!FoundMI.second)
407     return; // insert failed, so we found a duplicate; don't add it to MAI.MS
408   // No duplicates, so add it.
409   if (Append)
410     MAI.MS[MSType].push_back(&MI);
411   else
412     MAI.MS[MSType].insert(MAI.MS[MSType].begin(), &MI);
413 }
414 
415 // Some global instructions make reference to function-local ID regs, so cannot
416 // be correctly collected until these registers are globally numbered.
417 void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) {
418   InstrTraces IS;
419   for (auto F = M.begin(), E = M.end(); F != E; ++F) {
420     if ((*F).isDeclaration())
421       continue;
422     MachineFunction *MF = MMI->getMachineFunction(*F);
423     assert(MF);
424     for (MachineBasicBlock &MBB : *MF)
425       for (MachineInstr &MI : MBB) {
426         if (MAI.getSkipEmission(&MI))
427           continue;
428         const unsigned OpCode = MI.getOpcode();
429         if (OpCode == SPIRV::OpString) {
430           collectOtherInstr(MI, MAI, SPIRV::MB_DebugStrings, IS);
431         } else if (OpCode == SPIRV::OpExtInst) {
432           MachineOperand Ins = MI.getOperand(3);
433           namespace NS = SPIRV::NonSemanticExtInst;
434           static constexpr int64_t GlobalNonSemanticDITy[] = {
435               NS::DebugSource, NS::DebugCompilationUnit};
436           bool IsGlobalDI = false;
437           for (unsigned Idx = 0; Idx < std::size(GlobalNonSemanticDITy); ++Idx)
438             IsGlobalDI |= Ins.getImm() == GlobalNonSemanticDITy[Idx];
439           if (IsGlobalDI)
440             collectOtherInstr(MI, MAI, SPIRV::MB_NonSemanticGlobalDI, IS);
441         } else if (OpCode == SPIRV::OpName || OpCode == SPIRV::OpMemberName) {
442           collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames, IS);
443         } else if (OpCode == SPIRV::OpEntryPoint) {
444           collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints, IS);
445         } else if (TII->isDecorationInstr(MI)) {
446           collectOtherInstr(MI, MAI, SPIRV::MB_Annotations, IS);
447           collectFuncNames(MI, &*F);
448         } else if (TII->isConstantInstr(MI)) {
449           // Now OpSpecConstant*s are not in DT,
450           // but they need to be collected anyway.
451           collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS);
452         } else if (OpCode == SPIRV::OpFunction) {
453           collectFuncNames(MI, &*F);
454         } else if (OpCode == SPIRV::OpTypeForwardPointer) {
455           collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS, false);
456         }
457       }
458   }
459 }
460 
461 // Number registers in all functions globally from 0 onwards and store
462 // the result in global register alias table. Some registers are already
463 // numbered in collectGlobalEntities.
464 void SPIRVModuleAnalysis::numberRegistersGlobally(const Module &M) {
465   for (auto F = M.begin(), E = M.end(); F != E; ++F) {
466     if ((*F).isDeclaration())
467       continue;
468     MachineFunction *MF = MMI->getMachineFunction(*F);
469     assert(MF);
470     for (MachineBasicBlock &MBB : *MF) {
471       for (MachineInstr &MI : MBB) {
472         for (MachineOperand &Op : MI.operands()) {
473           if (!Op.isReg())
474             continue;
475           Register Reg = Op.getReg();
476           if (MAI.hasRegisterAlias(MF, Reg))
477             continue;
478           Register NewReg = Register::index2VirtReg(MAI.getNextID());
479           MAI.setRegisterAlias(MF, Reg, NewReg);
480         }
481         if (MI.getOpcode() != SPIRV::OpExtInst)
482           continue;
483         auto Set = MI.getOperand(2).getImm();
484         if (!MAI.ExtInstSetMap.contains(Set))
485           MAI.ExtInstSetMap[Set] = Register::index2VirtReg(MAI.getNextID());
486       }
487     }
488   }
489 }
490 
491 // RequirementHandler implementations.
492 void SPIRV::RequirementHandler::getAndAddRequirements(
493     SPIRV::OperandCategory::OperandCategory Category, uint32_t i,
494     const SPIRVSubtarget &ST) {
495   addRequirements(getSymbolicOperandRequirements(Category, i, ST, *this));
496 }
497 
498 void SPIRV::RequirementHandler::recursiveAddCapabilities(
499     const CapabilityList &ToPrune) {
500   for (const auto &Cap : ToPrune) {
501     AllCaps.insert(Cap);
502     CapabilityList ImplicitDecls =
503         getSymbolicOperandCapabilities(OperandCategory::CapabilityOperand, Cap);
504     recursiveAddCapabilities(ImplicitDecls);
505   }
506 }
507 
508 void SPIRV::RequirementHandler::addCapabilities(const CapabilityList &ToAdd) {
509   for (const auto &Cap : ToAdd) {
510     bool IsNewlyInserted = AllCaps.insert(Cap).second;
511     if (!IsNewlyInserted) // Don't re-add if it's already been declared.
512       continue;
513     CapabilityList ImplicitDecls =
514         getSymbolicOperandCapabilities(OperandCategory::CapabilityOperand, Cap);
515     recursiveAddCapabilities(ImplicitDecls);
516     MinimalCaps.push_back(Cap);
517   }
518 }
519 
520 void SPIRV::RequirementHandler::addRequirements(
521     const SPIRV::Requirements &Req) {
522   if (!Req.IsSatisfiable)
523     report_fatal_error("Adding SPIR-V requirements this target can't satisfy.");
524 
525   if (Req.Cap.has_value())
526     addCapabilities({Req.Cap.value()});
527 
528   addExtensions(Req.Exts);
529 
530   if (!Req.MinVer.empty()) {
531     if (!MaxVersion.empty() && Req.MinVer > MaxVersion) {
532       LLVM_DEBUG(dbgs() << "Conflicting version requirements: >= " << Req.MinVer
533                         << " and <= " << MaxVersion << "\n");
534       report_fatal_error("Adding SPIR-V requirements that can't be satisfied.");
535     }
536 
537     if (MinVersion.empty() || Req.MinVer > MinVersion)
538       MinVersion = Req.MinVer;
539   }
540 
541   if (!Req.MaxVer.empty()) {
542     if (!MinVersion.empty() && Req.MaxVer < MinVersion) {
543       LLVM_DEBUG(dbgs() << "Conflicting version requirements: <= " << Req.MaxVer
544                         << " and >= " << MinVersion << "\n");
545       report_fatal_error("Adding SPIR-V requirements that can't be satisfied.");
546     }
547 
548     if (MaxVersion.empty() || Req.MaxVer < MaxVersion)
549       MaxVersion = Req.MaxVer;
550   }
551 }
552 
553 void SPIRV::RequirementHandler::checkSatisfiable(
554     const SPIRVSubtarget &ST) const {
555   // Report as many errors as possible before aborting the compilation.
556   bool IsSatisfiable = true;
557   auto TargetVer = ST.getSPIRVVersion();
558 
559   if (!MaxVersion.empty() && !TargetVer.empty() && MaxVersion < TargetVer) {
560     LLVM_DEBUG(
561         dbgs() << "Target SPIR-V version too high for required features\n"
562                << "Required max version: " << MaxVersion << " target version "
563                << TargetVer << "\n");
564     IsSatisfiable = false;
565   }
566 
567   if (!MinVersion.empty() && !TargetVer.empty() && MinVersion > TargetVer) {
568     LLVM_DEBUG(dbgs() << "Target SPIR-V version too low for required features\n"
569                       << "Required min version: " << MinVersion
570                       << " target version " << TargetVer << "\n");
571     IsSatisfiable = false;
572   }
573 
574   if (!MinVersion.empty() && !MaxVersion.empty() && MinVersion > MaxVersion) {
575     LLVM_DEBUG(
576         dbgs()
577         << "Version is too low for some features and too high for others.\n"
578         << "Required SPIR-V min version: " << MinVersion
579         << " required SPIR-V max version " << MaxVersion << "\n");
580     IsSatisfiable = false;
581   }
582 
583   for (auto Cap : MinimalCaps) {
584     if (AvailableCaps.contains(Cap))
585       continue;
586     LLVM_DEBUG(dbgs() << "Capability not supported: "
587                       << getSymbolicOperandMnemonic(
588                              OperandCategory::CapabilityOperand, Cap)
589                       << "\n");
590     IsSatisfiable = false;
591   }
592 
593   for (auto Ext : AllExtensions) {
594     if (ST.canUseExtension(Ext))
595       continue;
596     LLVM_DEBUG(dbgs() << "Extension not supported: "
597                       << getSymbolicOperandMnemonic(
598                              OperandCategory::ExtensionOperand, Ext)
599                       << "\n");
600     IsSatisfiable = false;
601   }
602 
603   if (!IsSatisfiable)
604     report_fatal_error("Unable to meet SPIR-V requirements for this target.");
605 }
606 
607 // Add the given capabilities and all their implicitly defined capabilities too.
608 void SPIRV::RequirementHandler::addAvailableCaps(const CapabilityList &ToAdd) {
609   for (const auto Cap : ToAdd)
610     if (AvailableCaps.insert(Cap).second)
611       addAvailableCaps(getSymbolicOperandCapabilities(
612           SPIRV::OperandCategory::CapabilityOperand, Cap));
613 }
614 
615 void SPIRV::RequirementHandler::removeCapabilityIf(
616     const Capability::Capability ToRemove,
617     const Capability::Capability IfPresent) {
618   if (AllCaps.contains(IfPresent))
619     AllCaps.erase(ToRemove);
620 }
621 
622 namespace llvm {
623 namespace SPIRV {
624 void RequirementHandler::initAvailableCapabilities(const SPIRVSubtarget &ST) {
625   if (ST.isOpenCLEnv()) {
626     initAvailableCapabilitiesForOpenCL(ST);
627     return;
628   }
629 
630   if (ST.isVulkanEnv()) {
631     initAvailableCapabilitiesForVulkan(ST);
632     return;
633   }
634 
635   report_fatal_error("Unimplemented environment for SPIR-V generation.");
636 }
637 
638 void RequirementHandler::initAvailableCapabilitiesForOpenCL(
639     const SPIRVSubtarget &ST) {
640   // Add the min requirements for different OpenCL and SPIR-V versions.
641   addAvailableCaps({Capability::Addresses, Capability::Float16Buffer,
642                     Capability::Int16, Capability::Int8, Capability::Kernel,
643                     Capability::Linkage, Capability::Vector16,
644                     Capability::Groups, Capability::GenericPointer,
645                     Capability::Shader});
646   if (ST.hasOpenCLFullProfile())
647     addAvailableCaps({Capability::Int64, Capability::Int64Atomics});
648   if (ST.hasOpenCLImageSupport()) {
649     addAvailableCaps({Capability::ImageBasic, Capability::LiteralSampler,
650                       Capability::Image1D, Capability::SampledBuffer,
651                       Capability::ImageBuffer});
652     if (ST.isAtLeastOpenCLVer(VersionTuple(2, 0)))
653       addAvailableCaps({Capability::ImageReadWrite});
654   }
655   if (ST.isAtLeastSPIRVVer(VersionTuple(1, 1)) &&
656       ST.isAtLeastOpenCLVer(VersionTuple(2, 2)))
657     addAvailableCaps({Capability::SubgroupDispatch, Capability::PipeStorage});
658   if (ST.isAtLeastSPIRVVer(VersionTuple(1, 3)))
659     addAvailableCaps({Capability::GroupNonUniform,
660                       Capability::GroupNonUniformVote,
661                       Capability::GroupNonUniformArithmetic,
662                       Capability::GroupNonUniformBallot,
663                       Capability::GroupNonUniformClustered,
664                       Capability::GroupNonUniformShuffle,
665                       Capability::GroupNonUniformShuffleRelative});
666   if (ST.isAtLeastSPIRVVer(VersionTuple(1, 4)))
667     addAvailableCaps({Capability::DenormPreserve, Capability::DenormFlushToZero,
668                       Capability::SignedZeroInfNanPreserve,
669                       Capability::RoundingModeRTE,
670                       Capability::RoundingModeRTZ});
671   // TODO: verify if this needs some checks.
672   addAvailableCaps({Capability::Float16, Capability::Float64});
673 
674   // Add capabilities enabled by extensions.
675   for (auto Extension : ST.getAllAvailableExtensions()) {
676     CapabilityList EnabledCapabilities =
677         getCapabilitiesEnabledByExtension(Extension);
678     addAvailableCaps(EnabledCapabilities);
679   }
680 
681   // TODO: add OpenCL extensions.
682 }
683 
684 void RequirementHandler::initAvailableCapabilitiesForVulkan(
685     const SPIRVSubtarget &ST) {
686   addAvailableCaps({Capability::Shader, Capability::Linkage});
687 
688   // Provided by all supported Vulkan versions.
689   addAvailableCaps({Capability::Int16, Capability::Int64, Capability::Float16,
690                     Capability::Float64, Capability::GroupNonUniform});
691 }
692 
693 } // namespace SPIRV
694 } // namespace llvm
695 
696 // Add the required capabilities from a decoration instruction (including
697 // BuiltIns).
698 static void addOpDecorateReqs(const MachineInstr &MI, unsigned DecIndex,
699                               SPIRV::RequirementHandler &Reqs,
700                               const SPIRVSubtarget &ST) {
701   int64_t DecOp = MI.getOperand(DecIndex).getImm();
702   auto Dec = static_cast<SPIRV::Decoration::Decoration>(DecOp);
703   Reqs.addRequirements(getSymbolicOperandRequirements(
704       SPIRV::OperandCategory::DecorationOperand, Dec, ST, Reqs));
705 
706   if (Dec == SPIRV::Decoration::BuiltIn) {
707     int64_t BuiltInOp = MI.getOperand(DecIndex + 1).getImm();
708     auto BuiltIn = static_cast<SPIRV::BuiltIn::BuiltIn>(BuiltInOp);
709     Reqs.addRequirements(getSymbolicOperandRequirements(
710         SPIRV::OperandCategory::BuiltInOperand, BuiltIn, ST, Reqs));
711   } else if (Dec == SPIRV::Decoration::LinkageAttributes) {
712     int64_t LinkageOp = MI.getOperand(MI.getNumOperands() - 1).getImm();
713     SPIRV::LinkageType::LinkageType LnkType =
714         static_cast<SPIRV::LinkageType::LinkageType>(LinkageOp);
715     if (LnkType == SPIRV::LinkageType::LinkOnceODR)
716       Reqs.addExtension(SPIRV::Extension::SPV_KHR_linkonce_odr);
717   } else if (Dec == SPIRV::Decoration::CacheControlLoadINTEL ||
718              Dec == SPIRV::Decoration::CacheControlStoreINTEL) {
719     Reqs.addExtension(SPIRV::Extension::SPV_INTEL_cache_controls);
720   } else if (Dec == SPIRV::Decoration::HostAccessINTEL) {
721     Reqs.addExtension(SPIRV::Extension::SPV_INTEL_global_variable_host_access);
722   } else if (Dec == SPIRV::Decoration::InitModeINTEL ||
723              Dec == SPIRV::Decoration::ImplementInRegisterMapINTEL) {
724     Reqs.addExtension(
725         SPIRV::Extension::SPV_INTEL_global_variable_fpga_decorations);
726   }
727 }
728 
729 // Add requirements for image handling.
730 static void addOpTypeImageReqs(const MachineInstr &MI,
731                                SPIRV::RequirementHandler &Reqs,
732                                const SPIRVSubtarget &ST) {
733   assert(MI.getNumOperands() >= 8 && "Insufficient operands for OpTypeImage");
734   // The operand indices used here are based on the OpTypeImage layout, which
735   // the MachineInstr follows as well.
736   int64_t ImgFormatOp = MI.getOperand(7).getImm();
737   auto ImgFormat = static_cast<SPIRV::ImageFormat::ImageFormat>(ImgFormatOp);
738   Reqs.getAndAddRequirements(SPIRV::OperandCategory::ImageFormatOperand,
739                              ImgFormat, ST);
740 
741   bool IsArrayed = MI.getOperand(4).getImm() == 1;
742   bool IsMultisampled = MI.getOperand(5).getImm() == 1;
743   bool NoSampler = MI.getOperand(6).getImm() == 2;
744   // Add dimension requirements.
745   assert(MI.getOperand(2).isImm());
746   switch (MI.getOperand(2).getImm()) {
747   case SPIRV::Dim::DIM_1D:
748     Reqs.addRequirements(NoSampler ? SPIRV::Capability::Image1D
749                                    : SPIRV::Capability::Sampled1D);
750     break;
751   case SPIRV::Dim::DIM_2D:
752     if (IsMultisampled && NoSampler)
753       Reqs.addRequirements(SPIRV::Capability::ImageMSArray);
754     break;
755   case SPIRV::Dim::DIM_Cube:
756     Reqs.addRequirements(SPIRV::Capability::Shader);
757     if (IsArrayed)
758       Reqs.addRequirements(NoSampler ? SPIRV::Capability::ImageCubeArray
759                                      : SPIRV::Capability::SampledCubeArray);
760     break;
761   case SPIRV::Dim::DIM_Rect:
762     Reqs.addRequirements(NoSampler ? SPIRV::Capability::ImageRect
763                                    : SPIRV::Capability::SampledRect);
764     break;
765   case SPIRV::Dim::DIM_Buffer:
766     Reqs.addRequirements(NoSampler ? SPIRV::Capability::ImageBuffer
767                                    : SPIRV::Capability::SampledBuffer);
768     break;
769   case SPIRV::Dim::DIM_SubpassData:
770     Reqs.addRequirements(SPIRV::Capability::InputAttachment);
771     break;
772   }
773 
774   // Has optional access qualifier.
775   // TODO: check if it's OpenCL's kernel.
776   if (MI.getNumOperands() > 8 &&
777       MI.getOperand(8).getImm() == SPIRV::AccessQualifier::ReadWrite)
778     Reqs.addRequirements(SPIRV::Capability::ImageReadWrite);
779   else
780     Reqs.addRequirements(SPIRV::Capability::ImageBasic);
781 }
782 
783 // Add requirements for handling atomic float instructions
784 #define ATOM_FLT_REQ_EXT_MSG(ExtName)                                          \
785   "The atomic float instruction requires the following SPIR-V "                \
786   "extension: SPV_EXT_shader_atomic_float" ExtName
787 static void AddAtomicFloatRequirements(const MachineInstr &MI,
788                                        SPIRV::RequirementHandler &Reqs,
789                                        const SPIRVSubtarget &ST) {
790   assert(MI.getOperand(1).isReg() &&
791          "Expect register operand in atomic float instruction");
792   Register TypeReg = MI.getOperand(1).getReg();
793   SPIRVType *TypeDef = MI.getMF()->getRegInfo().getVRegDef(TypeReg);
794   if (TypeDef->getOpcode() != SPIRV::OpTypeFloat)
795     report_fatal_error("Result type of an atomic float instruction must be a "
796                        "floating-point type scalar");
797 
798   unsigned BitWidth = TypeDef->getOperand(1).getImm();
799   unsigned Op = MI.getOpcode();
800   if (Op == SPIRV::OpAtomicFAddEXT) {
801     if (!ST.canUseExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float_add))
802       report_fatal_error(ATOM_FLT_REQ_EXT_MSG("_add"), false);
803     Reqs.addExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float_add);
804     switch (BitWidth) {
805     case 16:
806       if (!ST.canUseExtension(
807               SPIRV::Extension::SPV_EXT_shader_atomic_float16_add))
808         report_fatal_error(ATOM_FLT_REQ_EXT_MSG("16_add"), false);
809       Reqs.addExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float16_add);
810       Reqs.addCapability(SPIRV::Capability::AtomicFloat16AddEXT);
811       break;
812     case 32:
813       Reqs.addCapability(SPIRV::Capability::AtomicFloat32AddEXT);
814       break;
815     case 64:
816       Reqs.addCapability(SPIRV::Capability::AtomicFloat64AddEXT);
817       break;
818     default:
819       report_fatal_error(
820           "Unexpected floating-point type width in atomic float instruction");
821     }
822   } else {
823     if (!ST.canUseExtension(
824             SPIRV::Extension::SPV_EXT_shader_atomic_float_min_max))
825       report_fatal_error(ATOM_FLT_REQ_EXT_MSG("_min_max"), false);
826     Reqs.addExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float_min_max);
827     switch (BitWidth) {
828     case 16:
829       Reqs.addCapability(SPIRV::Capability::AtomicFloat16MinMaxEXT);
830       break;
831     case 32:
832       Reqs.addCapability(SPIRV::Capability::AtomicFloat32MinMaxEXT);
833       break;
834     case 64:
835       Reqs.addCapability(SPIRV::Capability::AtomicFloat64MinMaxEXT);
836       break;
837     default:
838       report_fatal_error(
839           "Unexpected floating-point type width in atomic float instruction");
840     }
841   }
842 }
843 
844 void addInstrRequirements(const MachineInstr &MI,
845                           SPIRV::RequirementHandler &Reqs,
846                           const SPIRVSubtarget &ST) {
847   switch (MI.getOpcode()) {
848   case SPIRV::OpMemoryModel: {
849     int64_t Addr = MI.getOperand(0).getImm();
850     Reqs.getAndAddRequirements(SPIRV::OperandCategory::AddressingModelOperand,
851                                Addr, ST);
852     int64_t Mem = MI.getOperand(1).getImm();
853     Reqs.getAndAddRequirements(SPIRV::OperandCategory::MemoryModelOperand, Mem,
854                                ST);
855     break;
856   }
857   case SPIRV::OpEntryPoint: {
858     int64_t Exe = MI.getOperand(0).getImm();
859     Reqs.getAndAddRequirements(SPIRV::OperandCategory::ExecutionModelOperand,
860                                Exe, ST);
861     break;
862   }
863   case SPIRV::OpExecutionMode:
864   case SPIRV::OpExecutionModeId: {
865     int64_t Exe = MI.getOperand(1).getImm();
866     Reqs.getAndAddRequirements(SPIRV::OperandCategory::ExecutionModeOperand,
867                                Exe, ST);
868     break;
869   }
870   case SPIRV::OpTypeMatrix:
871     Reqs.addCapability(SPIRV::Capability::Matrix);
872     break;
873   case SPIRV::OpTypeInt: {
874     unsigned BitWidth = MI.getOperand(1).getImm();
875     if (BitWidth == 64)
876       Reqs.addCapability(SPIRV::Capability::Int64);
877     else if (BitWidth == 16)
878       Reqs.addCapability(SPIRV::Capability::Int16);
879     else if (BitWidth == 8)
880       Reqs.addCapability(SPIRV::Capability::Int8);
881     break;
882   }
883   case SPIRV::OpTypeFloat: {
884     unsigned BitWidth = MI.getOperand(1).getImm();
885     if (BitWidth == 64)
886       Reqs.addCapability(SPIRV::Capability::Float64);
887     else if (BitWidth == 16)
888       Reqs.addCapability(SPIRV::Capability::Float16);
889     break;
890   }
891   case SPIRV::OpTypeVector: {
892     unsigned NumComponents = MI.getOperand(2).getImm();
893     if (NumComponents == 8 || NumComponents == 16)
894       Reqs.addCapability(SPIRV::Capability::Vector16);
895     break;
896   }
897   case SPIRV::OpTypePointer: {
898     auto SC = MI.getOperand(1).getImm();
899     Reqs.getAndAddRequirements(SPIRV::OperandCategory::StorageClassOperand, SC,
900                                ST);
901     // If it's a type of pointer to float16 targeting OpenCL, add Float16Buffer
902     // capability.
903     if (!ST.isOpenCLEnv())
904       break;
905     assert(MI.getOperand(2).isReg());
906     const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
907     SPIRVType *TypeDef = MRI.getVRegDef(MI.getOperand(2).getReg());
908     if (TypeDef->getOpcode() == SPIRV::OpTypeFloat &&
909         TypeDef->getOperand(1).getImm() == 16)
910       Reqs.addCapability(SPIRV::Capability::Float16Buffer);
911     break;
912   }
913   case SPIRV::OpExtInst: {
914     if (MI.getOperand(2).getImm() ==
915         static_cast<int64_t>(
916             SPIRV::InstructionSet::NonSemantic_Shader_DebugInfo_100)) {
917       Reqs.addExtension(SPIRV::Extension::SPV_KHR_non_semantic_info);
918     }
919     break;
920   }
921   case SPIRV::OpBitReverse:
922   case SPIRV::OpBitFieldInsert:
923   case SPIRV::OpBitFieldSExtract:
924   case SPIRV::OpBitFieldUExtract:
925     if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions)) {
926       Reqs.addCapability(SPIRV::Capability::Shader);
927       break;
928     }
929     Reqs.addExtension(SPIRV::Extension::SPV_KHR_bit_instructions);
930     Reqs.addCapability(SPIRV::Capability::BitInstructions);
931     break;
932   case SPIRV::OpTypeRuntimeArray:
933     Reqs.addCapability(SPIRV::Capability::Shader);
934     break;
935   case SPIRV::OpTypeOpaque:
936   case SPIRV::OpTypeEvent:
937     Reqs.addCapability(SPIRV::Capability::Kernel);
938     break;
939   case SPIRV::OpTypePipe:
940   case SPIRV::OpTypeReserveId:
941     Reqs.addCapability(SPIRV::Capability::Pipes);
942     break;
943   case SPIRV::OpTypeDeviceEvent:
944   case SPIRV::OpTypeQueue:
945   case SPIRV::OpBuildNDRange:
946     Reqs.addCapability(SPIRV::Capability::DeviceEnqueue);
947     break;
948   case SPIRV::OpDecorate:
949   case SPIRV::OpDecorateId:
950   case SPIRV::OpDecorateString:
951     addOpDecorateReqs(MI, 1, Reqs, ST);
952     break;
953   case SPIRV::OpMemberDecorate:
954   case SPIRV::OpMemberDecorateString:
955     addOpDecorateReqs(MI, 2, Reqs, ST);
956     break;
957   case SPIRV::OpInBoundsPtrAccessChain:
958     Reqs.addCapability(SPIRV::Capability::Addresses);
959     break;
960   case SPIRV::OpConstantSampler:
961     Reqs.addCapability(SPIRV::Capability::LiteralSampler);
962     break;
963   case SPIRV::OpTypeImage:
964     addOpTypeImageReqs(MI, Reqs, ST);
965     break;
966   case SPIRV::OpTypeSampler:
967     Reqs.addCapability(SPIRV::Capability::ImageBasic);
968     break;
969   case SPIRV::OpTypeForwardPointer:
970     // TODO: check if it's OpenCL's kernel.
971     Reqs.addCapability(SPIRV::Capability::Addresses);
972     break;
973   case SPIRV::OpAtomicFlagTestAndSet:
974   case SPIRV::OpAtomicLoad:
975   case SPIRV::OpAtomicStore:
976   case SPIRV::OpAtomicExchange:
977   case SPIRV::OpAtomicCompareExchange:
978   case SPIRV::OpAtomicIIncrement:
979   case SPIRV::OpAtomicIDecrement:
980   case SPIRV::OpAtomicIAdd:
981   case SPIRV::OpAtomicISub:
982   case SPIRV::OpAtomicUMin:
983   case SPIRV::OpAtomicUMax:
984   case SPIRV::OpAtomicSMin:
985   case SPIRV::OpAtomicSMax:
986   case SPIRV::OpAtomicAnd:
987   case SPIRV::OpAtomicOr:
988   case SPIRV::OpAtomicXor: {
989     const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
990     const MachineInstr *InstrPtr = &MI;
991     if (MI.getOpcode() == SPIRV::OpAtomicStore) {
992       assert(MI.getOperand(3).isReg());
993       InstrPtr = MRI.getVRegDef(MI.getOperand(3).getReg());
994       assert(InstrPtr && "Unexpected type instruction for OpAtomicStore");
995     }
996     assert(InstrPtr->getOperand(1).isReg() && "Unexpected operand in atomic");
997     Register TypeReg = InstrPtr->getOperand(1).getReg();
998     SPIRVType *TypeDef = MRI.getVRegDef(TypeReg);
999     if (TypeDef->getOpcode() == SPIRV::OpTypeInt) {
1000       unsigned BitWidth = TypeDef->getOperand(1).getImm();
1001       if (BitWidth == 64)
1002         Reqs.addCapability(SPIRV::Capability::Int64Atomics);
1003     }
1004     break;
1005   }
1006   case SPIRV::OpGroupNonUniformIAdd:
1007   case SPIRV::OpGroupNonUniformFAdd:
1008   case SPIRV::OpGroupNonUniformIMul:
1009   case SPIRV::OpGroupNonUniformFMul:
1010   case SPIRV::OpGroupNonUniformSMin:
1011   case SPIRV::OpGroupNonUniformUMin:
1012   case SPIRV::OpGroupNonUniformFMin:
1013   case SPIRV::OpGroupNonUniformSMax:
1014   case SPIRV::OpGroupNonUniformUMax:
1015   case SPIRV::OpGroupNonUniformFMax:
1016   case SPIRV::OpGroupNonUniformBitwiseAnd:
1017   case SPIRV::OpGroupNonUniformBitwiseOr:
1018   case SPIRV::OpGroupNonUniformBitwiseXor:
1019   case SPIRV::OpGroupNonUniformLogicalAnd:
1020   case SPIRV::OpGroupNonUniformLogicalOr:
1021   case SPIRV::OpGroupNonUniformLogicalXor: {
1022     assert(MI.getOperand(3).isImm());
1023     int64_t GroupOp = MI.getOperand(3).getImm();
1024     switch (GroupOp) {
1025     case SPIRV::GroupOperation::Reduce:
1026     case SPIRV::GroupOperation::InclusiveScan:
1027     case SPIRV::GroupOperation::ExclusiveScan:
1028       Reqs.addCapability(SPIRV::Capability::Kernel);
1029       Reqs.addCapability(SPIRV::Capability::GroupNonUniformArithmetic);
1030       Reqs.addCapability(SPIRV::Capability::GroupNonUniformBallot);
1031       break;
1032     case SPIRV::GroupOperation::ClusteredReduce:
1033       Reqs.addCapability(SPIRV::Capability::GroupNonUniformClustered);
1034       break;
1035     case SPIRV::GroupOperation::PartitionedReduceNV:
1036     case SPIRV::GroupOperation::PartitionedInclusiveScanNV:
1037     case SPIRV::GroupOperation::PartitionedExclusiveScanNV:
1038       Reqs.addCapability(SPIRV::Capability::GroupNonUniformPartitionedNV);
1039       break;
1040     }
1041     break;
1042   }
1043   case SPIRV::OpGroupNonUniformShuffle:
1044   case SPIRV::OpGroupNonUniformShuffleXor:
1045     Reqs.addCapability(SPIRV::Capability::GroupNonUniformShuffle);
1046     break;
1047   case SPIRV::OpGroupNonUniformShuffleUp:
1048   case SPIRV::OpGroupNonUniformShuffleDown:
1049     Reqs.addCapability(SPIRV::Capability::GroupNonUniformShuffleRelative);
1050     break;
1051   case SPIRV::OpGroupAll:
1052   case SPIRV::OpGroupAny:
1053   case SPIRV::OpGroupBroadcast:
1054   case SPIRV::OpGroupIAdd:
1055   case SPIRV::OpGroupFAdd:
1056   case SPIRV::OpGroupFMin:
1057   case SPIRV::OpGroupUMin:
1058   case SPIRV::OpGroupSMin:
1059   case SPIRV::OpGroupFMax:
1060   case SPIRV::OpGroupUMax:
1061   case SPIRV::OpGroupSMax:
1062     Reqs.addCapability(SPIRV::Capability::Groups);
1063     break;
1064   case SPIRV::OpGroupNonUniformElect:
1065     Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
1066     break;
1067   case SPIRV::OpGroupNonUniformAll:
1068   case SPIRV::OpGroupNonUniformAny:
1069   case SPIRV::OpGroupNonUniformAllEqual:
1070     Reqs.addCapability(SPIRV::Capability::GroupNonUniformVote);
1071     break;
1072   case SPIRV::OpGroupNonUniformBroadcast:
1073   case SPIRV::OpGroupNonUniformBroadcastFirst:
1074   case SPIRV::OpGroupNonUniformBallot:
1075   case SPIRV::OpGroupNonUniformInverseBallot:
1076   case SPIRV::OpGroupNonUniformBallotBitExtract:
1077   case SPIRV::OpGroupNonUniformBallotBitCount:
1078   case SPIRV::OpGroupNonUniformBallotFindLSB:
1079   case SPIRV::OpGroupNonUniformBallotFindMSB:
1080     Reqs.addCapability(SPIRV::Capability::GroupNonUniformBallot);
1081     break;
1082   case SPIRV::OpSubgroupShuffleINTEL:
1083   case SPIRV::OpSubgroupShuffleDownINTEL:
1084   case SPIRV::OpSubgroupShuffleUpINTEL:
1085   case SPIRV::OpSubgroupShuffleXorINTEL:
1086     if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) {
1087       Reqs.addExtension(SPIRV::Extension::SPV_INTEL_subgroups);
1088       Reqs.addCapability(SPIRV::Capability::SubgroupShuffleINTEL);
1089     }
1090     break;
1091   case SPIRV::OpSubgroupBlockReadINTEL:
1092   case SPIRV::OpSubgroupBlockWriteINTEL:
1093     if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) {
1094       Reqs.addExtension(SPIRV::Extension::SPV_INTEL_subgroups);
1095       Reqs.addCapability(SPIRV::Capability::SubgroupBufferBlockIOINTEL);
1096     }
1097     break;
1098   case SPIRV::OpSubgroupImageBlockReadINTEL:
1099   case SPIRV::OpSubgroupImageBlockWriteINTEL:
1100     if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) {
1101       Reqs.addExtension(SPIRV::Extension::SPV_INTEL_subgroups);
1102       Reqs.addCapability(SPIRV::Capability::SubgroupImageBlockIOINTEL);
1103     }
1104     break;
1105   case SPIRV::OpAssumeTrueKHR:
1106   case SPIRV::OpExpectKHR:
1107     if (ST.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) {
1108       Reqs.addExtension(SPIRV::Extension::SPV_KHR_expect_assume);
1109       Reqs.addCapability(SPIRV::Capability::ExpectAssumeKHR);
1110     }
1111     break;
1112   case SPIRV::OpPtrCastToCrossWorkgroupINTEL:
1113   case SPIRV::OpCrossWorkgroupCastToPtrINTEL:
1114     if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_usm_storage_classes)) {
1115       Reqs.addExtension(SPIRV::Extension::SPV_INTEL_usm_storage_classes);
1116       Reqs.addCapability(SPIRV::Capability::USMStorageClassesINTEL);
1117     }
1118     break;
1119   case SPIRV::OpConstantFunctionPointerINTEL:
1120     if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers)) {
1121       Reqs.addExtension(SPIRV::Extension::SPV_INTEL_function_pointers);
1122       Reqs.addCapability(SPIRV::Capability::FunctionPointersINTEL);
1123     }
1124     break;
1125   case SPIRV::OpGroupNonUniformRotateKHR:
1126     if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_subgroup_rotate))
1127       report_fatal_error("OpGroupNonUniformRotateKHR instruction requires the "
1128                          "following SPIR-V extension: SPV_KHR_subgroup_rotate",
1129                          false);
1130     Reqs.addExtension(SPIRV::Extension::SPV_KHR_subgroup_rotate);
1131     Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
1132     Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
1133     break;
1134   case SPIRV::OpGroupIMulKHR:
1135   case SPIRV::OpGroupFMulKHR:
1136   case SPIRV::OpGroupBitwiseAndKHR:
1137   case SPIRV::OpGroupBitwiseOrKHR:
1138   case SPIRV::OpGroupBitwiseXorKHR:
1139   case SPIRV::OpGroupLogicalAndKHR:
1140   case SPIRV::OpGroupLogicalOrKHR:
1141   case SPIRV::OpGroupLogicalXorKHR:
1142     if (ST.canUseExtension(
1143             SPIRV::Extension::SPV_KHR_uniform_group_instructions)) {
1144       Reqs.addExtension(SPIRV::Extension::SPV_KHR_uniform_group_instructions);
1145       Reqs.addCapability(SPIRV::Capability::GroupUniformArithmeticKHR);
1146     }
1147     break;
1148   case SPIRV::OpReadClockKHR:
1149     if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_shader_clock))
1150       report_fatal_error("OpReadClockKHR instruction requires the "
1151                          "following SPIR-V extension: SPV_KHR_shader_clock",
1152                          false);
1153     Reqs.addExtension(SPIRV::Extension::SPV_KHR_shader_clock);
1154     Reqs.addCapability(SPIRV::Capability::ShaderClockKHR);
1155     break;
1156   case SPIRV::OpFunctionPointerCallINTEL:
1157     if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers)) {
1158       Reqs.addExtension(SPIRV::Extension::SPV_INTEL_function_pointers);
1159       Reqs.addCapability(SPIRV::Capability::FunctionPointersINTEL);
1160     }
1161     break;
1162   case SPIRV::OpAtomicFAddEXT:
1163   case SPIRV::OpAtomicFMinEXT:
1164   case SPIRV::OpAtomicFMaxEXT:
1165     AddAtomicFloatRequirements(MI, Reqs, ST);
1166     break;
1167   case SPIRV::OpConvertBF16ToFINTEL:
1168   case SPIRV::OpConvertFToBF16INTEL:
1169     if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_bfloat16_conversion)) {
1170       Reqs.addExtension(SPIRV::Extension::SPV_INTEL_bfloat16_conversion);
1171       Reqs.addCapability(SPIRV::Capability::BFloat16ConversionINTEL);
1172     }
1173     break;
1174   case SPIRV::OpVariableLengthArrayINTEL:
1175   case SPIRV::OpSaveMemoryINTEL:
1176   case SPIRV::OpRestoreMemoryINTEL:
1177     if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array)) {
1178       Reqs.addExtension(SPIRV::Extension::SPV_INTEL_variable_length_array);
1179       Reqs.addCapability(SPIRV::Capability::VariableLengthArrayINTEL);
1180     }
1181     break;
1182   case SPIRV::OpAsmTargetINTEL:
1183   case SPIRV::OpAsmINTEL:
1184   case SPIRV::OpAsmCallINTEL:
1185     if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_inline_assembly)) {
1186       Reqs.addExtension(SPIRV::Extension::SPV_INTEL_inline_assembly);
1187       Reqs.addCapability(SPIRV::Capability::AsmINTEL);
1188     }
1189     break;
1190   case SPIRV::OpTypeCooperativeMatrixKHR:
1191     if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_cooperative_matrix))
1192       report_fatal_error(
1193           "OpTypeCooperativeMatrixKHR type requires the "
1194           "following SPIR-V extension: SPV_KHR_cooperative_matrix",
1195           false);
1196     Reqs.addExtension(SPIRV::Extension::SPV_KHR_cooperative_matrix);
1197     Reqs.addCapability(SPIRV::Capability::CooperativeMatrixKHR);
1198     break;
1199   default:
1200     break;
1201   }
1202 
1203   // If we require capability Shader, then we can remove the requirement for
1204   // the BitInstructions capability, since Shader is a superset capability
1205   // of BitInstructions.
1206   Reqs.removeCapabilityIf(SPIRV::Capability::BitInstructions,
1207                           SPIRV::Capability::Shader);
1208 }
1209 
1210 static void collectReqs(const Module &M, SPIRV::ModuleAnalysisInfo &MAI,
1211                         MachineModuleInfo *MMI, const SPIRVSubtarget &ST) {
1212   // Collect requirements for existing instructions.
1213   for (auto F = M.begin(), E = M.end(); F != E; ++F) {
1214     MachineFunction *MF = MMI->getMachineFunction(*F);
1215     if (!MF)
1216       continue;
1217     for (const MachineBasicBlock &MBB : *MF)
1218       for (const MachineInstr &MI : MBB)
1219         addInstrRequirements(MI, MAI.Reqs, ST);
1220   }
1221   // Collect requirements for OpExecutionMode instructions.
1222   auto Node = M.getNamedMetadata("spirv.ExecutionMode");
1223   if (Node) {
1224     // SPV_KHR_float_controls is not available until v1.4
1225     bool RequireFloatControls = false,
1226          VerLower14 = !ST.isAtLeastSPIRVVer(VersionTuple(1, 4));
1227     for (unsigned i = 0; i < Node->getNumOperands(); i++) {
1228       MDNode *MDN = cast<MDNode>(Node->getOperand(i));
1229       const MDOperand &MDOp = MDN->getOperand(1);
1230       if (auto *CMeta = dyn_cast<ConstantAsMetadata>(MDOp)) {
1231         Constant *C = CMeta->getValue();
1232         if (ConstantInt *Const = dyn_cast<ConstantInt>(C)) {
1233           auto EM = Const->getZExtValue();
1234           MAI.Reqs.getAndAddRequirements(
1235               SPIRV::OperandCategory::ExecutionModeOperand, EM, ST);
1236           // add SPV_KHR_float_controls if the version is too low
1237           switch (EM) {
1238           case SPIRV::ExecutionMode::DenormPreserve:
1239           case SPIRV::ExecutionMode::DenormFlushToZero:
1240           case SPIRV::ExecutionMode::SignedZeroInfNanPreserve:
1241           case SPIRV::ExecutionMode::RoundingModeRTE:
1242           case SPIRV::ExecutionMode::RoundingModeRTZ:
1243             RequireFloatControls = VerLower14;
1244             break;
1245           }
1246         }
1247       }
1248     }
1249     if (RequireFloatControls &&
1250         ST.canUseExtension(SPIRV::Extension::SPV_KHR_float_controls))
1251       MAI.Reqs.addExtension(SPIRV::Extension::SPV_KHR_float_controls);
1252   }
1253   for (auto FI = M.begin(), E = M.end(); FI != E; ++FI) {
1254     const Function &F = *FI;
1255     if (F.isDeclaration())
1256       continue;
1257     if (F.getMetadata("reqd_work_group_size"))
1258       MAI.Reqs.getAndAddRequirements(
1259           SPIRV::OperandCategory::ExecutionModeOperand,
1260           SPIRV::ExecutionMode::LocalSize, ST);
1261     if (F.getFnAttribute("hlsl.numthreads").isValid()) {
1262       MAI.Reqs.getAndAddRequirements(
1263           SPIRV::OperandCategory::ExecutionModeOperand,
1264           SPIRV::ExecutionMode::LocalSize, ST);
1265     }
1266     if (F.getMetadata("work_group_size_hint"))
1267       MAI.Reqs.getAndAddRequirements(
1268           SPIRV::OperandCategory::ExecutionModeOperand,
1269           SPIRV::ExecutionMode::LocalSizeHint, ST);
1270     if (F.getMetadata("intel_reqd_sub_group_size"))
1271       MAI.Reqs.getAndAddRequirements(
1272           SPIRV::OperandCategory::ExecutionModeOperand,
1273           SPIRV::ExecutionMode::SubgroupSize, ST);
1274     if (F.getMetadata("vec_type_hint"))
1275       MAI.Reqs.getAndAddRequirements(
1276           SPIRV::OperandCategory::ExecutionModeOperand,
1277           SPIRV::ExecutionMode::VecTypeHint, ST);
1278 
1279     if (F.hasOptNone() &&
1280         ST.canUseExtension(SPIRV::Extension::SPV_INTEL_optnone)) {
1281       // Output OpCapability OptNoneINTEL.
1282       MAI.Reqs.addExtension(SPIRV::Extension::SPV_INTEL_optnone);
1283       MAI.Reqs.addCapability(SPIRV::Capability::OptNoneINTEL);
1284     }
1285   }
1286 }
1287 
1288 static unsigned getFastMathFlags(const MachineInstr &I) {
1289   unsigned Flags = SPIRV::FPFastMathMode::None;
1290   if (I.getFlag(MachineInstr::MIFlag::FmNoNans))
1291     Flags |= SPIRV::FPFastMathMode::NotNaN;
1292   if (I.getFlag(MachineInstr::MIFlag::FmNoInfs))
1293     Flags |= SPIRV::FPFastMathMode::NotInf;
1294   if (I.getFlag(MachineInstr::MIFlag::FmNsz))
1295     Flags |= SPIRV::FPFastMathMode::NSZ;
1296   if (I.getFlag(MachineInstr::MIFlag::FmArcp))
1297     Flags |= SPIRV::FPFastMathMode::AllowRecip;
1298   if (I.getFlag(MachineInstr::MIFlag::FmReassoc))
1299     Flags |= SPIRV::FPFastMathMode::Fast;
1300   return Flags;
1301 }
1302 
1303 static void handleMIFlagDecoration(MachineInstr &I, const SPIRVSubtarget &ST,
1304                                    const SPIRVInstrInfo &TII,
1305                                    SPIRV::RequirementHandler &Reqs) {
1306   if (I.getFlag(MachineInstr::MIFlag::NoSWrap) && TII.canUseNSW(I) &&
1307       getSymbolicOperandRequirements(SPIRV::OperandCategory::DecorationOperand,
1308                                      SPIRV::Decoration::NoSignedWrap, ST, Reqs)
1309           .IsSatisfiable) {
1310     buildOpDecorate(I.getOperand(0).getReg(), I, TII,
1311                     SPIRV::Decoration::NoSignedWrap, {});
1312   }
1313   if (I.getFlag(MachineInstr::MIFlag::NoUWrap) && TII.canUseNUW(I) &&
1314       getSymbolicOperandRequirements(SPIRV::OperandCategory::DecorationOperand,
1315                                      SPIRV::Decoration::NoUnsignedWrap, ST,
1316                                      Reqs)
1317           .IsSatisfiable) {
1318     buildOpDecorate(I.getOperand(0).getReg(), I, TII,
1319                     SPIRV::Decoration::NoUnsignedWrap, {});
1320   }
1321   if (!TII.canUseFastMathFlags(I))
1322     return;
1323   unsigned FMFlags = getFastMathFlags(I);
1324   if (FMFlags == SPIRV::FPFastMathMode::None)
1325     return;
1326   Register DstReg = I.getOperand(0).getReg();
1327   buildOpDecorate(DstReg, I, TII, SPIRV::Decoration::FPFastMathMode, {FMFlags});
1328 }
1329 
1330 // Walk all functions and add decorations related to MI flags.
1331 static void addDecorations(const Module &M, const SPIRVInstrInfo &TII,
1332                            MachineModuleInfo *MMI, const SPIRVSubtarget &ST,
1333                            SPIRV::ModuleAnalysisInfo &MAI) {
1334   for (auto F = M.begin(), E = M.end(); F != E; ++F) {
1335     MachineFunction *MF = MMI->getMachineFunction(*F);
1336     if (!MF)
1337       continue;
1338     for (auto &MBB : *MF)
1339       for (auto &MI : MBB)
1340         handleMIFlagDecoration(MI, ST, TII, MAI.Reqs);
1341   }
1342 }
1343 
1344 struct SPIRV::ModuleAnalysisInfo SPIRVModuleAnalysis::MAI;
1345 
1346 void SPIRVModuleAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
1347   AU.addRequired<TargetPassConfig>();
1348   AU.addRequired<MachineModuleInfoWrapperPass>();
1349 }
1350 
1351 bool SPIRVModuleAnalysis::runOnModule(Module &M) {
1352   SPIRVTargetMachine &TM =
1353       getAnalysis<TargetPassConfig>().getTM<SPIRVTargetMachine>();
1354   ST = TM.getSubtargetImpl();
1355   GR = ST->getSPIRVGlobalRegistry();
1356   TII = ST->getInstrInfo();
1357 
1358   MMI = &getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
1359 
1360   setBaseInfo(M);
1361 
1362   addDecorations(M, *TII, MMI, *ST, MAI);
1363 
1364   collectReqs(M, MAI, MMI, *ST);
1365 
1366   // Process type/const/global var/func decl instructions, number their
1367   // destination registers from 0 to N, collect Extensions and Capabilities.
1368   processDefInstrs(M);
1369 
1370   // Number rest of registers from N+1 onwards.
1371   numberRegistersGlobally(M);
1372 
1373   // Update references to OpFunction instructions to use Global Registers
1374   if (GR->hasConstFunPtr())
1375     collectFuncPtrs();
1376 
1377   // Collect OpName, OpEntryPoint, OpDecorate etc, process other instructions.
1378   processOtherInstrs(M);
1379 
1380   // If there are no entry points, we need the Linkage capability.
1381   if (MAI.MS[SPIRV::MB_EntryPoints].empty())
1382     MAI.Reqs.addCapability(SPIRV::Capability::Linkage);
1383 
1384   // Set maximum ID used.
1385   GR->setBound(MAI.MaxID);
1386 
1387   return false;
1388 }
1389