1 //===- SPIRVInstructionSelector.cpp ------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the targeting of the InstructionSelector class for 10 // SPIRV. 11 // TODO: This should be generated by TableGen. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MCTargetDesc/SPIRVBaseInfo.h" 16 #include "MCTargetDesc/SPIRVMCTargetDesc.h" 17 #include "SPIRV.h" 18 #include "SPIRVGlobalRegistry.h" 19 #include "SPIRVInstrInfo.h" 20 #include "SPIRVRegisterBankInfo.h" 21 #include "SPIRVRegisterInfo.h" 22 #include "SPIRVTargetMachine.h" 23 #include "SPIRVUtils.h" 24 #include "llvm/ADT/APFloat.h" 25 #include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h" 26 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h" 27 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 28 #include "llvm/CodeGen/MachineInstrBuilder.h" 29 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/TargetOpcodes.h" 32 #include "llvm/IR/IntrinsicsSPIRV.h" 33 #include "llvm/Support/Debug.h" 34 35 namespace llvm { 36 37 class SPIRVMachineModuleInfo : public MachineModuleInfoImpl { 38 public: 39 SyncScope::ID Work_ItemSSID; 40 SyncScope::ID WorkGroupSSID; 41 SyncScope::ID DeviceSSID; 42 SyncScope::ID AllSVMDevicesSSID; 43 SyncScope::ID SubGroupSSID; 44 45 SPIRVMachineModuleInfo(const MachineModuleInfo &MMI) { 46 LLVMContext &CTX = MMI.getModule()->getContext(); 47 Work_ItemSSID = CTX.getOrInsertSyncScopeID("work_item"); 48 WorkGroupSSID = CTX.getOrInsertSyncScopeID("workgroup"); 49 DeviceSSID = CTX.getOrInsertSyncScopeID("device"); 50 AllSVMDevicesSSID = CTX.getOrInsertSyncScopeID("all_svm_devices"); 51 SubGroupSSID = CTX.getOrInsertSyncScopeID("sub_group"); 52 } 53 }; 54 55 } // end namespace llvm 56 57 #define DEBUG_TYPE "spirv-isel" 58 59 using namespace llvm; 60 namespace CL = SPIRV::OpenCLExtInst; 61 namespace GL = SPIRV::GLSLExtInst; 62 63 using ExtInstList = 64 std::vector<std::pair<SPIRV::InstructionSet::InstructionSet, uint32_t>>; 65 66 namespace { 67 68 #define GET_GLOBALISEL_PREDICATE_BITSET 69 #include "SPIRVGenGlobalISel.inc" 70 #undef GET_GLOBALISEL_PREDICATE_BITSET 71 72 class SPIRVInstructionSelector : public InstructionSelector { 73 const SPIRVSubtarget &STI; 74 const SPIRVInstrInfo &TII; 75 const SPIRVRegisterInfo &TRI; 76 const RegisterBankInfo &RBI; 77 SPIRVGlobalRegistry &GR; 78 MachineRegisterInfo *MRI; 79 SPIRVMachineModuleInfo *MMI = nullptr; 80 81 /// We need to keep track of the number we give to anonymous global values to 82 /// generate the same name every time when this is needed. 83 mutable DenseMap<const GlobalValue *, unsigned> UnnamedGlobalIDs; 84 85 public: 86 SPIRVInstructionSelector(const SPIRVTargetMachine &TM, 87 const SPIRVSubtarget &ST, 88 const RegisterBankInfo &RBI); 89 void setupMF(MachineFunction &MF, GISelKnownBits *KB, 90 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, 91 BlockFrequencyInfo *BFI) override; 92 // Common selection code. Instruction-specific selection occurs in spvSelect. 93 bool select(MachineInstr &I) override; 94 static const char *getName() { return DEBUG_TYPE; } 95 96 #define GET_GLOBALISEL_PREDICATES_DECL 97 #include "SPIRVGenGlobalISel.inc" 98 #undef GET_GLOBALISEL_PREDICATES_DECL 99 100 #define GET_GLOBALISEL_TEMPORARIES_DECL 101 #include "SPIRVGenGlobalISel.inc" 102 #undef GET_GLOBALISEL_TEMPORARIES_DECL 103 104 private: 105 // tblgen-erated 'select' implementation, used as the initial selector for 106 // the patterns that don't require complex C++. 107 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 108 109 // All instruction-specific selection that didn't happen in "select()". 110 // Is basically a large Switch/Case delegating to all other select method. 111 bool spvSelect(Register ResVReg, const SPIRVType *ResType, 112 MachineInstr &I) const; 113 114 bool selectGlobalValue(Register ResVReg, MachineInstr &I, 115 const MachineInstr *Init = nullptr) const; 116 117 bool selectUnOpWithSrc(Register ResVReg, const SPIRVType *ResType, 118 MachineInstr &I, Register SrcReg, 119 unsigned Opcode) const; 120 bool selectUnOp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, 121 unsigned Opcode) const; 122 123 bool selectBitcast(Register ResVReg, const SPIRVType *ResType, 124 MachineInstr &I) const; 125 126 bool selectLoad(Register ResVReg, const SPIRVType *ResType, 127 MachineInstr &I) const; 128 bool selectStore(MachineInstr &I) const; 129 130 bool selectStackSave(Register ResVReg, const SPIRVType *ResType, 131 MachineInstr &I) const; 132 bool selectStackRestore(MachineInstr &I) const; 133 134 bool selectMemOperation(Register ResVReg, MachineInstr &I) const; 135 136 bool selectAtomicRMW(Register ResVReg, const SPIRVType *ResType, 137 MachineInstr &I, unsigned NewOpcode, 138 unsigned NegateOpcode = 0) const; 139 140 bool selectAtomicCmpXchg(Register ResVReg, const SPIRVType *ResType, 141 MachineInstr &I) const; 142 143 bool selectFence(MachineInstr &I) const; 144 145 bool selectAddrSpaceCast(Register ResVReg, const SPIRVType *ResType, 146 MachineInstr &I) const; 147 148 bool selectAnyOrAll(Register ResVReg, const SPIRVType *ResType, 149 MachineInstr &I, unsigned OpType) const; 150 151 bool selectAll(Register ResVReg, const SPIRVType *ResType, 152 MachineInstr &I) const; 153 154 bool selectAny(Register ResVReg, const SPIRVType *ResType, 155 MachineInstr &I) const; 156 157 bool selectBitreverse(Register ResVReg, const SPIRVType *ResType, 158 MachineInstr &I) const; 159 160 bool selectConstVector(Register ResVReg, const SPIRVType *ResType, 161 MachineInstr &I) const; 162 bool selectSplatVector(Register ResVReg, const SPIRVType *ResType, 163 MachineInstr &I) const; 164 165 bool selectCmp(Register ResVReg, const SPIRVType *ResType, 166 unsigned comparisonOpcode, MachineInstr &I) const; 167 168 bool selectICmp(Register ResVReg, const SPIRVType *ResType, 169 MachineInstr &I) const; 170 bool selectFCmp(Register ResVReg, const SPIRVType *ResType, 171 MachineInstr &I) const; 172 173 bool selectFmix(Register ResVReg, const SPIRVType *ResType, 174 MachineInstr &I) const; 175 176 bool selectRsqrt(Register ResVReg, const SPIRVType *ResType, 177 MachineInstr &I) const; 178 179 void renderImm32(MachineInstrBuilder &MIB, const MachineInstr &I, 180 int OpIdx) const; 181 void renderFImm32(MachineInstrBuilder &MIB, const MachineInstr &I, 182 int OpIdx) const; 183 184 bool selectConst(Register ResVReg, const SPIRVType *ResType, const APInt &Imm, 185 MachineInstr &I) const; 186 187 bool selectSelect(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, 188 bool IsSigned) const; 189 bool selectIToF(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, 190 bool IsSigned, unsigned Opcode) const; 191 bool selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, 192 bool IsSigned) const; 193 194 bool selectTrunc(Register ResVReg, const SPIRVType *ResType, 195 MachineInstr &I) const; 196 197 bool selectIntToBool(Register IntReg, Register ResVReg, MachineInstr &I, 198 const SPIRVType *intTy, const SPIRVType *boolTy) const; 199 200 bool selectOpUndef(Register ResVReg, const SPIRVType *ResType, 201 MachineInstr &I) const; 202 bool selectFreeze(Register ResVReg, const SPIRVType *ResType, 203 MachineInstr &I) const; 204 bool selectIntrinsic(Register ResVReg, const SPIRVType *ResType, 205 MachineInstr &I) const; 206 bool selectExtractVal(Register ResVReg, const SPIRVType *ResType, 207 MachineInstr &I) const; 208 bool selectInsertVal(Register ResVReg, const SPIRVType *ResType, 209 MachineInstr &I) const; 210 bool selectExtractElt(Register ResVReg, const SPIRVType *ResType, 211 MachineInstr &I) const; 212 bool selectInsertElt(Register ResVReg, const SPIRVType *ResType, 213 MachineInstr &I) const; 214 bool selectGEP(Register ResVReg, const SPIRVType *ResType, 215 MachineInstr &I) const; 216 217 bool selectFrameIndex(Register ResVReg, const SPIRVType *ResType, 218 MachineInstr &I) const; 219 bool selectAllocaArray(Register ResVReg, const SPIRVType *ResType, 220 MachineInstr &I) const; 221 222 bool selectBranch(MachineInstr &I) const; 223 bool selectBranchCond(MachineInstr &I) const; 224 225 bool selectPhi(Register ResVReg, const SPIRVType *ResType, 226 MachineInstr &I) const; 227 228 bool selectExtInst(Register ResVReg, const SPIRVType *ResType, 229 MachineInstr &I, CL::OpenCLExtInst CLInst) const; 230 bool selectExtInst(Register ResVReg, const SPIRVType *ResType, 231 MachineInstr &I, CL::OpenCLExtInst CLInst, 232 GL::GLSLExtInst GLInst) const; 233 bool selectExtInst(Register ResVReg, const SPIRVType *ResType, 234 MachineInstr &I, const ExtInstList &ExtInsts) const; 235 236 bool selectLog10(Register ResVReg, const SPIRVType *ResType, 237 MachineInstr &I) const; 238 239 bool selectSpvThreadId(Register ResVReg, const SPIRVType *ResType, 240 MachineInstr &I) const; 241 242 bool selectUnmergeValues(MachineInstr &I) const; 243 244 Register buildI32Constant(uint32_t Val, MachineInstr &I, 245 const SPIRVType *ResType = nullptr) const; 246 247 Register buildZerosVal(const SPIRVType *ResType, MachineInstr &I) const; 248 Register buildZerosValF(const SPIRVType *ResType, MachineInstr &I) const; 249 Register buildOnesVal(bool AllOnes, const SPIRVType *ResType, 250 MachineInstr &I) const; 251 252 bool wrapIntoSpecConstantOp(MachineInstr &I, 253 SmallVector<Register> &CompositeArgs) const; 254 }; 255 256 } // end anonymous namespace 257 258 #define GET_GLOBALISEL_IMPL 259 #include "SPIRVGenGlobalISel.inc" 260 #undef GET_GLOBALISEL_IMPL 261 262 SPIRVInstructionSelector::SPIRVInstructionSelector(const SPIRVTargetMachine &TM, 263 const SPIRVSubtarget &ST, 264 const RegisterBankInfo &RBI) 265 : InstructionSelector(), STI(ST), TII(*ST.getInstrInfo()), 266 TRI(*ST.getRegisterInfo()), RBI(RBI), GR(*ST.getSPIRVGlobalRegistry()), 267 #define GET_GLOBALISEL_PREDICATES_INIT 268 #include "SPIRVGenGlobalISel.inc" 269 #undef GET_GLOBALISEL_PREDICATES_INIT 270 #define GET_GLOBALISEL_TEMPORARIES_INIT 271 #include "SPIRVGenGlobalISel.inc" 272 #undef GET_GLOBALISEL_TEMPORARIES_INIT 273 { 274 } 275 276 void SPIRVInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits *KB, 277 CodeGenCoverage *CoverageInfo, 278 ProfileSummaryInfo *PSI, 279 BlockFrequencyInfo *BFI) { 280 MMI = &MF.getMMI().getObjFileInfo<SPIRVMachineModuleInfo>(); 281 MRI = &MF.getRegInfo(); 282 GR.setCurrentFunc(MF); 283 InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI); 284 } 285 286 static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI); 287 288 // Defined in SPIRVLegalizerInfo.cpp. 289 extern bool isTypeFoldingSupported(unsigned Opcode); 290 291 bool SPIRVInstructionSelector::select(MachineInstr &I) { 292 assert(I.getParent() && "Instruction should be in a basic block!"); 293 assert(I.getParent()->getParent() && "Instruction should be in a function!"); 294 295 Register Opcode = I.getOpcode(); 296 // If it's not a GMIR instruction, we've selected it already. 297 if (!isPreISelGenericOpcode(Opcode)) { 298 if (Opcode == SPIRV::ASSIGN_TYPE) { // These pseudos aren't needed any more. 299 Register DstReg = I.getOperand(0).getReg(); 300 Register SrcReg = I.getOperand(1).getReg(); 301 auto *Def = MRI->getVRegDef(SrcReg); 302 if (isTypeFoldingSupported(Def->getOpcode())) { 303 if (MRI->getType(DstReg).isPointer()) 304 MRI->setType(DstReg, LLT::scalar(32)); 305 bool Res = selectImpl(I, *CoverageInfo); 306 assert(Res || Def->getOpcode() == TargetOpcode::G_CONSTANT); 307 if (Res) 308 return Res; 309 } 310 MRI->replaceRegWith(SrcReg, DstReg); 311 I.removeFromParent(); 312 return true; 313 } else if (I.getNumDefs() == 1) { 314 // Make all vregs 32 bits (for SPIR-V IDs). 315 MRI->setType(I.getOperand(0).getReg(), LLT::scalar(32)); 316 } 317 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 318 } 319 320 if (I.getNumOperands() != I.getNumExplicitOperands()) { 321 LLVM_DEBUG(errs() << "Generic instr has unexpected implicit operands\n"); 322 return false; 323 } 324 325 // Common code for getting return reg+type, and removing selected instr 326 // from parent occurs here. Instr-specific selection happens in spvSelect(). 327 bool HasDefs = I.getNumDefs() > 0; 328 Register ResVReg = HasDefs ? I.getOperand(0).getReg() : Register(0); 329 SPIRVType *ResType = HasDefs ? GR.getSPIRVTypeForVReg(ResVReg) : nullptr; 330 assert(!HasDefs || ResType || I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE); 331 if (spvSelect(ResVReg, ResType, I)) { 332 if (HasDefs) // Make all vregs 32 bits (for SPIR-V IDs). 333 for (unsigned i = 0; i < I.getNumDefs(); ++i) 334 MRI->setType(I.getOperand(i).getReg(), LLT::scalar(32)); 335 I.removeFromParent(); 336 return true; 337 } 338 return false; 339 } 340 341 bool SPIRVInstructionSelector::spvSelect(Register ResVReg, 342 const SPIRVType *ResType, 343 MachineInstr &I) const { 344 const unsigned Opcode = I.getOpcode(); 345 if (isTypeFoldingSupported(Opcode) && Opcode != TargetOpcode::G_CONSTANT) 346 return selectImpl(I, *CoverageInfo); 347 switch (Opcode) { 348 case TargetOpcode::G_CONSTANT: 349 return selectConst(ResVReg, ResType, I.getOperand(1).getCImm()->getValue(), 350 I); 351 case TargetOpcode::G_GLOBAL_VALUE: 352 return selectGlobalValue(ResVReg, I); 353 case TargetOpcode::G_IMPLICIT_DEF: 354 return selectOpUndef(ResVReg, ResType, I); 355 case TargetOpcode::G_FREEZE: 356 return selectFreeze(ResVReg, ResType, I); 357 358 case TargetOpcode::G_INTRINSIC: 359 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: 360 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: 361 return selectIntrinsic(ResVReg, ResType, I); 362 case TargetOpcode::G_BITREVERSE: 363 return selectBitreverse(ResVReg, ResType, I); 364 365 case TargetOpcode::G_BUILD_VECTOR: 366 return selectConstVector(ResVReg, ResType, I); 367 case TargetOpcode::G_SPLAT_VECTOR: 368 return selectSplatVector(ResVReg, ResType, I); 369 370 case TargetOpcode::G_SHUFFLE_VECTOR: { 371 MachineBasicBlock &BB = *I.getParent(); 372 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorShuffle)) 373 .addDef(ResVReg) 374 .addUse(GR.getSPIRVTypeID(ResType)) 375 .addUse(I.getOperand(1).getReg()) 376 .addUse(I.getOperand(2).getReg()); 377 for (auto V : I.getOperand(3).getShuffleMask()) 378 MIB.addImm(V); 379 return MIB.constrainAllUses(TII, TRI, RBI); 380 } 381 case TargetOpcode::G_MEMMOVE: 382 case TargetOpcode::G_MEMCPY: 383 case TargetOpcode::G_MEMSET: 384 return selectMemOperation(ResVReg, I); 385 386 case TargetOpcode::G_ICMP: 387 return selectICmp(ResVReg, ResType, I); 388 case TargetOpcode::G_FCMP: 389 return selectFCmp(ResVReg, ResType, I); 390 391 case TargetOpcode::G_FRAME_INDEX: 392 return selectFrameIndex(ResVReg, ResType, I); 393 394 case TargetOpcode::G_LOAD: 395 return selectLoad(ResVReg, ResType, I); 396 case TargetOpcode::G_STORE: 397 return selectStore(I); 398 399 case TargetOpcode::G_BR: 400 return selectBranch(I); 401 case TargetOpcode::G_BRCOND: 402 return selectBranchCond(I); 403 404 case TargetOpcode::G_PHI: 405 return selectPhi(ResVReg, ResType, I); 406 407 case TargetOpcode::G_FPTOSI: 408 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToS); 409 case TargetOpcode::G_FPTOUI: 410 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToU); 411 412 case TargetOpcode::G_SITOFP: 413 return selectIToF(ResVReg, ResType, I, true, SPIRV::OpConvertSToF); 414 case TargetOpcode::G_UITOFP: 415 return selectIToF(ResVReg, ResType, I, false, SPIRV::OpConvertUToF); 416 417 case TargetOpcode::G_CTPOP: 418 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitCount); 419 case TargetOpcode::G_SMIN: 420 return selectExtInst(ResVReg, ResType, I, CL::s_min, GL::SMin); 421 case TargetOpcode::G_UMIN: 422 return selectExtInst(ResVReg, ResType, I, CL::u_min, GL::UMin); 423 424 case TargetOpcode::G_SMAX: 425 return selectExtInst(ResVReg, ResType, I, CL::s_max, GL::SMax); 426 case TargetOpcode::G_UMAX: 427 return selectExtInst(ResVReg, ResType, I, CL::u_max, GL::UMax); 428 429 case TargetOpcode::G_FMA: 430 return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma); 431 432 case TargetOpcode::G_FPOW: 433 return selectExtInst(ResVReg, ResType, I, CL::pow, GL::Pow); 434 case TargetOpcode::G_FPOWI: 435 return selectExtInst(ResVReg, ResType, I, CL::pown); 436 437 case TargetOpcode::G_FEXP: 438 return selectExtInst(ResVReg, ResType, I, CL::exp, GL::Exp); 439 case TargetOpcode::G_FEXP2: 440 return selectExtInst(ResVReg, ResType, I, CL::exp2, GL::Exp2); 441 442 case TargetOpcode::G_FLOG: 443 return selectExtInst(ResVReg, ResType, I, CL::log, GL::Log); 444 case TargetOpcode::G_FLOG2: 445 return selectExtInst(ResVReg, ResType, I, CL::log2, GL::Log2); 446 case TargetOpcode::G_FLOG10: 447 return selectLog10(ResVReg, ResType, I); 448 449 case TargetOpcode::G_FABS: 450 return selectExtInst(ResVReg, ResType, I, CL::fabs, GL::FAbs); 451 case TargetOpcode::G_ABS: 452 return selectExtInst(ResVReg, ResType, I, CL::s_abs, GL::SAbs); 453 454 case TargetOpcode::G_FMINNUM: 455 case TargetOpcode::G_FMINIMUM: 456 return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::NMin); 457 case TargetOpcode::G_FMAXNUM: 458 case TargetOpcode::G_FMAXIMUM: 459 return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::NMax); 460 461 case TargetOpcode::G_FCOPYSIGN: 462 return selectExtInst(ResVReg, ResType, I, CL::copysign); 463 464 case TargetOpcode::G_FCEIL: 465 return selectExtInst(ResVReg, ResType, I, CL::ceil, GL::Ceil); 466 case TargetOpcode::G_FFLOOR: 467 return selectExtInst(ResVReg, ResType, I, CL::floor, GL::Floor); 468 469 case TargetOpcode::G_FCOS: 470 return selectExtInst(ResVReg, ResType, I, CL::cos, GL::Cos); 471 case TargetOpcode::G_FSIN: 472 return selectExtInst(ResVReg, ResType, I, CL::sin, GL::Sin); 473 case TargetOpcode::G_FTAN: 474 return selectExtInst(ResVReg, ResType, I, CL::tan, GL::Tan); 475 case TargetOpcode::G_FACOS: 476 return selectExtInst(ResVReg, ResType, I, CL::acos, GL::Acos); 477 case TargetOpcode::G_FASIN: 478 return selectExtInst(ResVReg, ResType, I, CL::asin, GL::Asin); 479 case TargetOpcode::G_FATAN: 480 return selectExtInst(ResVReg, ResType, I, CL::atan, GL::Atan); 481 case TargetOpcode::G_FCOSH: 482 return selectExtInst(ResVReg, ResType, I, CL::cosh, GL::Cosh); 483 case TargetOpcode::G_FSINH: 484 return selectExtInst(ResVReg, ResType, I, CL::sinh, GL::Sinh); 485 case TargetOpcode::G_FTANH: 486 return selectExtInst(ResVReg, ResType, I, CL::tanh, GL::Tanh); 487 488 case TargetOpcode::G_FSQRT: 489 return selectExtInst(ResVReg, ResType, I, CL::sqrt, GL::Sqrt); 490 491 case TargetOpcode::G_CTTZ: 492 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 493 return selectExtInst(ResVReg, ResType, I, CL::ctz); 494 case TargetOpcode::G_CTLZ: 495 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 496 return selectExtInst(ResVReg, ResType, I, CL::clz); 497 498 case TargetOpcode::G_INTRINSIC_ROUND: 499 return selectExtInst(ResVReg, ResType, I, CL::round, GL::Round); 500 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 501 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven); 502 case TargetOpcode::G_INTRINSIC_TRUNC: 503 return selectExtInst(ResVReg, ResType, I, CL::trunc, GL::Trunc); 504 case TargetOpcode::G_FRINT: 505 case TargetOpcode::G_FNEARBYINT: 506 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven); 507 508 case TargetOpcode::G_SMULH: 509 return selectExtInst(ResVReg, ResType, I, CL::s_mul_hi); 510 case TargetOpcode::G_UMULH: 511 return selectExtInst(ResVReg, ResType, I, CL::u_mul_hi); 512 513 case TargetOpcode::G_SADDSAT: 514 return selectExtInst(ResVReg, ResType, I, CL::s_add_sat); 515 case TargetOpcode::G_UADDSAT: 516 return selectExtInst(ResVReg, ResType, I, CL::u_add_sat); 517 case TargetOpcode::G_SSUBSAT: 518 return selectExtInst(ResVReg, ResType, I, CL::s_sub_sat); 519 case TargetOpcode::G_USUBSAT: 520 return selectExtInst(ResVReg, ResType, I, CL::u_sub_sat); 521 522 case TargetOpcode::G_SEXT: 523 return selectExt(ResVReg, ResType, I, true); 524 case TargetOpcode::G_ANYEXT: 525 case TargetOpcode::G_ZEXT: 526 return selectExt(ResVReg, ResType, I, false); 527 case TargetOpcode::G_TRUNC: 528 return selectTrunc(ResVReg, ResType, I); 529 case TargetOpcode::G_FPTRUNC: 530 case TargetOpcode::G_FPEXT: 531 return selectUnOp(ResVReg, ResType, I, SPIRV::OpFConvert); 532 533 case TargetOpcode::G_PTRTOINT: 534 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertPtrToU); 535 case TargetOpcode::G_INTTOPTR: 536 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertUToPtr); 537 case TargetOpcode::G_BITCAST: 538 return selectBitcast(ResVReg, ResType, I); 539 case TargetOpcode::G_ADDRSPACE_CAST: 540 return selectAddrSpaceCast(ResVReg, ResType, I); 541 case TargetOpcode::G_PTR_ADD: { 542 // Currently, we get G_PTR_ADD only as a result of translating 543 // global variables, initialized with constant expressions like GV + Const 544 // (see test opencl/basic/progvar_prog_scope_init.ll). 545 // TODO: extend the handler once we have other cases. 546 assert(I.getOperand(1).isReg() && I.getOperand(2).isReg()); 547 Register GV = I.getOperand(1).getReg(); 548 MachineRegisterInfo::def_instr_iterator II = MRI->def_instr_begin(GV); 549 (void)II; 550 assert(((*II).getOpcode() == TargetOpcode::G_GLOBAL_VALUE || 551 (*II).getOpcode() == TargetOpcode::COPY || 552 (*II).getOpcode() == SPIRV::OpVariable) && 553 isImm(I.getOperand(2), MRI)); 554 Register Idx = buildZerosVal(GR.getOrCreateSPIRVIntegerType(32, I, TII), I); 555 MachineBasicBlock &BB = *I.getParent(); 556 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) 557 .addDef(ResVReg) 558 .addUse(GR.getSPIRVTypeID(ResType)) 559 .addImm(static_cast<uint32_t>( 560 SPIRV::Opcode::InBoundsPtrAccessChain)) 561 .addUse(GV) 562 .addUse(Idx) 563 .addUse(I.getOperand(2).getReg()); 564 return MIB.constrainAllUses(TII, TRI, RBI); 565 } 566 567 case TargetOpcode::G_ATOMICRMW_OR: 568 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicOr); 569 case TargetOpcode::G_ATOMICRMW_ADD: 570 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicIAdd); 571 case TargetOpcode::G_ATOMICRMW_AND: 572 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicAnd); 573 case TargetOpcode::G_ATOMICRMW_MAX: 574 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMax); 575 case TargetOpcode::G_ATOMICRMW_MIN: 576 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMin); 577 case TargetOpcode::G_ATOMICRMW_SUB: 578 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicISub); 579 case TargetOpcode::G_ATOMICRMW_XOR: 580 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicXor); 581 case TargetOpcode::G_ATOMICRMW_UMAX: 582 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMax); 583 case TargetOpcode::G_ATOMICRMW_UMIN: 584 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMin); 585 case TargetOpcode::G_ATOMICRMW_XCHG: 586 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicExchange); 587 case TargetOpcode::G_ATOMIC_CMPXCHG: 588 return selectAtomicCmpXchg(ResVReg, ResType, I); 589 590 case TargetOpcode::G_ATOMICRMW_FADD: 591 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT); 592 case TargetOpcode::G_ATOMICRMW_FSUB: 593 // Translate G_ATOMICRMW_FSUB to OpAtomicFAddEXT with negative value operand 594 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT, 595 SPIRV::OpFNegate); 596 case TargetOpcode::G_ATOMICRMW_FMIN: 597 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMinEXT); 598 case TargetOpcode::G_ATOMICRMW_FMAX: 599 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMaxEXT); 600 601 case TargetOpcode::G_FENCE: 602 return selectFence(I); 603 604 case TargetOpcode::G_STACKSAVE: 605 return selectStackSave(ResVReg, ResType, I); 606 case TargetOpcode::G_STACKRESTORE: 607 return selectStackRestore(I); 608 609 case TargetOpcode::G_UNMERGE_VALUES: 610 return selectUnmergeValues(I); 611 612 default: 613 return false; 614 } 615 } 616 617 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, 618 const SPIRVType *ResType, 619 MachineInstr &I, 620 CL::OpenCLExtInst CLInst) const { 621 return selectExtInst(ResVReg, ResType, I, 622 {{SPIRV::InstructionSet::OpenCL_std, CLInst}}); 623 } 624 625 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, 626 const SPIRVType *ResType, 627 MachineInstr &I, 628 CL::OpenCLExtInst CLInst, 629 GL::GLSLExtInst GLInst) const { 630 ExtInstList ExtInsts = {{SPIRV::InstructionSet::OpenCL_std, CLInst}, 631 {SPIRV::InstructionSet::GLSL_std_450, GLInst}}; 632 return selectExtInst(ResVReg, ResType, I, ExtInsts); 633 } 634 635 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, 636 const SPIRVType *ResType, 637 MachineInstr &I, 638 const ExtInstList &Insts) const { 639 640 for (const auto &Ex : Insts) { 641 SPIRV::InstructionSet::InstructionSet Set = Ex.first; 642 uint32_t Opcode = Ex.second; 643 if (STI.canUseExtInstSet(Set)) { 644 MachineBasicBlock &BB = *I.getParent(); 645 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) 646 .addDef(ResVReg) 647 .addUse(GR.getSPIRVTypeID(ResType)) 648 .addImm(static_cast<uint32_t>(Set)) 649 .addImm(Opcode); 650 const unsigned NumOps = I.getNumOperands(); 651 for (unsigned i = 1; i < NumOps; ++i) 652 MIB.add(I.getOperand(i)); 653 return MIB.constrainAllUses(TII, TRI, RBI); 654 } 655 } 656 return false; 657 } 658 659 bool SPIRVInstructionSelector::selectUnOpWithSrc(Register ResVReg, 660 const SPIRVType *ResType, 661 MachineInstr &I, 662 Register SrcReg, 663 unsigned Opcode) const { 664 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) 665 .addDef(ResVReg) 666 .addUse(GR.getSPIRVTypeID(ResType)) 667 .addUse(SrcReg) 668 .constrainAllUses(TII, TRI, RBI); 669 } 670 671 bool SPIRVInstructionSelector::selectUnOp(Register ResVReg, 672 const SPIRVType *ResType, 673 MachineInstr &I, 674 unsigned Opcode) const { 675 if (STI.isOpenCLEnv() && I.getOperand(1).isReg()) { 676 Register SrcReg = I.getOperand(1).getReg(); 677 bool IsGV = false; 678 for (MachineRegisterInfo::def_instr_iterator DefIt = 679 MRI->def_instr_begin(SrcReg); 680 DefIt != MRI->def_instr_end(); DefIt = std::next(DefIt)) { 681 if ((*DefIt).getOpcode() == TargetOpcode::G_GLOBAL_VALUE) { 682 IsGV = true; 683 break; 684 } 685 } 686 if (IsGV) { 687 uint32_t SpecOpcode = 0; 688 switch (Opcode) { 689 case SPIRV::OpConvertPtrToU: 690 SpecOpcode = static_cast<uint32_t>(SPIRV::Opcode::ConvertPtrToU); 691 break; 692 case SPIRV::OpConvertUToPtr: 693 SpecOpcode = static_cast<uint32_t>(SPIRV::Opcode::ConvertUToPtr); 694 break; 695 } 696 if (SpecOpcode) 697 return BuildMI(*I.getParent(), I, I.getDebugLoc(), 698 TII.get(SPIRV::OpSpecConstantOp)) 699 .addDef(ResVReg) 700 .addUse(GR.getSPIRVTypeID(ResType)) 701 .addImm(SpecOpcode) 702 .addUse(SrcReg) 703 .constrainAllUses(TII, TRI, RBI); 704 } 705 } 706 return selectUnOpWithSrc(ResVReg, ResType, I, I.getOperand(1).getReg(), 707 Opcode); 708 } 709 710 bool SPIRVInstructionSelector::selectBitcast(Register ResVReg, 711 const SPIRVType *ResType, 712 MachineInstr &I) const { 713 Register OpReg = I.getOperand(1).getReg(); 714 SPIRVType *OpType = OpReg.isValid() ? GR.getSPIRVTypeForVReg(OpReg) : nullptr; 715 if (!GR.isBitcastCompatible(ResType, OpType)) 716 report_fatal_error("incompatible result and operand types in a bitcast"); 717 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitcast); 718 } 719 720 static SPIRV::Scope::Scope getScope(SyncScope::ID Ord, 721 SPIRVMachineModuleInfo *MMI) { 722 if (Ord == SyncScope::SingleThread || Ord == MMI->Work_ItemSSID) 723 return SPIRV::Scope::Invocation; 724 else if (Ord == SyncScope::System || Ord == MMI->DeviceSSID) 725 return SPIRV::Scope::Device; 726 else if (Ord == MMI->WorkGroupSSID) 727 return SPIRV::Scope::Workgroup; 728 else if (Ord == MMI->AllSVMDevicesSSID) 729 return SPIRV::Scope::CrossDevice; 730 else if (Ord == MMI->SubGroupSSID) 731 return SPIRV::Scope::Subgroup; 732 else 733 // OpenCL approach is: "The functions that do not have memory_scope argument 734 // have the same semantics as the corresponding functions with the 735 // memory_scope argument set to memory_scope_device." See ref.: // 736 // https://registry.khronos.org/OpenCL/specs/3.0-unified/html/OpenCL_C.html#atomic-functions 737 // In our case if the scope is unknown, assuming that SPIR-V code is to be 738 // consumed in an OpenCL environment, we use the same approach and set the 739 // scope to memory_scope_device. 740 return SPIRV::Scope::Device; 741 } 742 743 static void addMemoryOperands(MachineMemOperand *MemOp, 744 MachineInstrBuilder &MIB) { 745 uint32_t SpvMemOp = static_cast<uint32_t>(SPIRV::MemoryOperand::None); 746 if (MemOp->isVolatile()) 747 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Volatile); 748 if (MemOp->isNonTemporal()) 749 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Nontemporal); 750 if (MemOp->getAlign().value()) 751 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Aligned); 752 753 if (SpvMemOp != static_cast<uint32_t>(SPIRV::MemoryOperand::None)) { 754 MIB.addImm(SpvMemOp); 755 if (SpvMemOp & static_cast<uint32_t>(SPIRV::MemoryOperand::Aligned)) 756 MIB.addImm(MemOp->getAlign().value()); 757 } 758 } 759 760 static void addMemoryOperands(uint64_t Flags, MachineInstrBuilder &MIB) { 761 uint32_t SpvMemOp = static_cast<uint32_t>(SPIRV::MemoryOperand::None); 762 if (Flags & MachineMemOperand::Flags::MOVolatile) 763 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Volatile); 764 if (Flags & MachineMemOperand::Flags::MONonTemporal) 765 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Nontemporal); 766 767 if (SpvMemOp != static_cast<uint32_t>(SPIRV::MemoryOperand::None)) 768 MIB.addImm(SpvMemOp); 769 } 770 771 bool SPIRVInstructionSelector::selectLoad(Register ResVReg, 772 const SPIRVType *ResType, 773 MachineInstr &I) const { 774 unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0; 775 Register Ptr = I.getOperand(1 + OpOffset).getReg(); 776 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) 777 .addDef(ResVReg) 778 .addUse(GR.getSPIRVTypeID(ResType)) 779 .addUse(Ptr); 780 if (!I.getNumMemOperands()) { 781 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS || 782 I.getOpcode() == 783 TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS); 784 addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB); 785 } else { 786 addMemoryOperands(*I.memoperands_begin(), MIB); 787 } 788 return MIB.constrainAllUses(TII, TRI, RBI); 789 } 790 791 bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const { 792 unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0; 793 Register StoreVal = I.getOperand(0 + OpOffset).getReg(); 794 Register Ptr = I.getOperand(1 + OpOffset).getReg(); 795 MachineBasicBlock &BB = *I.getParent(); 796 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpStore)) 797 .addUse(Ptr) 798 .addUse(StoreVal); 799 if (!I.getNumMemOperands()) { 800 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS || 801 I.getOpcode() == 802 TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS); 803 addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB); 804 } else { 805 addMemoryOperands(*I.memoperands_begin(), MIB); 806 } 807 return MIB.constrainAllUses(TII, TRI, RBI); 808 } 809 810 bool SPIRVInstructionSelector::selectStackSave(Register ResVReg, 811 const SPIRVType *ResType, 812 MachineInstr &I) const { 813 if (!STI.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array)) 814 report_fatal_error( 815 "llvm.stacksave intrinsic: this instruction requires the following " 816 "SPIR-V extension: SPV_INTEL_variable_length_array", 817 false); 818 MachineBasicBlock &BB = *I.getParent(); 819 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSaveMemoryINTEL)) 820 .addDef(ResVReg) 821 .addUse(GR.getSPIRVTypeID(ResType)) 822 .constrainAllUses(TII, TRI, RBI); 823 } 824 825 bool SPIRVInstructionSelector::selectStackRestore(MachineInstr &I) const { 826 if (!STI.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array)) 827 report_fatal_error( 828 "llvm.stackrestore intrinsic: this instruction requires the following " 829 "SPIR-V extension: SPV_INTEL_variable_length_array", 830 false); 831 if (!I.getOperand(0).isReg()) 832 return false; 833 MachineBasicBlock &BB = *I.getParent(); 834 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpRestoreMemoryINTEL)) 835 .addUse(I.getOperand(0).getReg()) 836 .constrainAllUses(TII, TRI, RBI); 837 } 838 839 bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg, 840 MachineInstr &I) const { 841 MachineBasicBlock &BB = *I.getParent(); 842 Register SrcReg = I.getOperand(1).getReg(); 843 if (I.getOpcode() == TargetOpcode::G_MEMSET) { 844 assert(I.getOperand(1).isReg() && I.getOperand(2).isReg()); 845 unsigned Val = getIConstVal(I.getOperand(1).getReg(), MRI); 846 unsigned Num = getIConstVal(I.getOperand(2).getReg(), MRI); 847 SPIRVType *ValTy = GR.getOrCreateSPIRVIntegerType(8, I, TII); 848 SPIRVType *ArrTy = GR.getOrCreateSPIRVArrayType(ValTy, Num, I, TII); 849 Register Const = GR.getOrCreateConsIntArray(Val, I, ArrTy, TII); 850 SPIRVType *VarTy = GR.getOrCreateSPIRVPointerType( 851 ArrTy, I, TII, SPIRV::StorageClass::UniformConstant); 852 // TODO: check if we have such GV, add init, use buildGlobalVariable. 853 Function &CurFunction = GR.CurMF->getFunction(); 854 Type *LLVMArrTy = 855 ArrayType::get(IntegerType::get(CurFunction.getContext(), 8), Num); 856 // Module takes ownership of the global var. 857 GlobalVariable *GV = new GlobalVariable(*CurFunction.getParent(), LLVMArrTy, 858 true, GlobalValue::InternalLinkage, 859 Constant::getNullValue(LLVMArrTy)); 860 Register VarReg = MRI->createGenericVirtualRegister(LLT::scalar(32)); 861 GR.add(GV, GR.CurMF, VarReg); 862 863 buildOpDecorate(VarReg, I, TII, SPIRV::Decoration::Constant, {}); 864 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpVariable)) 865 .addDef(VarReg) 866 .addUse(GR.getSPIRVTypeID(VarTy)) 867 .addImm(SPIRV::StorageClass::UniformConstant) 868 .addUse(Const) 869 .constrainAllUses(TII, TRI, RBI); 870 SPIRVType *SourceTy = GR.getOrCreateSPIRVPointerType( 871 ValTy, I, TII, SPIRV::StorageClass::UniformConstant); 872 SrcReg = MRI->createGenericVirtualRegister(LLT::scalar(32)); 873 selectUnOpWithSrc(SrcReg, SourceTy, I, VarReg, SPIRV::OpBitcast); 874 } 875 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCopyMemorySized)) 876 .addUse(I.getOperand(0).getReg()) 877 .addUse(SrcReg) 878 .addUse(I.getOperand(2).getReg()); 879 if (I.getNumMemOperands()) 880 addMemoryOperands(*I.memoperands_begin(), MIB); 881 bool Result = MIB.constrainAllUses(TII, TRI, RBI); 882 if (ResVReg.isValid() && ResVReg != MIB->getOperand(0).getReg()) 883 BuildMI(BB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY), ResVReg) 884 .addUse(MIB->getOperand(0).getReg()); 885 return Result; 886 } 887 888 bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, 889 const SPIRVType *ResType, 890 MachineInstr &I, 891 unsigned NewOpcode, 892 unsigned NegateOpcode) const { 893 assert(I.hasOneMemOperand()); 894 const MachineMemOperand *MemOp = *I.memoperands_begin(); 895 uint32_t Scope = 896 static_cast<uint32_t>(getScope(MemOp->getSyncScopeID(), MMI)); 897 Register ScopeReg = buildI32Constant(Scope, I); 898 899 Register Ptr = I.getOperand(1).getReg(); 900 // TODO: Changed as it's implemented in the translator. See test/atomicrmw.ll 901 // auto ScSem = 902 // getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr)); 903 AtomicOrdering AO = MemOp->getSuccessOrdering(); 904 uint32_t MemSem = static_cast<uint32_t>(getMemSemantics(AO)); 905 Register MemSemReg = buildI32Constant(MemSem /*| ScSem*/, I); 906 907 bool Result = false; 908 Register ValueReg = I.getOperand(2).getReg(); 909 if (NegateOpcode != 0) { 910 // Translation with negative value operand is requested 911 Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); 912 Result |= selectUnOpWithSrc(TmpReg, ResType, I, ValueReg, NegateOpcode); 913 ValueReg = TmpReg; 914 } 915 916 Result |= BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) 917 .addDef(ResVReg) 918 .addUse(GR.getSPIRVTypeID(ResType)) 919 .addUse(Ptr) 920 .addUse(ScopeReg) 921 .addUse(MemSemReg) 922 .addUse(ValueReg) 923 .constrainAllUses(TII, TRI, RBI); 924 return Result; 925 } 926 927 bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const { 928 unsigned ArgI = I.getNumOperands() - 1; 929 Register SrcReg = 930 I.getOperand(ArgI).isReg() ? I.getOperand(ArgI).getReg() : Register(0); 931 SPIRVType *DefType = 932 SrcReg.isValid() ? GR.getSPIRVTypeForVReg(SrcReg) : nullptr; 933 if (!DefType || DefType->getOpcode() != SPIRV::OpTypeVector) 934 report_fatal_error( 935 "cannot select G_UNMERGE_VALUES with a non-vector argument"); 936 937 SPIRVType *ScalarType = 938 GR.getSPIRVTypeForVReg(DefType->getOperand(1).getReg()); 939 MachineBasicBlock &BB = *I.getParent(); 940 bool Res = false; 941 for (unsigned i = 0; i < I.getNumDefs(); ++i) { 942 Register ResVReg = I.getOperand(i).getReg(); 943 SPIRVType *ResType = GR.getSPIRVTypeForVReg(ResVReg); 944 if (!ResType) { 945 // There was no "assign type" actions, let's fix this now 946 ResType = ScalarType; 947 MRI->setRegClass(ResVReg, &SPIRV::IDRegClass); 948 MRI->setType(ResVReg, LLT::scalar(GR.getScalarOrVectorBitWidth(ResType))); 949 GR.assignSPIRVTypeToVReg(ResType, ResVReg, *GR.CurMF); 950 } 951 auto MIB = 952 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) 953 .addDef(ResVReg) 954 .addUse(GR.getSPIRVTypeID(ResType)) 955 .addUse(SrcReg) 956 .addImm(static_cast<int64_t>(i)); 957 Res |= MIB.constrainAllUses(TII, TRI, RBI); 958 } 959 return Res; 960 } 961 962 bool SPIRVInstructionSelector::selectFence(MachineInstr &I) const { 963 AtomicOrdering AO = AtomicOrdering(I.getOperand(0).getImm()); 964 uint32_t MemSem = static_cast<uint32_t>(getMemSemantics(AO)); 965 Register MemSemReg = buildI32Constant(MemSem, I); 966 SyncScope::ID Ord = SyncScope::ID(I.getOperand(1).getImm()); 967 uint32_t Scope = static_cast<uint32_t>(getScope(Ord, MMI)); 968 Register ScopeReg = buildI32Constant(Scope, I); 969 MachineBasicBlock &BB = *I.getParent(); 970 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpMemoryBarrier)) 971 .addUse(ScopeReg) 972 .addUse(MemSemReg) 973 .constrainAllUses(TII, TRI, RBI); 974 } 975 976 bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg, 977 const SPIRVType *ResType, 978 MachineInstr &I) const { 979 Register ScopeReg; 980 Register MemSemEqReg; 981 Register MemSemNeqReg; 982 Register Ptr = I.getOperand(2).getReg(); 983 if (!isa<GIntrinsic>(I)) { 984 assert(I.hasOneMemOperand()); 985 const MachineMemOperand *MemOp = *I.memoperands_begin(); 986 unsigned Scope = 987 static_cast<uint32_t>(getScope(MemOp->getSyncScopeID(), MMI)); 988 ScopeReg = buildI32Constant(Scope, I); 989 990 unsigned ScSem = static_cast<uint32_t>( 991 getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr))); 992 AtomicOrdering AO = MemOp->getSuccessOrdering(); 993 unsigned MemSemEq = static_cast<uint32_t>(getMemSemantics(AO)) | ScSem; 994 MemSemEqReg = buildI32Constant(MemSemEq, I); 995 AtomicOrdering FO = MemOp->getFailureOrdering(); 996 unsigned MemSemNeq = static_cast<uint32_t>(getMemSemantics(FO)) | ScSem; 997 MemSemNeqReg = 998 MemSemEq == MemSemNeq ? MemSemEqReg : buildI32Constant(MemSemNeq, I); 999 } else { 1000 ScopeReg = I.getOperand(5).getReg(); 1001 MemSemEqReg = I.getOperand(6).getReg(); 1002 MemSemNeqReg = I.getOperand(7).getReg(); 1003 } 1004 1005 Register Cmp = I.getOperand(3).getReg(); 1006 Register Val = I.getOperand(4).getReg(); 1007 SPIRVType *SpvValTy = GR.getSPIRVTypeForVReg(Val); 1008 Register ACmpRes = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1009 const DebugLoc &DL = I.getDebugLoc(); 1010 bool Result = 1011 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpAtomicCompareExchange)) 1012 .addDef(ACmpRes) 1013 .addUse(GR.getSPIRVTypeID(SpvValTy)) 1014 .addUse(Ptr) 1015 .addUse(ScopeReg) 1016 .addUse(MemSemEqReg) 1017 .addUse(MemSemNeqReg) 1018 .addUse(Val) 1019 .addUse(Cmp) 1020 .constrainAllUses(TII, TRI, RBI); 1021 Register CmpSuccReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1022 SPIRVType *BoolTy = GR.getOrCreateSPIRVBoolType(I, TII); 1023 Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpIEqual)) 1024 .addDef(CmpSuccReg) 1025 .addUse(GR.getSPIRVTypeID(BoolTy)) 1026 .addUse(ACmpRes) 1027 .addUse(Cmp) 1028 .constrainAllUses(TII, TRI, RBI); 1029 Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1030 Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) 1031 .addDef(TmpReg) 1032 .addUse(GR.getSPIRVTypeID(ResType)) 1033 .addUse(ACmpRes) 1034 .addUse(GR.getOrCreateUndef(I, ResType, TII)) 1035 .addImm(0) 1036 .constrainAllUses(TII, TRI, RBI); 1037 Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) 1038 .addDef(ResVReg) 1039 .addUse(GR.getSPIRVTypeID(ResType)) 1040 .addUse(CmpSuccReg) 1041 .addUse(TmpReg) 1042 .addImm(1) 1043 .constrainAllUses(TII, TRI, RBI); 1044 return Result; 1045 } 1046 1047 static bool isGenericCastablePtr(SPIRV::StorageClass::StorageClass SC) { 1048 switch (SC) { 1049 case SPIRV::StorageClass::Workgroup: 1050 case SPIRV::StorageClass::CrossWorkgroup: 1051 case SPIRV::StorageClass::Function: 1052 return true; 1053 default: 1054 return false; 1055 } 1056 } 1057 1058 static bool isUSMStorageClass(SPIRV::StorageClass::StorageClass SC) { 1059 switch (SC) { 1060 case SPIRV::StorageClass::DeviceOnlyINTEL: 1061 case SPIRV::StorageClass::HostOnlyINTEL: 1062 return true; 1063 default: 1064 return false; 1065 } 1066 } 1067 1068 // In SPIR-V address space casting can only happen to and from the Generic 1069 // storage class. We can also only cast Workgroup, CrossWorkgroup, or Function 1070 // pointers to and from Generic pointers. As such, we can convert e.g. from 1071 // Workgroup to Function by going via a Generic pointer as an intermediary. All 1072 // other combinations can only be done by a bitcast, and are probably not safe. 1073 bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg, 1074 const SPIRVType *ResType, 1075 MachineInstr &I) const { 1076 // If the AddrSpaceCast user is single and in OpConstantComposite or 1077 // OpVariable, we should select OpSpecConstantOp. 1078 auto UIs = MRI->use_instructions(ResVReg); 1079 if (!UIs.empty() && ++UIs.begin() == UIs.end() && 1080 (UIs.begin()->getOpcode() == SPIRV::OpConstantComposite || 1081 UIs.begin()->getOpcode() == SPIRV::OpVariable || 1082 isSpvIntrinsic(*UIs.begin(), Intrinsic::spv_init_global))) { 1083 Register NewReg = I.getOperand(1).getReg(); 1084 MachineBasicBlock &BB = *I.getParent(); 1085 SPIRVType *SpvBaseTy = GR.getOrCreateSPIRVIntegerType(8, I, TII); 1086 ResType = GR.getOrCreateSPIRVPointerType(SpvBaseTy, I, TII, 1087 SPIRV::StorageClass::Generic); 1088 bool Result = 1089 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) 1090 .addDef(ResVReg) 1091 .addUse(GR.getSPIRVTypeID(ResType)) 1092 .addImm(static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric)) 1093 .addUse(NewReg) 1094 .constrainAllUses(TII, TRI, RBI); 1095 return Result; 1096 } 1097 Register SrcPtr = I.getOperand(1).getReg(); 1098 SPIRVType *SrcPtrTy = GR.getSPIRVTypeForVReg(SrcPtr); 1099 SPIRV::StorageClass::StorageClass SrcSC = GR.getPointerStorageClass(SrcPtr); 1100 SPIRV::StorageClass::StorageClass DstSC = GR.getPointerStorageClass(ResVReg); 1101 1102 // don't generate a cast between identical storage classes 1103 if (SrcSC == DstSC) 1104 return BuildMI(*I.getParent(), I, I.getDebugLoc(), 1105 TII.get(TargetOpcode::COPY)) 1106 .addDef(ResVReg) 1107 .addUse(SrcPtr) 1108 .constrainAllUses(TII, TRI, RBI); 1109 1110 // Casting from an eligible pointer to Generic. 1111 if (DstSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(SrcSC)) 1112 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric); 1113 // Casting from Generic to an eligible pointer. 1114 if (SrcSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(DstSC)) 1115 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr); 1116 // Casting between 2 eligible pointers using Generic as an intermediary. 1117 if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) { 1118 Register Tmp = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1119 SPIRVType *GenericPtrTy = GR.getOrCreateSPIRVPointerType( 1120 GR.getPointeeType(SrcPtrTy), I, TII, SPIRV::StorageClass::Generic); 1121 MachineBasicBlock &BB = *I.getParent(); 1122 const DebugLoc &DL = I.getDebugLoc(); 1123 bool Success = BuildMI(BB, I, DL, TII.get(SPIRV::OpPtrCastToGeneric)) 1124 .addDef(Tmp) 1125 .addUse(GR.getSPIRVTypeID(GenericPtrTy)) 1126 .addUse(SrcPtr) 1127 .constrainAllUses(TII, TRI, RBI); 1128 return Success && BuildMI(BB, I, DL, TII.get(SPIRV::OpGenericCastToPtr)) 1129 .addDef(ResVReg) 1130 .addUse(GR.getSPIRVTypeID(ResType)) 1131 .addUse(Tmp) 1132 .constrainAllUses(TII, TRI, RBI); 1133 } 1134 1135 // Check if instructions from the SPV_INTEL_usm_storage_classes extension may 1136 // be applied 1137 if (isUSMStorageClass(SrcSC) && DstSC == SPIRV::StorageClass::CrossWorkgroup) 1138 return selectUnOp(ResVReg, ResType, I, 1139 SPIRV::OpPtrCastToCrossWorkgroupINTEL); 1140 if (SrcSC == SPIRV::StorageClass::CrossWorkgroup && isUSMStorageClass(DstSC)) 1141 return selectUnOp(ResVReg, ResType, I, 1142 SPIRV::OpCrossWorkgroupCastToPtrINTEL); 1143 if (isUSMStorageClass(SrcSC) && DstSC == SPIRV::StorageClass::Generic) 1144 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric); 1145 if (SrcSC == SPIRV::StorageClass::Generic && isUSMStorageClass(DstSC)) 1146 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr); 1147 1148 // Bitcast for pointers requires that the address spaces must match 1149 return false; 1150 } 1151 1152 static unsigned getFCmpOpcode(unsigned PredNum) { 1153 auto Pred = static_cast<CmpInst::Predicate>(PredNum); 1154 switch (Pred) { 1155 case CmpInst::FCMP_OEQ: 1156 return SPIRV::OpFOrdEqual; 1157 case CmpInst::FCMP_OGE: 1158 return SPIRV::OpFOrdGreaterThanEqual; 1159 case CmpInst::FCMP_OGT: 1160 return SPIRV::OpFOrdGreaterThan; 1161 case CmpInst::FCMP_OLE: 1162 return SPIRV::OpFOrdLessThanEqual; 1163 case CmpInst::FCMP_OLT: 1164 return SPIRV::OpFOrdLessThan; 1165 case CmpInst::FCMP_ONE: 1166 return SPIRV::OpFOrdNotEqual; 1167 case CmpInst::FCMP_ORD: 1168 return SPIRV::OpOrdered; 1169 case CmpInst::FCMP_UEQ: 1170 return SPIRV::OpFUnordEqual; 1171 case CmpInst::FCMP_UGE: 1172 return SPIRV::OpFUnordGreaterThanEqual; 1173 case CmpInst::FCMP_UGT: 1174 return SPIRV::OpFUnordGreaterThan; 1175 case CmpInst::FCMP_ULE: 1176 return SPIRV::OpFUnordLessThanEqual; 1177 case CmpInst::FCMP_ULT: 1178 return SPIRV::OpFUnordLessThan; 1179 case CmpInst::FCMP_UNE: 1180 return SPIRV::OpFUnordNotEqual; 1181 case CmpInst::FCMP_UNO: 1182 return SPIRV::OpUnordered; 1183 default: 1184 llvm_unreachable("Unknown predicate type for FCmp"); 1185 } 1186 } 1187 1188 static unsigned getICmpOpcode(unsigned PredNum) { 1189 auto Pred = static_cast<CmpInst::Predicate>(PredNum); 1190 switch (Pred) { 1191 case CmpInst::ICMP_EQ: 1192 return SPIRV::OpIEqual; 1193 case CmpInst::ICMP_NE: 1194 return SPIRV::OpINotEqual; 1195 case CmpInst::ICMP_SGE: 1196 return SPIRV::OpSGreaterThanEqual; 1197 case CmpInst::ICMP_SGT: 1198 return SPIRV::OpSGreaterThan; 1199 case CmpInst::ICMP_SLE: 1200 return SPIRV::OpSLessThanEqual; 1201 case CmpInst::ICMP_SLT: 1202 return SPIRV::OpSLessThan; 1203 case CmpInst::ICMP_UGE: 1204 return SPIRV::OpUGreaterThanEqual; 1205 case CmpInst::ICMP_UGT: 1206 return SPIRV::OpUGreaterThan; 1207 case CmpInst::ICMP_ULE: 1208 return SPIRV::OpULessThanEqual; 1209 case CmpInst::ICMP_ULT: 1210 return SPIRV::OpULessThan; 1211 default: 1212 llvm_unreachable("Unknown predicate type for ICmp"); 1213 } 1214 } 1215 1216 static unsigned getPtrCmpOpcode(unsigned Pred) { 1217 switch (static_cast<CmpInst::Predicate>(Pred)) { 1218 case CmpInst::ICMP_EQ: 1219 return SPIRV::OpPtrEqual; 1220 case CmpInst::ICMP_NE: 1221 return SPIRV::OpPtrNotEqual; 1222 default: 1223 llvm_unreachable("Unknown predicate type for pointer comparison"); 1224 } 1225 } 1226 1227 // Return the logical operation, or abort if none exists. 1228 static unsigned getBoolCmpOpcode(unsigned PredNum) { 1229 auto Pred = static_cast<CmpInst::Predicate>(PredNum); 1230 switch (Pred) { 1231 case CmpInst::ICMP_EQ: 1232 return SPIRV::OpLogicalEqual; 1233 case CmpInst::ICMP_NE: 1234 return SPIRV::OpLogicalNotEqual; 1235 default: 1236 llvm_unreachable("Unknown predicate type for Bool comparison"); 1237 } 1238 } 1239 1240 bool SPIRVInstructionSelector::selectAnyOrAll(Register ResVReg, 1241 const SPIRVType *ResType, 1242 MachineInstr &I, 1243 unsigned OpAnyOrAll) const { 1244 assert(I.getNumOperands() == 3); 1245 assert(I.getOperand(2).isReg()); 1246 MachineBasicBlock &BB = *I.getParent(); 1247 Register InputRegister = I.getOperand(2).getReg(); 1248 SPIRVType *InputType = GR.getSPIRVTypeForVReg(InputRegister); 1249 1250 if (!InputType) 1251 report_fatal_error("Input Type could not be determined."); 1252 1253 bool IsBoolTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeBool); 1254 bool IsVectorTy = InputType->getOpcode() == SPIRV::OpTypeVector; 1255 if (IsBoolTy && !IsVectorTy) { 1256 assert(ResVReg == I.getOperand(0).getReg()); 1257 return BuildMI(*I.getParent(), I, I.getDebugLoc(), 1258 TII.get(TargetOpcode::COPY)) 1259 .addDef(ResVReg) 1260 .addUse(InputRegister) 1261 .constrainAllUses(TII, TRI, RBI); 1262 } 1263 1264 bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat); 1265 unsigned SpirvNotEqualId = 1266 IsFloatTy ? SPIRV::OpFOrdNotEqual : SPIRV::OpINotEqual; 1267 SPIRVType *SpvBoolScalarTy = GR.getOrCreateSPIRVBoolType(I, TII); 1268 SPIRVType *SpvBoolTy = SpvBoolScalarTy; 1269 Register NotEqualReg = ResVReg; 1270 1271 if (IsVectorTy) { 1272 NotEqualReg = IsBoolTy ? InputRegister 1273 : MRI->createVirtualRegister(&SPIRV::IDRegClass); 1274 const unsigned NumElts = InputType->getOperand(2).getImm(); 1275 SpvBoolTy = GR.getOrCreateSPIRVVectorType(SpvBoolTy, NumElts, I, TII); 1276 } 1277 1278 if (!IsBoolTy) { 1279 Register ConstZeroReg = 1280 IsFloatTy ? buildZerosValF(InputType, I) : buildZerosVal(InputType, I); 1281 1282 BuildMI(BB, I, I.getDebugLoc(), TII.get(SpirvNotEqualId)) 1283 .addDef(NotEqualReg) 1284 .addUse(GR.getSPIRVTypeID(SpvBoolTy)) 1285 .addUse(InputRegister) 1286 .addUse(ConstZeroReg) 1287 .constrainAllUses(TII, TRI, RBI); 1288 } 1289 1290 if (!IsVectorTy) 1291 return true; 1292 1293 return BuildMI(BB, I, I.getDebugLoc(), TII.get(OpAnyOrAll)) 1294 .addDef(ResVReg) 1295 .addUse(GR.getSPIRVTypeID(SpvBoolScalarTy)) 1296 .addUse(NotEqualReg) 1297 .constrainAllUses(TII, TRI, RBI); 1298 } 1299 1300 bool SPIRVInstructionSelector::selectAll(Register ResVReg, 1301 const SPIRVType *ResType, 1302 MachineInstr &I) const { 1303 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAll); 1304 } 1305 1306 bool SPIRVInstructionSelector::selectAny(Register ResVReg, 1307 const SPIRVType *ResType, 1308 MachineInstr &I) const { 1309 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAny); 1310 } 1311 1312 bool SPIRVInstructionSelector::selectFmix(Register ResVReg, 1313 const SPIRVType *ResType, 1314 MachineInstr &I) const { 1315 1316 assert(I.getNumOperands() == 5); 1317 assert(I.getOperand(2).isReg()); 1318 assert(I.getOperand(3).isReg()); 1319 assert(I.getOperand(4).isReg()); 1320 MachineBasicBlock &BB = *I.getParent(); 1321 1322 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) 1323 .addDef(ResVReg) 1324 .addUse(GR.getSPIRVTypeID(ResType)) 1325 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) 1326 .addImm(GL::FMix) 1327 .addUse(I.getOperand(2).getReg()) 1328 .addUse(I.getOperand(3).getReg()) 1329 .addUse(I.getOperand(4).getReg()) 1330 .constrainAllUses(TII, TRI, RBI); 1331 } 1332 1333 bool SPIRVInstructionSelector::selectRsqrt(Register ResVReg, 1334 const SPIRVType *ResType, 1335 MachineInstr &I) const { 1336 1337 assert(I.getNumOperands() == 3); 1338 assert(I.getOperand(2).isReg()); 1339 MachineBasicBlock &BB = *I.getParent(); 1340 1341 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) 1342 .addDef(ResVReg) 1343 .addUse(GR.getSPIRVTypeID(ResType)) 1344 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) 1345 .addImm(GL::InverseSqrt) 1346 .addUse(I.getOperand(2).getReg()) 1347 .constrainAllUses(TII, TRI, RBI); 1348 } 1349 1350 bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg, 1351 const SPIRVType *ResType, 1352 MachineInstr &I) const { 1353 MachineBasicBlock &BB = *I.getParent(); 1354 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitReverse)) 1355 .addDef(ResVReg) 1356 .addUse(GR.getSPIRVTypeID(ResType)) 1357 .addUse(I.getOperand(1).getReg()) 1358 .constrainAllUses(TII, TRI, RBI); 1359 } 1360 1361 bool SPIRVInstructionSelector::selectFreeze(Register ResVReg, 1362 const SPIRVType *ResType, 1363 MachineInstr &I) const { 1364 // There is no way to implement `freeze` correctly without support on SPIR-V 1365 // standard side, but we may at least address a simple (static) case when 1366 // undef/poison value presence is obvious. The main benefit of even 1367 // incomplete `freeze` support is preventing of translation from crashing due 1368 // to lack of support on legalization and instruction selection steps. 1369 if (!I.getOperand(0).isReg() || !I.getOperand(1).isReg()) 1370 return false; 1371 Register OpReg = I.getOperand(1).getReg(); 1372 if (MachineInstr *Def = MRI->getVRegDef(OpReg)) { 1373 Register Reg; 1374 switch (Def->getOpcode()) { 1375 case SPIRV::ASSIGN_TYPE: 1376 if (MachineInstr *AssignToDef = 1377 MRI->getVRegDef(Def->getOperand(1).getReg())) { 1378 if (AssignToDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) 1379 Reg = Def->getOperand(2).getReg(); 1380 } 1381 break; 1382 case SPIRV::OpUndef: 1383 Reg = Def->getOperand(1).getReg(); 1384 break; 1385 } 1386 unsigned DestOpCode; 1387 if (Reg.isValid()) { 1388 DestOpCode = SPIRV::OpConstantNull; 1389 } else { 1390 DestOpCode = TargetOpcode::COPY; 1391 Reg = OpReg; 1392 } 1393 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DestOpCode)) 1394 .addDef(I.getOperand(0).getReg()) 1395 .addUse(Reg) 1396 .constrainAllUses(TII, TRI, RBI); 1397 } 1398 return false; 1399 } 1400 1401 bool SPIRVInstructionSelector::selectConstVector(Register ResVReg, 1402 const SPIRVType *ResType, 1403 MachineInstr &I) const { 1404 // TODO: only const case is supported for now. 1405 assert(std::all_of( 1406 I.operands_begin(), I.operands_end(), [this](const MachineOperand &MO) { 1407 if (MO.isDef()) 1408 return true; 1409 if (!MO.isReg()) 1410 return false; 1411 SPIRVType *ConstTy = this->MRI->getVRegDef(MO.getReg()); 1412 assert(ConstTy && ConstTy->getOpcode() == SPIRV::ASSIGN_TYPE && 1413 ConstTy->getOperand(1).isReg()); 1414 Register ConstReg = ConstTy->getOperand(1).getReg(); 1415 const MachineInstr *Const = this->MRI->getVRegDef(ConstReg); 1416 assert(Const); 1417 return (Const->getOpcode() == TargetOpcode::G_CONSTANT || 1418 Const->getOpcode() == TargetOpcode::G_FCONSTANT); 1419 })); 1420 1421 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), 1422 TII.get(SPIRV::OpConstantComposite)) 1423 .addDef(ResVReg) 1424 .addUse(GR.getSPIRVTypeID(ResType)); 1425 for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i) 1426 MIB.addUse(I.getOperand(i).getReg()); 1427 return MIB.constrainAllUses(TII, TRI, RBI); 1428 } 1429 1430 static unsigned getArrayComponentCount(MachineRegisterInfo *MRI, 1431 const SPIRVType *ResType) { 1432 Register OpReg = ResType->getOperand(2).getReg(); 1433 SPIRVType *OpDef = MRI->getVRegDef(OpReg); 1434 if (!OpDef) 1435 return 0; 1436 if (OpDef->getOpcode() == SPIRV::ASSIGN_TYPE && 1437 OpDef->getOperand(1).isReg()) { 1438 if (SPIRVType *RefDef = MRI->getVRegDef(OpDef->getOperand(1).getReg())) 1439 OpDef = RefDef; 1440 } 1441 unsigned N = OpDef->getOpcode() == TargetOpcode::G_CONSTANT 1442 ? OpDef->getOperand(1).getCImm()->getValue().getZExtValue() 1443 : 0; 1444 return N; 1445 } 1446 1447 // Return true if the type represents a constant register 1448 static bool isConstReg(MachineRegisterInfo *MRI, SPIRVType *OpDef) { 1449 if (OpDef->getOpcode() == SPIRV::ASSIGN_TYPE && 1450 OpDef->getOperand(1).isReg()) { 1451 if (SPIRVType *RefDef = MRI->getVRegDef(OpDef->getOperand(1).getReg())) 1452 OpDef = RefDef; 1453 } 1454 return OpDef->getOpcode() == TargetOpcode::G_CONSTANT || 1455 OpDef->getOpcode() == TargetOpcode::G_FCONSTANT; 1456 } 1457 1458 // Return true if the virtual register represents a constant 1459 static bool isConstReg(MachineRegisterInfo *MRI, Register OpReg) { 1460 if (SPIRVType *OpDef = MRI->getVRegDef(OpReg)) 1461 return isConstReg(MRI, OpDef); 1462 return false; 1463 } 1464 1465 bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg, 1466 const SPIRVType *ResType, 1467 MachineInstr &I) const { 1468 unsigned N = 0; 1469 if (ResType->getOpcode() == SPIRV::OpTypeVector) 1470 N = GR.getScalarOrVectorComponentCount(ResType); 1471 else if (ResType->getOpcode() == SPIRV::OpTypeArray) 1472 N = getArrayComponentCount(MRI, ResType); 1473 else 1474 report_fatal_error("Cannot select G_SPLAT_VECTOR with a non-vector result"); 1475 1476 unsigned OpIdx = I.getNumExplicitDefs(); 1477 if (!I.getOperand(OpIdx).isReg()) 1478 report_fatal_error("Unexpected argument in G_SPLAT_VECTOR"); 1479 1480 // check if we may construct a constant vector 1481 Register OpReg = I.getOperand(OpIdx).getReg(); 1482 bool IsConst = isConstReg(MRI, OpReg); 1483 1484 if (!IsConst && N < 2) 1485 report_fatal_error( 1486 "There must be at least two constituent operands in a vector"); 1487 1488 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), 1489 TII.get(IsConst ? SPIRV::OpConstantComposite 1490 : SPIRV::OpCompositeConstruct)) 1491 .addDef(ResVReg) 1492 .addUse(GR.getSPIRVTypeID(ResType)); 1493 for (unsigned i = 0; i < N; ++i) 1494 MIB.addUse(OpReg); 1495 return MIB.constrainAllUses(TII, TRI, RBI); 1496 } 1497 1498 bool SPIRVInstructionSelector::selectCmp(Register ResVReg, 1499 const SPIRVType *ResType, 1500 unsigned CmpOpc, 1501 MachineInstr &I) const { 1502 Register Cmp0 = I.getOperand(2).getReg(); 1503 Register Cmp1 = I.getOperand(3).getReg(); 1504 assert(GR.getSPIRVTypeForVReg(Cmp0)->getOpcode() == 1505 GR.getSPIRVTypeForVReg(Cmp1)->getOpcode() && 1506 "CMP operands should have the same type"); 1507 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CmpOpc)) 1508 .addDef(ResVReg) 1509 .addUse(GR.getSPIRVTypeID(ResType)) 1510 .addUse(Cmp0) 1511 .addUse(Cmp1) 1512 .constrainAllUses(TII, TRI, RBI); 1513 } 1514 1515 bool SPIRVInstructionSelector::selectICmp(Register ResVReg, 1516 const SPIRVType *ResType, 1517 MachineInstr &I) const { 1518 auto Pred = I.getOperand(1).getPredicate(); 1519 unsigned CmpOpc; 1520 1521 Register CmpOperand = I.getOperand(2).getReg(); 1522 if (GR.isScalarOfType(CmpOperand, SPIRV::OpTypePointer)) 1523 CmpOpc = getPtrCmpOpcode(Pred); 1524 else if (GR.isScalarOrVectorOfType(CmpOperand, SPIRV::OpTypeBool)) 1525 CmpOpc = getBoolCmpOpcode(Pred); 1526 else 1527 CmpOpc = getICmpOpcode(Pred); 1528 return selectCmp(ResVReg, ResType, CmpOpc, I); 1529 } 1530 1531 void SPIRVInstructionSelector::renderFImm32(MachineInstrBuilder &MIB, 1532 const MachineInstr &I, 1533 int OpIdx) const { 1534 assert(I.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1 && 1535 "Expected G_FCONSTANT"); 1536 const ConstantFP *FPImm = I.getOperand(1).getFPImm(); 1537 addNumImm(FPImm->getValueAPF().bitcastToAPInt(), MIB); 1538 } 1539 1540 void SPIRVInstructionSelector::renderImm32(MachineInstrBuilder &MIB, 1541 const MachineInstr &I, 1542 int OpIdx) const { 1543 assert(I.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && 1544 "Expected G_CONSTANT"); 1545 addNumImm(I.getOperand(1).getCImm()->getValue(), MIB); 1546 } 1547 1548 Register 1549 SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I, 1550 const SPIRVType *ResType) const { 1551 Type *LLVMTy = IntegerType::get(GR.CurMF->getFunction().getContext(), 32); 1552 const SPIRVType *SpvI32Ty = 1553 ResType ? ResType : GR.getOrCreateSPIRVIntegerType(32, I, TII); 1554 // Find a constant in DT or build a new one. 1555 auto ConstInt = ConstantInt::get(LLVMTy, Val); 1556 Register NewReg = GR.find(ConstInt, GR.CurMF); 1557 if (!NewReg.isValid()) { 1558 NewReg = MRI->createGenericVirtualRegister(LLT::scalar(32)); 1559 GR.add(ConstInt, GR.CurMF, NewReg); 1560 MachineInstr *MI; 1561 MachineBasicBlock &BB = *I.getParent(); 1562 if (Val == 0) { 1563 MI = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) 1564 .addDef(NewReg) 1565 .addUse(GR.getSPIRVTypeID(SpvI32Ty)); 1566 } else { 1567 MI = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI)) 1568 .addDef(NewReg) 1569 .addUse(GR.getSPIRVTypeID(SpvI32Ty)) 1570 .addImm(APInt(32, Val).getZExtValue()); 1571 } 1572 constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); 1573 } 1574 return NewReg; 1575 } 1576 1577 bool SPIRVInstructionSelector::selectFCmp(Register ResVReg, 1578 const SPIRVType *ResType, 1579 MachineInstr &I) const { 1580 unsigned CmpOp = getFCmpOpcode(I.getOperand(1).getPredicate()); 1581 return selectCmp(ResVReg, ResType, CmpOp, I); 1582 } 1583 1584 Register SPIRVInstructionSelector::buildZerosVal(const SPIRVType *ResType, 1585 MachineInstr &I) const { 1586 // OpenCL uses nulls for Zero. In HLSL we don't use null constants. 1587 bool ZeroAsNull = STI.isOpenCLEnv(); 1588 if (ResType->getOpcode() == SPIRV::OpTypeVector) 1589 return GR.getOrCreateConstVector(0UL, I, ResType, TII, ZeroAsNull); 1590 return GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull); 1591 } 1592 1593 static APFloat getZeroFP(const Type *LLVMFloatTy) { 1594 if (!LLVMFloatTy) 1595 return APFloat::getZero(APFloat::IEEEsingle()); 1596 switch (LLVMFloatTy->getScalarType()->getTypeID()) { 1597 case Type::HalfTyID: 1598 return APFloat::getZero(APFloat::IEEEhalf()); 1599 default: 1600 case Type::FloatTyID: 1601 return APFloat::getZero(APFloat::IEEEsingle()); 1602 case Type::DoubleTyID: 1603 return APFloat::getZero(APFloat::IEEEdouble()); 1604 } 1605 } 1606 1607 Register SPIRVInstructionSelector::buildZerosValF(const SPIRVType *ResType, 1608 MachineInstr &I) const { 1609 // OpenCL uses nulls for Zero. In HLSL we don't use null constants. 1610 bool ZeroAsNull = STI.isOpenCLEnv(); 1611 APFloat VZero = getZeroFP(GR.getTypeForSPIRVType(ResType)); 1612 if (ResType->getOpcode() == SPIRV::OpTypeVector) 1613 return GR.getOrCreateConstVector(VZero, I, ResType, TII, ZeroAsNull); 1614 return GR.getOrCreateConstFP(VZero, I, ResType, TII, ZeroAsNull); 1615 } 1616 1617 Register SPIRVInstructionSelector::buildOnesVal(bool AllOnes, 1618 const SPIRVType *ResType, 1619 MachineInstr &I) const { 1620 unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType); 1621 APInt One = 1622 AllOnes ? APInt::getAllOnes(BitWidth) : APInt::getOneBitSet(BitWidth, 0); 1623 if (ResType->getOpcode() == SPIRV::OpTypeVector) 1624 return GR.getOrCreateConstVector(One.getZExtValue(), I, ResType, TII); 1625 return GR.getOrCreateConstInt(One.getZExtValue(), I, ResType, TII); 1626 } 1627 1628 bool SPIRVInstructionSelector::selectSelect(Register ResVReg, 1629 const SPIRVType *ResType, 1630 MachineInstr &I, 1631 bool IsSigned) const { 1632 // To extend a bool, we need to use OpSelect between constants. 1633 Register ZeroReg = buildZerosVal(ResType, I); 1634 Register OneReg = buildOnesVal(IsSigned, ResType, I); 1635 bool IsScalarBool = 1636 GR.isScalarOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool); 1637 unsigned Opcode = 1638 IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectSIVCond; 1639 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) 1640 .addDef(ResVReg) 1641 .addUse(GR.getSPIRVTypeID(ResType)) 1642 .addUse(I.getOperand(1).getReg()) 1643 .addUse(OneReg) 1644 .addUse(ZeroReg) 1645 .constrainAllUses(TII, TRI, RBI); 1646 } 1647 1648 bool SPIRVInstructionSelector::selectIToF(Register ResVReg, 1649 const SPIRVType *ResType, 1650 MachineInstr &I, bool IsSigned, 1651 unsigned Opcode) const { 1652 Register SrcReg = I.getOperand(1).getReg(); 1653 // We can convert bool value directly to float type without OpConvert*ToF, 1654 // however the translator generates OpSelect+OpConvert*ToF, so we do the same. 1655 if (GR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) { 1656 unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType); 1657 SPIRVType *TmpType = GR.getOrCreateSPIRVIntegerType(BitWidth, I, TII); 1658 if (ResType->getOpcode() == SPIRV::OpTypeVector) { 1659 const unsigned NumElts = ResType->getOperand(2).getImm(); 1660 TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII); 1661 } 1662 SrcReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1663 selectSelect(SrcReg, TmpType, I, false); 1664 } 1665 return selectUnOpWithSrc(ResVReg, ResType, I, SrcReg, Opcode); 1666 } 1667 1668 bool SPIRVInstructionSelector::selectExt(Register ResVReg, 1669 const SPIRVType *ResType, 1670 MachineInstr &I, bool IsSigned) const { 1671 Register SrcReg = I.getOperand(1).getReg(); 1672 if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool)) 1673 return selectSelect(ResVReg, ResType, I, IsSigned); 1674 1675 SPIRVType *SrcType = GR.getSPIRVTypeForVReg(SrcReg); 1676 if (SrcType == ResType) 1677 return BuildMI(*I.getParent(), I, I.getDebugLoc(), 1678 TII.get(TargetOpcode::COPY)) 1679 .addDef(ResVReg) 1680 .addUse(SrcReg) 1681 .constrainAllUses(TII, TRI, RBI); 1682 1683 unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert; 1684 return selectUnOp(ResVReg, ResType, I, Opcode); 1685 } 1686 1687 bool SPIRVInstructionSelector::selectIntToBool(Register IntReg, 1688 Register ResVReg, 1689 MachineInstr &I, 1690 const SPIRVType *IntTy, 1691 const SPIRVType *BoolTy) const { 1692 // To truncate to a bool, we use OpBitwiseAnd 1 and OpINotEqual to zero. 1693 Register BitIntReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1694 bool IsVectorTy = IntTy->getOpcode() == SPIRV::OpTypeVector; 1695 unsigned Opcode = IsVectorTy ? SPIRV::OpBitwiseAndV : SPIRV::OpBitwiseAndS; 1696 Register Zero = buildZerosVal(IntTy, I); 1697 Register One = buildOnesVal(false, IntTy, I); 1698 MachineBasicBlock &BB = *I.getParent(); 1699 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) 1700 .addDef(BitIntReg) 1701 .addUse(GR.getSPIRVTypeID(IntTy)) 1702 .addUse(IntReg) 1703 .addUse(One) 1704 .constrainAllUses(TII, TRI, RBI); 1705 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual)) 1706 .addDef(ResVReg) 1707 .addUse(GR.getSPIRVTypeID(BoolTy)) 1708 .addUse(BitIntReg) 1709 .addUse(Zero) 1710 .constrainAllUses(TII, TRI, RBI); 1711 } 1712 1713 bool SPIRVInstructionSelector::selectTrunc(Register ResVReg, 1714 const SPIRVType *ResType, 1715 MachineInstr &I) const { 1716 Register IntReg = I.getOperand(1).getReg(); 1717 const SPIRVType *ArgType = GR.getSPIRVTypeForVReg(IntReg); 1718 if (GR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool)) 1719 return selectIntToBool(IntReg, ResVReg, I, ArgType, ResType); 1720 if (ArgType == ResType) 1721 return BuildMI(*I.getParent(), I, I.getDebugLoc(), 1722 TII.get(TargetOpcode::COPY)) 1723 .addDef(ResVReg) 1724 .addUse(IntReg) 1725 .constrainAllUses(TII, TRI, RBI); 1726 bool IsSigned = GR.isScalarOrVectorSigned(ResType); 1727 unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert; 1728 return selectUnOp(ResVReg, ResType, I, Opcode); 1729 } 1730 1731 bool SPIRVInstructionSelector::selectConst(Register ResVReg, 1732 const SPIRVType *ResType, 1733 const APInt &Imm, 1734 MachineInstr &I) const { 1735 unsigned TyOpcode = ResType->getOpcode(); 1736 assert(TyOpcode != SPIRV::OpTypePointer || Imm.isZero()); 1737 MachineBasicBlock &BB = *I.getParent(); 1738 if ((TyOpcode == SPIRV::OpTypePointer || TyOpcode == SPIRV::OpTypeEvent) && 1739 Imm.isZero()) 1740 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) 1741 .addDef(ResVReg) 1742 .addUse(GR.getSPIRVTypeID(ResType)) 1743 .constrainAllUses(TII, TRI, RBI); 1744 if (TyOpcode == SPIRV::OpTypeInt) { 1745 assert(Imm.getBitWidth() <= 64 && "Unsupported integer width!"); 1746 Register Reg = GR.getOrCreateConstInt(Imm.getZExtValue(), I, ResType, TII); 1747 if (Reg == ResVReg) 1748 return true; 1749 return BuildMI(BB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY)) 1750 .addDef(ResVReg) 1751 .addUse(Reg) 1752 .constrainAllUses(TII, TRI, RBI); 1753 } 1754 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI)) 1755 .addDef(ResVReg) 1756 .addUse(GR.getSPIRVTypeID(ResType)); 1757 // <=32-bit integers should be caught by the sdag pattern. 1758 assert(Imm.getBitWidth() > 32); 1759 addNumImm(Imm, MIB); 1760 return MIB.constrainAllUses(TII, TRI, RBI); 1761 } 1762 1763 bool SPIRVInstructionSelector::selectOpUndef(Register ResVReg, 1764 const SPIRVType *ResType, 1765 MachineInstr &I) const { 1766 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) 1767 .addDef(ResVReg) 1768 .addUse(GR.getSPIRVTypeID(ResType)) 1769 .constrainAllUses(TII, TRI, RBI); 1770 } 1771 1772 static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI) { 1773 assert(MO.isReg()); 1774 const SPIRVType *TypeInst = MRI->getVRegDef(MO.getReg()); 1775 if (TypeInst->getOpcode() != SPIRV::ASSIGN_TYPE) 1776 return false; 1777 assert(TypeInst->getOperand(1).isReg()); 1778 MachineInstr *ImmInst = MRI->getVRegDef(TypeInst->getOperand(1).getReg()); 1779 return ImmInst->getOpcode() == TargetOpcode::G_CONSTANT; 1780 } 1781 1782 static int64_t foldImm(const MachineOperand &MO, MachineRegisterInfo *MRI) { 1783 const SPIRVType *TypeInst = MRI->getVRegDef(MO.getReg()); 1784 MachineInstr *ImmInst = MRI->getVRegDef(TypeInst->getOperand(1).getReg()); 1785 assert(ImmInst->getOpcode() == TargetOpcode::G_CONSTANT); 1786 return ImmInst->getOperand(1).getCImm()->getZExtValue(); 1787 } 1788 1789 bool SPIRVInstructionSelector::selectInsertVal(Register ResVReg, 1790 const SPIRVType *ResType, 1791 MachineInstr &I) const { 1792 MachineBasicBlock &BB = *I.getParent(); 1793 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeInsert)) 1794 .addDef(ResVReg) 1795 .addUse(GR.getSPIRVTypeID(ResType)) 1796 // object to insert 1797 .addUse(I.getOperand(3).getReg()) 1798 // composite to insert into 1799 .addUse(I.getOperand(2).getReg()); 1800 for (unsigned i = 4; i < I.getNumOperands(); i++) 1801 MIB.addImm(foldImm(I.getOperand(i), MRI)); 1802 return MIB.constrainAllUses(TII, TRI, RBI); 1803 } 1804 1805 bool SPIRVInstructionSelector::selectExtractVal(Register ResVReg, 1806 const SPIRVType *ResType, 1807 MachineInstr &I) const { 1808 MachineBasicBlock &BB = *I.getParent(); 1809 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) 1810 .addDef(ResVReg) 1811 .addUse(GR.getSPIRVTypeID(ResType)) 1812 .addUse(I.getOperand(2).getReg()); 1813 for (unsigned i = 3; i < I.getNumOperands(); i++) 1814 MIB.addImm(foldImm(I.getOperand(i), MRI)); 1815 return MIB.constrainAllUses(TII, TRI, RBI); 1816 } 1817 1818 bool SPIRVInstructionSelector::selectInsertElt(Register ResVReg, 1819 const SPIRVType *ResType, 1820 MachineInstr &I) const { 1821 if (isImm(I.getOperand(4), MRI)) 1822 return selectInsertVal(ResVReg, ResType, I); 1823 MachineBasicBlock &BB = *I.getParent(); 1824 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorInsertDynamic)) 1825 .addDef(ResVReg) 1826 .addUse(GR.getSPIRVTypeID(ResType)) 1827 .addUse(I.getOperand(2).getReg()) 1828 .addUse(I.getOperand(3).getReg()) 1829 .addUse(I.getOperand(4).getReg()) 1830 .constrainAllUses(TII, TRI, RBI); 1831 } 1832 1833 bool SPIRVInstructionSelector::selectExtractElt(Register ResVReg, 1834 const SPIRVType *ResType, 1835 MachineInstr &I) const { 1836 if (isImm(I.getOperand(3), MRI)) 1837 return selectExtractVal(ResVReg, ResType, I); 1838 MachineBasicBlock &BB = *I.getParent(); 1839 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorExtractDynamic)) 1840 .addDef(ResVReg) 1841 .addUse(GR.getSPIRVTypeID(ResType)) 1842 .addUse(I.getOperand(2).getReg()) 1843 .addUse(I.getOperand(3).getReg()) 1844 .constrainAllUses(TII, TRI, RBI); 1845 } 1846 1847 bool SPIRVInstructionSelector::selectGEP(Register ResVReg, 1848 const SPIRVType *ResType, 1849 MachineInstr &I) const { 1850 const bool IsGEPInBounds = I.getOperand(2).getImm(); 1851 1852 // OpAccessChain could be used for OpenCL, but the SPIRV-LLVM Translator only 1853 // relies on PtrAccessChain, so we'll try not to deviate. For Vulkan however, 1854 // we have to use Op[InBounds]AccessChain. 1855 const unsigned Opcode = STI.isVulkanEnv() 1856 ? (IsGEPInBounds ? SPIRV::OpInBoundsAccessChain 1857 : SPIRV::OpAccessChain) 1858 : (IsGEPInBounds ? SPIRV::OpInBoundsPtrAccessChain 1859 : SPIRV::OpPtrAccessChain); 1860 1861 auto Res = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) 1862 .addDef(ResVReg) 1863 .addUse(GR.getSPIRVTypeID(ResType)) 1864 // Object to get a pointer to. 1865 .addUse(I.getOperand(3).getReg()); 1866 // Adding indices. 1867 const unsigned StartingIndex = 1868 (Opcode == SPIRV::OpAccessChain || Opcode == SPIRV::OpInBoundsAccessChain) 1869 ? 5 1870 : 4; 1871 for (unsigned i = StartingIndex; i < I.getNumExplicitOperands(); ++i) 1872 Res.addUse(I.getOperand(i).getReg()); 1873 return Res.constrainAllUses(TII, TRI, RBI); 1874 } 1875 1876 // Maybe wrap a value into OpSpecConstantOp 1877 bool SPIRVInstructionSelector::wrapIntoSpecConstantOp( 1878 MachineInstr &I, SmallVector<Register> &CompositeArgs) const { 1879 bool Result = true; 1880 unsigned Lim = I.getNumExplicitOperands(); 1881 for (unsigned i = I.getNumExplicitDefs() + 1; i < Lim; ++i) { 1882 Register OpReg = I.getOperand(i).getReg(); 1883 SPIRVType *OpDefine = MRI->getVRegDef(OpReg); 1884 SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpReg); 1885 if (!OpDefine || !OpType || isConstReg(MRI, OpDefine) || 1886 OpDefine->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST) { 1887 // The case of G_ADDRSPACE_CAST inside spv_const_composite() is processed 1888 // by selectAddrSpaceCast() 1889 CompositeArgs.push_back(OpReg); 1890 continue; 1891 } 1892 MachineFunction *MF = I.getMF(); 1893 Register WrapReg = GR.find(OpDefine, MF); 1894 if (WrapReg.isValid()) { 1895 CompositeArgs.push_back(WrapReg); 1896 continue; 1897 } 1898 // Create a new register for the wrapper 1899 WrapReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1900 GR.add(OpDefine, MF, WrapReg); 1901 CompositeArgs.push_back(WrapReg); 1902 // Decorate the wrapper register and generate a new instruction 1903 MRI->setType(WrapReg, LLT::pointer(0, 32)); 1904 GR.assignSPIRVTypeToVReg(OpType, WrapReg, *MF); 1905 MachineBasicBlock &BB = *I.getParent(); 1906 Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) 1907 .addDef(WrapReg) 1908 .addUse(GR.getSPIRVTypeID(OpType)) 1909 .addImm(static_cast<uint32_t>(SPIRV::Opcode::Bitcast)) 1910 .addUse(OpReg) 1911 .constrainAllUses(TII, TRI, RBI); 1912 if (!Result) 1913 break; 1914 } 1915 return Result; 1916 } 1917 1918 bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, 1919 const SPIRVType *ResType, 1920 MachineInstr &I) const { 1921 MachineBasicBlock &BB = *I.getParent(); 1922 Intrinsic::ID IID = cast<GIntrinsic>(I).getIntrinsicID(); 1923 switch (IID) { 1924 case Intrinsic::spv_load: 1925 return selectLoad(ResVReg, ResType, I); 1926 case Intrinsic::spv_store: 1927 return selectStore(I); 1928 case Intrinsic::spv_extractv: 1929 return selectExtractVal(ResVReg, ResType, I); 1930 case Intrinsic::spv_insertv: 1931 return selectInsertVal(ResVReg, ResType, I); 1932 case Intrinsic::spv_extractelt: 1933 return selectExtractElt(ResVReg, ResType, I); 1934 case Intrinsic::spv_insertelt: 1935 return selectInsertElt(ResVReg, ResType, I); 1936 case Intrinsic::spv_gep: 1937 return selectGEP(ResVReg, ResType, I); 1938 case Intrinsic::spv_unref_global: 1939 case Intrinsic::spv_init_global: { 1940 MachineInstr *MI = MRI->getVRegDef(I.getOperand(1).getReg()); 1941 MachineInstr *Init = I.getNumExplicitOperands() > 2 1942 ? MRI->getVRegDef(I.getOperand(2).getReg()) 1943 : nullptr; 1944 assert(MI); 1945 return selectGlobalValue(MI->getOperand(0).getReg(), *MI, Init); 1946 } 1947 case Intrinsic::spv_undef: { 1948 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) 1949 .addDef(ResVReg) 1950 .addUse(GR.getSPIRVTypeID(ResType)); 1951 return MIB.constrainAllUses(TII, TRI, RBI); 1952 } 1953 case Intrinsic::spv_const_composite: { 1954 // If no values are attached, the composite is null constant. 1955 bool IsNull = I.getNumExplicitDefs() + 1 == I.getNumExplicitOperands(); 1956 // Select a proper instruction. 1957 unsigned Opcode = SPIRV::OpConstantNull; 1958 SmallVector<Register> CompositeArgs; 1959 if (!IsNull) { 1960 Opcode = SPIRV::OpConstantComposite; 1961 if (!wrapIntoSpecConstantOp(I, CompositeArgs)) 1962 return false; 1963 } 1964 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) 1965 .addDef(ResVReg) 1966 .addUse(GR.getSPIRVTypeID(ResType)); 1967 // skip type MD node we already used when generated assign.type for this 1968 if (!IsNull) { 1969 for (Register OpReg : CompositeArgs) 1970 MIB.addUse(OpReg); 1971 } 1972 return MIB.constrainAllUses(TII, TRI, RBI); 1973 } 1974 case Intrinsic::spv_assign_name: { 1975 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpName)); 1976 MIB.addUse(I.getOperand(I.getNumExplicitDefs() + 1).getReg()); 1977 for (unsigned i = I.getNumExplicitDefs() + 2; 1978 i < I.getNumExplicitOperands(); ++i) { 1979 MIB.addImm(I.getOperand(i).getImm()); 1980 } 1981 return MIB.constrainAllUses(TII, TRI, RBI); 1982 } 1983 case Intrinsic::spv_switch: { 1984 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSwitch)); 1985 for (unsigned i = 1; i < I.getNumExplicitOperands(); ++i) { 1986 if (I.getOperand(i).isReg()) 1987 MIB.addReg(I.getOperand(i).getReg()); 1988 else if (I.getOperand(i).isCImm()) 1989 addNumImm(I.getOperand(i).getCImm()->getValue(), MIB); 1990 else if (I.getOperand(i).isMBB()) 1991 MIB.addMBB(I.getOperand(i).getMBB()); 1992 else 1993 llvm_unreachable("Unexpected OpSwitch operand"); 1994 } 1995 return MIB.constrainAllUses(TII, TRI, RBI); 1996 } 1997 case Intrinsic::spv_cmpxchg: 1998 return selectAtomicCmpXchg(ResVReg, ResType, I); 1999 case Intrinsic::spv_unreachable: 2000 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUnreachable)); 2001 break; 2002 case Intrinsic::spv_alloca: 2003 return selectFrameIndex(ResVReg, ResType, I); 2004 case Intrinsic::spv_alloca_array: 2005 return selectAllocaArray(ResVReg, ResType, I); 2006 case Intrinsic::spv_assume: 2007 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) 2008 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpAssumeTrueKHR)) 2009 .addUse(I.getOperand(1).getReg()); 2010 break; 2011 case Intrinsic::spv_expect: 2012 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) 2013 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExpectKHR)) 2014 .addDef(ResVReg) 2015 .addUse(GR.getSPIRVTypeID(ResType)) 2016 .addUse(I.getOperand(2).getReg()) 2017 .addUse(I.getOperand(3).getReg()); 2018 break; 2019 case Intrinsic::spv_thread_id: 2020 return selectSpvThreadId(ResVReg, ResType, I); 2021 case Intrinsic::spv_all: 2022 return selectAll(ResVReg, ResType, I); 2023 case Intrinsic::spv_any: 2024 return selectAny(ResVReg, ResType, I); 2025 case Intrinsic::spv_lerp: 2026 return selectFmix(ResVReg, ResType, I); 2027 case Intrinsic::spv_rsqrt: 2028 return selectRsqrt(ResVReg, ResType, I); 2029 case Intrinsic::spv_lifetime_start: 2030 case Intrinsic::spv_lifetime_end: { 2031 unsigned Op = IID == Intrinsic::spv_lifetime_start ? SPIRV::OpLifetimeStart 2032 : SPIRV::OpLifetimeStop; 2033 int64_t Size = I.getOperand(I.getNumExplicitDefs() + 1).getImm(); 2034 Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 2).getReg(); 2035 unsigned PonteeOpType = GR.getPointeeTypeOp(PtrReg); 2036 bool IsNonvoidPtr = PonteeOpType != 0 && PonteeOpType != SPIRV::OpTypeVoid; 2037 if (Size == -1 || IsNonvoidPtr) 2038 Size = 0; 2039 BuildMI(BB, I, I.getDebugLoc(), TII.get(Op)).addUse(PtrReg).addImm(Size); 2040 } break; 2041 default: { 2042 std::string DiagMsg; 2043 raw_string_ostream OS(DiagMsg); 2044 I.print(OS); 2045 DiagMsg = "Intrinsic selection not implemented: " + DiagMsg; 2046 report_fatal_error(DiagMsg.c_str(), false); 2047 } 2048 } 2049 return true; 2050 } 2051 2052 bool SPIRVInstructionSelector::selectAllocaArray(Register ResVReg, 2053 const SPIRVType *ResType, 2054 MachineInstr &I) const { 2055 // there was an allocation size parameter to the allocation instruction 2056 // that is not 1 2057 MachineBasicBlock &BB = *I.getParent(); 2058 return BuildMI(BB, I, I.getDebugLoc(), 2059 TII.get(SPIRV::OpVariableLengthArrayINTEL)) 2060 .addDef(ResVReg) 2061 .addUse(GR.getSPIRVTypeID(ResType)) 2062 .addUse(I.getOperand(2).getReg()) 2063 .constrainAllUses(TII, TRI, RBI); 2064 } 2065 2066 bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg, 2067 const SPIRVType *ResType, 2068 MachineInstr &I) const { 2069 // Change order of instructions if needed: all OpVariable instructions in a 2070 // function must be the first instructions in the first block 2071 MachineFunction *MF = I.getParent()->getParent(); 2072 MachineBasicBlock *MBB = &MF->front(); 2073 auto It = MBB->SkipPHIsAndLabels(MBB->begin()), E = MBB->end(); 2074 bool IsHeader = false; 2075 unsigned Opcode; 2076 for (; It != E && It != I; ++It) { 2077 Opcode = It->getOpcode(); 2078 if (Opcode == SPIRV::OpFunction || Opcode == SPIRV::OpFunctionParameter) { 2079 IsHeader = true; 2080 } else if (IsHeader && 2081 !(Opcode == SPIRV::ASSIGN_TYPE || Opcode == SPIRV::OpLabel)) { 2082 ++It; 2083 break; 2084 } 2085 } 2086 return BuildMI(*MBB, It, It->getDebugLoc(), TII.get(SPIRV::OpVariable)) 2087 .addDef(ResVReg) 2088 .addUse(GR.getSPIRVTypeID(ResType)) 2089 .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function)) 2090 .constrainAllUses(TII, TRI, RBI); 2091 } 2092 2093 bool SPIRVInstructionSelector::selectBranch(MachineInstr &I) const { 2094 // InstructionSelector walks backwards through the instructions. We can use 2095 // both a G_BR and a G_BRCOND to create an OpBranchConditional. We hit G_BR 2096 // first, so can generate an OpBranchConditional here. If there is no 2097 // G_BRCOND, we just use OpBranch for a regular unconditional branch. 2098 const MachineInstr *PrevI = I.getPrevNode(); 2099 MachineBasicBlock &MBB = *I.getParent(); 2100 if (PrevI != nullptr && PrevI->getOpcode() == TargetOpcode::G_BRCOND) { 2101 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional)) 2102 .addUse(PrevI->getOperand(0).getReg()) 2103 .addMBB(PrevI->getOperand(1).getMBB()) 2104 .addMBB(I.getOperand(0).getMBB()) 2105 .constrainAllUses(TII, TRI, RBI); 2106 } 2107 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranch)) 2108 .addMBB(I.getOperand(0).getMBB()) 2109 .constrainAllUses(TII, TRI, RBI); 2110 } 2111 2112 bool SPIRVInstructionSelector::selectBranchCond(MachineInstr &I) const { 2113 // InstructionSelector walks backwards through the instructions. For an 2114 // explicit conditional branch with no fallthrough, we use both a G_BR and a 2115 // G_BRCOND to create an OpBranchConditional. We should hit G_BR first, and 2116 // generate the OpBranchConditional in selectBranch above. 2117 // 2118 // If an OpBranchConditional has been generated, we simply return, as the work 2119 // is alread done. If there is no OpBranchConditional, LLVM must be relying on 2120 // implicit fallthrough to the next basic block, so we need to create an 2121 // OpBranchConditional with an explicit "false" argument pointing to the next 2122 // basic block that LLVM would fall through to. 2123 const MachineInstr *NextI = I.getNextNode(); 2124 // Check if this has already been successfully selected. 2125 if (NextI != nullptr && NextI->getOpcode() == SPIRV::OpBranchConditional) 2126 return true; 2127 // Must be relying on implicit block fallthrough, so generate an 2128 // OpBranchConditional with the "next" basic block as the "false" target. 2129 MachineBasicBlock &MBB = *I.getParent(); 2130 unsigned NextMBBNum = MBB.getNextNode()->getNumber(); 2131 MachineBasicBlock *NextMBB = I.getMF()->getBlockNumbered(NextMBBNum); 2132 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional)) 2133 .addUse(I.getOperand(0).getReg()) 2134 .addMBB(I.getOperand(1).getMBB()) 2135 .addMBB(NextMBB) 2136 .constrainAllUses(TII, TRI, RBI); 2137 } 2138 2139 bool SPIRVInstructionSelector::selectPhi(Register ResVReg, 2140 const SPIRVType *ResType, 2141 MachineInstr &I) const { 2142 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpPhi)) 2143 .addDef(ResVReg) 2144 .addUse(GR.getSPIRVTypeID(ResType)); 2145 const unsigned NumOps = I.getNumOperands(); 2146 for (unsigned i = 1; i < NumOps; i += 2) { 2147 MIB.addUse(I.getOperand(i + 0).getReg()); 2148 MIB.addMBB(I.getOperand(i + 1).getMBB()); 2149 } 2150 return MIB.constrainAllUses(TII, TRI, RBI); 2151 } 2152 2153 bool SPIRVInstructionSelector::selectGlobalValue( 2154 Register ResVReg, MachineInstr &I, const MachineInstr *Init) const { 2155 // FIXME: don't use MachineIRBuilder here, replace it with BuildMI. 2156 MachineIRBuilder MIRBuilder(I); 2157 const GlobalValue *GV = I.getOperand(1).getGlobal(); 2158 Type *GVType = GR.getDeducedGlobalValueType(GV); 2159 SPIRVType *PointerBaseType; 2160 if (GVType->isArrayTy()) { 2161 SPIRVType *ArrayElementType = 2162 GR.getOrCreateSPIRVType(GVType->getArrayElementType(), MIRBuilder, 2163 SPIRV::AccessQualifier::ReadWrite, false); 2164 PointerBaseType = GR.getOrCreateSPIRVArrayType( 2165 ArrayElementType, GVType->getArrayNumElements(), I, TII); 2166 } else { 2167 PointerBaseType = GR.getOrCreateSPIRVType( 2168 GVType, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false); 2169 } 2170 SPIRVType *ResType = GR.getOrCreateSPIRVPointerType( 2171 PointerBaseType, I, TII, 2172 addressSpaceToStorageClass(GV->getAddressSpace(), STI)); 2173 2174 std::string GlobalIdent; 2175 if (!GV->hasName()) { 2176 unsigned &ID = UnnamedGlobalIDs[GV]; 2177 if (ID == 0) 2178 ID = UnnamedGlobalIDs.size(); 2179 GlobalIdent = "__unnamed_" + Twine(ID).str(); 2180 } else { 2181 GlobalIdent = GV->getGlobalIdentifier(); 2182 } 2183 2184 // Behaviour of functions as operands depends on availability of the 2185 // corresponding extension (SPV_INTEL_function_pointers): 2186 // - If there is an extension to operate with functions as operands: 2187 // We create a proper constant operand and evaluate a correct type for a 2188 // function pointer. 2189 // - Without the required extension: 2190 // We have functions as operands in tests with blocks of instruction e.g. in 2191 // transcoding/global_block.ll. These operands are not used and should be 2192 // substituted by zero constants. Their type is expected to be always 2193 // OpTypePointer Function %uchar. 2194 if (isa<Function>(GV)) { 2195 const Constant *ConstVal = GV; 2196 MachineBasicBlock &BB = *I.getParent(); 2197 Register NewReg = GR.find(ConstVal, GR.CurMF); 2198 if (!NewReg.isValid()) { 2199 Register NewReg = ResVReg; 2200 GR.add(ConstVal, GR.CurMF, NewReg); 2201 const Function *GVFun = 2202 STI.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers) 2203 ? dyn_cast<Function>(GV) 2204 : nullptr; 2205 if (GVFun) { 2206 // References to a function via function pointers generate virtual 2207 // registers without a definition. We will resolve it later, during 2208 // module analysis stage. 2209 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); 2210 Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32)); 2211 MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass); 2212 MachineInstrBuilder MB = 2213 BuildMI(BB, I, I.getDebugLoc(), 2214 TII.get(SPIRV::OpConstantFunctionPointerINTEL)) 2215 .addDef(NewReg) 2216 .addUse(GR.getSPIRVTypeID(ResType)) 2217 .addUse(FuncVReg); 2218 // mapping the function pointer to the used Function 2219 GR.recordFunctionPointer(&MB.getInstr()->getOperand(2), GVFun); 2220 return MB.constrainAllUses(TII, TRI, RBI); 2221 } 2222 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) 2223 .addDef(NewReg) 2224 .addUse(GR.getSPIRVTypeID(ResType)) 2225 .constrainAllUses(TII, TRI, RBI); 2226 } 2227 assert(NewReg != ResVReg); 2228 return BuildMI(BB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY)) 2229 .addDef(ResVReg) 2230 .addUse(NewReg) 2231 .constrainAllUses(TII, TRI, RBI); 2232 } 2233 auto GlobalVar = cast<GlobalVariable>(GV); 2234 assert(GlobalVar->getName() != "llvm.global.annotations"); 2235 2236 bool HasInit = GlobalVar->hasInitializer() && 2237 !isa<UndefValue>(GlobalVar->getInitializer()); 2238 // Skip empty declaration for GVs with initilaizers till we get the decl with 2239 // passed initializer. 2240 if (HasInit && !Init) 2241 return true; 2242 2243 unsigned AddrSpace = GV->getAddressSpace(); 2244 SPIRV::StorageClass::StorageClass Storage = 2245 addressSpaceToStorageClass(AddrSpace, STI); 2246 bool HasLnkTy = GV->getLinkage() != GlobalValue::InternalLinkage && 2247 Storage != SPIRV::StorageClass::Function; 2248 SPIRV::LinkageType::LinkageType LnkType = 2249 (GV->isDeclaration() || GV->hasAvailableExternallyLinkage()) 2250 ? SPIRV::LinkageType::Import 2251 : (GV->getLinkage() == GlobalValue::LinkOnceODRLinkage && 2252 STI.canUseExtension(SPIRV::Extension::SPV_KHR_linkonce_odr) 2253 ? SPIRV::LinkageType::LinkOnceODR 2254 : SPIRV::LinkageType::Export); 2255 2256 Register Reg = GR.buildGlobalVariable(ResVReg, ResType, GlobalIdent, GV, 2257 Storage, Init, GlobalVar->isConstant(), 2258 HasLnkTy, LnkType, MIRBuilder, true); 2259 return Reg.isValid(); 2260 } 2261 2262 bool SPIRVInstructionSelector::selectLog10(Register ResVReg, 2263 const SPIRVType *ResType, 2264 MachineInstr &I) const { 2265 if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) { 2266 return selectExtInst(ResVReg, ResType, I, CL::log10); 2267 } 2268 2269 // There is no log10 instruction in the GLSL Extended Instruction set, so it 2270 // is implemented as: 2271 // log10(x) = log2(x) * (1 / log2(10)) 2272 // = log2(x) * 0.30103 2273 2274 MachineIRBuilder MIRBuilder(I); 2275 MachineBasicBlock &BB = *I.getParent(); 2276 2277 // Build log2(x). 2278 Register VarReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); 2279 bool Result = 2280 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) 2281 .addDef(VarReg) 2282 .addUse(GR.getSPIRVTypeID(ResType)) 2283 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) 2284 .addImm(GL::Log2) 2285 .add(I.getOperand(1)) 2286 .constrainAllUses(TII, TRI, RBI); 2287 2288 // Build 0.30103. 2289 assert(ResType->getOpcode() == SPIRV::OpTypeVector || 2290 ResType->getOpcode() == SPIRV::OpTypeFloat); 2291 // TODO: Add matrix implementation once supported by the HLSL frontend. 2292 const SPIRVType *SpirvScalarType = 2293 ResType->getOpcode() == SPIRV::OpTypeVector 2294 ? GR.getSPIRVTypeForVReg(ResType->getOperand(1).getReg()) 2295 : ResType; 2296 Register ScaleReg = 2297 GR.buildConstantFP(APFloat(0.30103f), MIRBuilder, SpirvScalarType); 2298 2299 // Multiply log2(x) by 0.30103 to get log10(x) result. 2300 auto Opcode = ResType->getOpcode() == SPIRV::OpTypeVector 2301 ? SPIRV::OpVectorTimesScalar 2302 : SPIRV::OpFMulS; 2303 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) 2304 .addDef(ResVReg) 2305 .addUse(GR.getSPIRVTypeID(ResType)) 2306 .addUse(VarReg) 2307 .addUse(ScaleReg) 2308 .constrainAllUses(TII, TRI, RBI); 2309 2310 return Result; 2311 } 2312 2313 bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg, 2314 const SPIRVType *ResType, 2315 MachineInstr &I) const { 2316 // DX intrinsic: @llvm.dx.thread.id(i32) 2317 // ID Name Description 2318 // 93 ThreadId reads the thread ID 2319 2320 MachineIRBuilder MIRBuilder(I); 2321 const SPIRVType *U32Type = GR.getOrCreateSPIRVIntegerType(32, MIRBuilder); 2322 const SPIRVType *Vec3Ty = 2323 GR.getOrCreateSPIRVVectorType(U32Type, 3, MIRBuilder); 2324 const SPIRVType *PtrType = GR.getOrCreateSPIRVPointerType( 2325 Vec3Ty, MIRBuilder, SPIRV::StorageClass::Input); 2326 2327 // Create new register for GlobalInvocationID builtin variable. 2328 Register NewRegister = 2329 MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass); 2330 MIRBuilder.getMRI()->setType(NewRegister, LLT::pointer(0, 32)); 2331 GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF()); 2332 2333 // Build GlobalInvocationID global variable with the necessary decorations. 2334 Register Variable = GR.buildGlobalVariable( 2335 NewRegister, PtrType, 2336 getLinkStringForBuiltIn(SPIRV::BuiltIn::GlobalInvocationId), nullptr, 2337 SPIRV::StorageClass::Input, nullptr, true, true, 2338 SPIRV::LinkageType::Import, MIRBuilder, false); 2339 2340 // Create new register for loading value. 2341 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); 2342 Register LoadedRegister = MRI->createVirtualRegister(&SPIRV::IDRegClass); 2343 MIRBuilder.getMRI()->setType(LoadedRegister, LLT::pointer(0, 32)); 2344 GR.assignSPIRVTypeToVReg(Vec3Ty, LoadedRegister, MIRBuilder.getMF()); 2345 2346 // Load v3uint value from the global variable. 2347 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) 2348 .addDef(LoadedRegister) 2349 .addUse(GR.getSPIRVTypeID(Vec3Ty)) 2350 .addUse(Variable); 2351 2352 // Get Thread ID index. Expecting operand is a constant immediate value, 2353 // wrapped in a type assignment. 2354 assert(I.getOperand(2).isReg()); 2355 Register ThreadIdReg = I.getOperand(2).getReg(); 2356 SPIRVType *ConstTy = this->MRI->getVRegDef(ThreadIdReg); 2357 assert(ConstTy && ConstTy->getOpcode() == SPIRV::ASSIGN_TYPE && 2358 ConstTy->getOperand(1).isReg()); 2359 Register ConstReg = ConstTy->getOperand(1).getReg(); 2360 const MachineInstr *Const = this->MRI->getVRegDef(ConstReg); 2361 assert(Const && Const->getOpcode() == TargetOpcode::G_CONSTANT); 2362 const llvm::APInt &Val = Const->getOperand(1).getCImm()->getValue(); 2363 const uint32_t ThreadId = Val.getZExtValue(); 2364 2365 // Extract the thread ID from the loaded vector value. 2366 MachineBasicBlock &BB = *I.getParent(); 2367 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) 2368 .addDef(ResVReg) 2369 .addUse(GR.getSPIRVTypeID(ResType)) 2370 .addUse(LoadedRegister) 2371 .addImm(ThreadId); 2372 return MIB.constrainAllUses(TII, TRI, RBI); 2373 } 2374 2375 namespace llvm { 2376 InstructionSelector * 2377 createSPIRVInstructionSelector(const SPIRVTargetMachine &TM, 2378 const SPIRVSubtarget &Subtarget, 2379 const RegisterBankInfo &RBI) { 2380 return new SPIRVInstructionSelector(TM, Subtarget, RBI); 2381 } 2382 } // namespace llvm 2383