1 //===- SPIRVInstructionSelector.cpp ------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the targeting of the InstructionSelector class for 10 // SPIRV. 11 // TODO: This should be generated by TableGen. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MCTargetDesc/SPIRVBaseInfo.h" 16 #include "MCTargetDesc/SPIRVMCTargetDesc.h" 17 #include "SPIRV.h" 18 #include "SPIRVGlobalRegistry.h" 19 #include "SPIRVInstrInfo.h" 20 #include "SPIRVRegisterBankInfo.h" 21 #include "SPIRVRegisterInfo.h" 22 #include "SPIRVTargetMachine.h" 23 #include "SPIRVUtils.h" 24 #include "llvm/ADT/APFloat.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h" 27 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h" 28 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/Register.h" 33 #include "llvm/CodeGen/TargetOpcodes.h" 34 #include "llvm/IR/IntrinsicsSPIRV.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 38 #define DEBUG_TYPE "spirv-isel" 39 40 using namespace llvm; 41 namespace CL = SPIRV::OpenCLExtInst; 42 namespace GL = SPIRV::GLSLExtInst; 43 44 using ExtInstList = 45 std::vector<std::pair<SPIRV::InstructionSet::InstructionSet, uint32_t>>; 46 47 namespace { 48 49 llvm::SPIRV::SelectionControl::SelectionControl 50 getSelectionOperandForImm(int Imm) { 51 if (Imm == 2) 52 return SPIRV::SelectionControl::Flatten; 53 if (Imm == 1) 54 return SPIRV::SelectionControl::DontFlatten; 55 if (Imm == 0) 56 return SPIRV::SelectionControl::None; 57 llvm_unreachable("Invalid immediate"); 58 } 59 60 #define GET_GLOBALISEL_PREDICATE_BITSET 61 #include "SPIRVGenGlobalISel.inc" 62 #undef GET_GLOBALISEL_PREDICATE_BITSET 63 64 class SPIRVInstructionSelector : public InstructionSelector { 65 const SPIRVSubtarget &STI; 66 const SPIRVInstrInfo &TII; 67 const SPIRVRegisterInfo &TRI; 68 const RegisterBankInfo &RBI; 69 SPIRVGlobalRegistry &GR; 70 MachineRegisterInfo *MRI; 71 MachineFunction *HasVRegsReset = nullptr; 72 73 /// We need to keep track of the number we give to anonymous global values to 74 /// generate the same name every time when this is needed. 75 mutable DenseMap<const GlobalValue *, unsigned> UnnamedGlobalIDs; 76 SmallPtrSet<MachineInstr *, 8> DeadMIs; 77 78 public: 79 SPIRVInstructionSelector(const SPIRVTargetMachine &TM, 80 const SPIRVSubtarget &ST, 81 const RegisterBankInfo &RBI); 82 void setupMF(MachineFunction &MF, GISelKnownBits *KB, 83 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, 84 BlockFrequencyInfo *BFI) override; 85 // Common selection code. Instruction-specific selection occurs in spvSelect. 86 bool select(MachineInstr &I) override; 87 static const char *getName() { return DEBUG_TYPE; } 88 89 #define GET_GLOBALISEL_PREDICATES_DECL 90 #include "SPIRVGenGlobalISel.inc" 91 #undef GET_GLOBALISEL_PREDICATES_DECL 92 93 #define GET_GLOBALISEL_TEMPORARIES_DECL 94 #include "SPIRVGenGlobalISel.inc" 95 #undef GET_GLOBALISEL_TEMPORARIES_DECL 96 97 private: 98 void resetVRegsType(MachineFunction &MF); 99 100 // tblgen-erated 'select' implementation, used as the initial selector for 101 // the patterns that don't require complex C++. 102 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 103 104 // All instruction-specific selection that didn't happen in "select()". 105 // Is basically a large Switch/Case delegating to all other select method. 106 bool spvSelect(Register ResVReg, const SPIRVType *ResType, 107 MachineInstr &I) const; 108 109 bool selectFirstBitHigh(Register ResVReg, const SPIRVType *ResType, 110 MachineInstr &I, bool IsSigned) const; 111 112 bool selectFirstBitHigh16(Register ResVReg, const SPIRVType *ResType, 113 MachineInstr &I, bool IsSigned) const; 114 115 bool selectFirstBitHigh32(Register ResVReg, const SPIRVType *ResType, 116 MachineInstr &I, Register SrcReg, 117 bool IsSigned) const; 118 119 bool selectFirstBitHigh64(Register ResVReg, const SPIRVType *ResType, 120 MachineInstr &I, bool IsSigned) const; 121 122 bool selectGlobalValue(Register ResVReg, MachineInstr &I, 123 const MachineInstr *Init = nullptr) const; 124 125 bool selectOpWithSrcs(Register ResVReg, const SPIRVType *ResType, 126 MachineInstr &I, std::vector<Register> SrcRegs, 127 unsigned Opcode) const; 128 129 bool selectUnOp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, 130 unsigned Opcode) const; 131 132 bool selectBitcast(Register ResVReg, const SPIRVType *ResType, 133 MachineInstr &I) const; 134 135 bool selectLoad(Register ResVReg, const SPIRVType *ResType, 136 MachineInstr &I) const; 137 bool selectStore(MachineInstr &I) const; 138 139 bool selectStackSave(Register ResVReg, const SPIRVType *ResType, 140 MachineInstr &I) const; 141 bool selectStackRestore(MachineInstr &I) const; 142 143 bool selectMemOperation(Register ResVReg, MachineInstr &I) const; 144 145 bool selectAtomicRMW(Register ResVReg, const SPIRVType *ResType, 146 MachineInstr &I, unsigned NewOpcode, 147 unsigned NegateOpcode = 0) const; 148 149 bool selectAtomicCmpXchg(Register ResVReg, const SPIRVType *ResType, 150 MachineInstr &I) const; 151 152 bool selectFence(MachineInstr &I) const; 153 154 bool selectAddrSpaceCast(Register ResVReg, const SPIRVType *ResType, 155 MachineInstr &I) const; 156 157 bool selectAnyOrAll(Register ResVReg, const SPIRVType *ResType, 158 MachineInstr &I, unsigned OpType) const; 159 160 bool selectAll(Register ResVReg, const SPIRVType *ResType, 161 MachineInstr &I) const; 162 163 bool selectAny(Register ResVReg, const SPIRVType *ResType, 164 MachineInstr &I) const; 165 166 bool selectBitreverse(Register ResVReg, const SPIRVType *ResType, 167 MachineInstr &I) const; 168 169 bool selectBuildVector(Register ResVReg, const SPIRVType *ResType, 170 MachineInstr &I) const; 171 bool selectSplatVector(Register ResVReg, const SPIRVType *ResType, 172 MachineInstr &I) const; 173 174 bool selectCmp(Register ResVReg, const SPIRVType *ResType, 175 unsigned comparisonOpcode, MachineInstr &I) const; 176 bool selectCross(Register ResVReg, const SPIRVType *ResType, 177 MachineInstr &I) const; 178 bool selectDiscard(Register ResVReg, const SPIRVType *ResType, 179 MachineInstr &I) const; 180 181 bool selectICmp(Register ResVReg, const SPIRVType *ResType, 182 MachineInstr &I) const; 183 bool selectFCmp(Register ResVReg, const SPIRVType *ResType, 184 MachineInstr &I) const; 185 186 bool selectSign(Register ResVReg, const SPIRVType *ResType, 187 MachineInstr &I) const; 188 189 bool selectFloatDot(Register ResVReg, const SPIRVType *ResType, 190 MachineInstr &I) const; 191 192 bool selectOverflowArith(Register ResVReg, const SPIRVType *ResType, 193 MachineInstr &I, unsigned Opcode) const; 194 195 bool selectIntegerDot(Register ResVReg, const SPIRVType *ResType, 196 MachineInstr &I, bool Signed) const; 197 198 bool selectIntegerDotExpansion(Register ResVReg, const SPIRVType *ResType, 199 MachineInstr &I) const; 200 201 template <bool Signed> 202 bool selectDot4AddPacked(Register ResVReg, const SPIRVType *ResType, 203 MachineInstr &I) const; 204 template <bool Signed> 205 bool selectDot4AddPackedExpansion(Register ResVReg, const SPIRVType *ResType, 206 MachineInstr &I) const; 207 208 void renderImm32(MachineInstrBuilder &MIB, const MachineInstr &I, 209 int OpIdx) const; 210 void renderFImm64(MachineInstrBuilder &MIB, const MachineInstr &I, 211 int OpIdx) const; 212 213 bool selectConst(Register ResVReg, const SPIRVType *ResType, const APInt &Imm, 214 MachineInstr &I) const; 215 216 bool selectSelect(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, 217 bool IsSigned) const; 218 bool selectIToF(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, 219 bool IsSigned, unsigned Opcode) const; 220 bool selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, 221 bool IsSigned) const; 222 223 bool selectTrunc(Register ResVReg, const SPIRVType *ResType, 224 MachineInstr &I) const; 225 226 bool selectSUCmp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, 227 bool IsSigned) const; 228 229 bool selectIntToBool(Register IntReg, Register ResVReg, MachineInstr &I, 230 const SPIRVType *intTy, const SPIRVType *boolTy) const; 231 232 bool selectOpUndef(Register ResVReg, const SPIRVType *ResType, 233 MachineInstr &I) const; 234 bool selectFreeze(Register ResVReg, const SPIRVType *ResType, 235 MachineInstr &I) const; 236 bool selectIntrinsic(Register ResVReg, const SPIRVType *ResType, 237 MachineInstr &I) const; 238 bool selectExtractVal(Register ResVReg, const SPIRVType *ResType, 239 MachineInstr &I) const; 240 bool selectInsertVal(Register ResVReg, const SPIRVType *ResType, 241 MachineInstr &I) const; 242 bool selectExtractElt(Register ResVReg, const SPIRVType *ResType, 243 MachineInstr &I) const; 244 bool selectInsertElt(Register ResVReg, const SPIRVType *ResType, 245 MachineInstr &I) const; 246 bool selectGEP(Register ResVReg, const SPIRVType *ResType, 247 MachineInstr &I) const; 248 249 bool selectFrameIndex(Register ResVReg, const SPIRVType *ResType, 250 MachineInstr &I) const; 251 bool selectAllocaArray(Register ResVReg, const SPIRVType *ResType, 252 MachineInstr &I) const; 253 254 bool selectBranch(MachineInstr &I) const; 255 bool selectBranchCond(MachineInstr &I) const; 256 257 bool selectPhi(Register ResVReg, const SPIRVType *ResType, 258 MachineInstr &I) const; 259 260 [[maybe_unused]] bool selectExtInst(Register ResVReg, 261 const SPIRVType *RestType, 262 MachineInstr &I, 263 GL::GLSLExtInst GLInst) const; 264 bool selectExtInst(Register ResVReg, const SPIRVType *ResType, 265 MachineInstr &I, CL::OpenCLExtInst CLInst) const; 266 bool selectExtInst(Register ResVReg, const SPIRVType *ResType, 267 MachineInstr &I, CL::OpenCLExtInst CLInst, 268 GL::GLSLExtInst GLInst) const; 269 bool selectExtInst(Register ResVReg, const SPIRVType *ResType, 270 MachineInstr &I, const ExtInstList &ExtInsts) const; 271 272 bool selectLog10(Register ResVReg, const SPIRVType *ResType, 273 MachineInstr &I) const; 274 275 bool selectSaturate(Register ResVReg, const SPIRVType *ResType, 276 MachineInstr &I) const; 277 278 bool selectWaveOpInst(Register ResVReg, const SPIRVType *ResType, 279 MachineInstr &I, unsigned Opcode) const; 280 281 bool selectWaveActiveCountBits(Register ResVReg, const SPIRVType *ResType, 282 MachineInstr &I) const; 283 284 bool selectUnmergeValues(MachineInstr &I) const; 285 286 bool selectHandleFromBinding(Register &ResVReg, const SPIRVType *ResType, 287 MachineInstr &I) const; 288 289 void selectReadImageIntrinsic(Register &ResVReg, const SPIRVType *ResType, 290 MachineInstr &I) const; 291 292 void selectImageWriteIntrinsic(MachineInstr &I) const; 293 294 // Utilities 295 std::pair<Register, bool> 296 buildI32Constant(uint32_t Val, MachineInstr &I, 297 const SPIRVType *ResType = nullptr) const; 298 299 Register buildZerosVal(const SPIRVType *ResType, MachineInstr &I) const; 300 Register buildZerosValF(const SPIRVType *ResType, MachineInstr &I) const; 301 Register buildOnesVal(bool AllOnes, const SPIRVType *ResType, 302 MachineInstr &I) const; 303 Register buildOnesValF(const SPIRVType *ResType, MachineInstr &I) const; 304 305 bool wrapIntoSpecConstantOp(MachineInstr &I, 306 SmallVector<Register> &CompositeArgs) const; 307 308 Register getUcharPtrTypeReg(MachineInstr &I, 309 SPIRV::StorageClass::StorageClass SC) const; 310 MachineInstrBuilder buildSpecConstantOp(MachineInstr &I, Register Dest, 311 Register Src, Register DestType, 312 uint32_t Opcode) const; 313 MachineInstrBuilder buildConstGenericPtr(MachineInstr &I, Register SrcPtr, 314 SPIRVType *SrcPtrTy) const; 315 Register buildPointerToResource(const SPIRVType *ResType, uint32_t Set, 316 uint32_t Binding, uint32_t ArraySize, 317 Register IndexReg, bool IsNonUniform, 318 MachineIRBuilder MIRBuilder) const; 319 SPIRVType *widenTypeToVec4(const SPIRVType *Type, MachineInstr &I) const; 320 void extractSubvector(Register &ResVReg, const SPIRVType *ResType, 321 Register &ReadReg, MachineInstr &InsertionPoint) const; 322 bool BuildCOPY(Register DestReg, Register SrcReg, MachineInstr &I) const; 323 bool loadVec3BuiltinInputID(SPIRV::BuiltIn::BuiltIn BuiltInValue, 324 Register ResVReg, const SPIRVType *ResType, 325 MachineInstr &I) const; 326 }; 327 328 } // end anonymous namespace 329 330 #define GET_GLOBALISEL_IMPL 331 #include "SPIRVGenGlobalISel.inc" 332 #undef GET_GLOBALISEL_IMPL 333 334 SPIRVInstructionSelector::SPIRVInstructionSelector(const SPIRVTargetMachine &TM, 335 const SPIRVSubtarget &ST, 336 const RegisterBankInfo &RBI) 337 : InstructionSelector(), STI(ST), TII(*ST.getInstrInfo()), 338 TRI(*ST.getRegisterInfo()), RBI(RBI), GR(*ST.getSPIRVGlobalRegistry()), 339 #define GET_GLOBALISEL_PREDICATES_INIT 340 #include "SPIRVGenGlobalISel.inc" 341 #undef GET_GLOBALISEL_PREDICATES_INIT 342 #define GET_GLOBALISEL_TEMPORARIES_INIT 343 #include "SPIRVGenGlobalISel.inc" 344 #undef GET_GLOBALISEL_TEMPORARIES_INIT 345 { 346 } 347 348 void SPIRVInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits *KB, 349 CodeGenCoverage *CoverageInfo, 350 ProfileSummaryInfo *PSI, 351 BlockFrequencyInfo *BFI) { 352 MRI = &MF.getRegInfo(); 353 GR.setCurrentFunc(MF); 354 InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI); 355 } 356 357 // Ensure that register classes correspond to pattern matching rules. 358 void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) { 359 if (HasVRegsReset == &MF) 360 return; 361 HasVRegsReset = &MF; 362 363 MachineRegisterInfo &MRI = MF.getRegInfo(); 364 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) { 365 Register Reg = Register::index2VirtReg(I); 366 LLT RegType = MRI.getType(Reg); 367 if (RegType.isScalar()) 368 MRI.setType(Reg, LLT::scalar(64)); 369 else if (RegType.isPointer()) 370 MRI.setType(Reg, LLT::pointer(0, 64)); 371 else if (RegType.isVector()) 372 MRI.setType(Reg, LLT::fixed_vector(2, LLT::scalar(64))); 373 } 374 for (const auto &MBB : MF) { 375 for (const auto &MI : MBB) { 376 if (MI.getOpcode() != SPIRV::ASSIGN_TYPE) 377 continue; 378 Register DstReg = MI.getOperand(0).getReg(); 379 LLT DstType = MRI.getType(DstReg); 380 Register SrcReg = MI.getOperand(1).getReg(); 381 LLT SrcType = MRI.getType(SrcReg); 382 if (DstType != SrcType) 383 MRI.setType(DstReg, MRI.getType(SrcReg)); 384 385 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); 386 const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg); 387 if (DstRC != SrcRC && SrcRC) 388 MRI.setRegClass(DstReg, SrcRC); 389 } 390 } 391 } 392 393 static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI); 394 395 // Defined in SPIRVLegalizerInfo.cpp. 396 extern bool isTypeFoldingSupported(unsigned Opcode); 397 398 bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI) { 399 for (const auto &MO : MI.all_defs()) { 400 Register Reg = MO.getReg(); 401 if (Reg.isPhysical() || !MRI.use_nodbg_empty(Reg)) 402 return false; 403 } 404 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE || MI.isFakeUse() || 405 MI.isLifetimeMarker()) 406 return false; 407 if (MI.isPHI()) 408 return true; 409 if (MI.mayStore() || MI.isCall() || 410 (MI.mayLoad() && MI.hasOrderedMemoryRef()) || MI.isPosition() || 411 MI.isDebugInstr() || MI.isTerminator() || MI.isJumpTableDebugInfo()) 412 return false; 413 return true; 414 } 415 416 bool SPIRVInstructionSelector::select(MachineInstr &I) { 417 resetVRegsType(*I.getParent()->getParent()); 418 419 assert(I.getParent() && "Instruction should be in a basic block!"); 420 assert(I.getParent()->getParent() && "Instruction should be in a function!"); 421 422 Register Opcode = I.getOpcode(); 423 // If it's not a GMIR instruction, we've selected it already. 424 if (!isPreISelGenericOpcode(Opcode)) { 425 if (Opcode == SPIRV::ASSIGN_TYPE) { // These pseudos aren't needed any more. 426 Register DstReg = I.getOperand(0).getReg(); 427 Register SrcReg = I.getOperand(1).getReg(); 428 auto *Def = MRI->getVRegDef(SrcReg); 429 if (isTypeFoldingSupported(Def->getOpcode())) { 430 bool Res = selectImpl(I, *CoverageInfo); 431 LLVM_DEBUG({ 432 if (!Res && Def->getOpcode() != TargetOpcode::G_CONSTANT) { 433 dbgs() << "Unexpected pattern in ASSIGN_TYPE.\nInstruction: "; 434 I.print(dbgs()); 435 } 436 }); 437 assert(Res || Def->getOpcode() == TargetOpcode::G_CONSTANT); 438 if (Res) { 439 if (!isTriviallyDead(*Def, *MRI) && isDead(*Def, *MRI)) 440 DeadMIs.insert(Def); 441 return Res; 442 } 443 } 444 MRI->setRegClass(SrcReg, MRI->getRegClass(DstReg)); 445 MRI->replaceRegWith(SrcReg, DstReg); 446 GR.invalidateMachineInstr(&I); 447 I.removeFromParent(); 448 return true; 449 } else if (I.getNumDefs() == 1) { 450 // Make all vregs 64 bits (for SPIR-V IDs). 451 MRI->setType(I.getOperand(0).getReg(), LLT::scalar(64)); 452 } 453 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 454 } 455 456 if (DeadMIs.contains(&I)) { 457 // if the instruction has been already made dead by folding it away 458 // erase it 459 LLVM_DEBUG(dbgs() << "Instruction is folded and dead.\n"); 460 salvageDebugInfo(*MRI, I); 461 GR.invalidateMachineInstr(&I); 462 I.eraseFromParent(); 463 return true; 464 } 465 466 if (I.getNumOperands() != I.getNumExplicitOperands()) { 467 LLVM_DEBUG(errs() << "Generic instr has unexpected implicit operands\n"); 468 return false; 469 } 470 471 // Common code for getting return reg+type, and removing selected instr 472 // from parent occurs here. Instr-specific selection happens in spvSelect(). 473 bool HasDefs = I.getNumDefs() > 0; 474 Register ResVReg = HasDefs ? I.getOperand(0).getReg() : Register(0); 475 SPIRVType *ResType = HasDefs ? GR.getSPIRVTypeForVReg(ResVReg) : nullptr; 476 assert(!HasDefs || ResType || I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE); 477 if (spvSelect(ResVReg, ResType, I)) { 478 if (HasDefs) // Make all vregs 64 bits (for SPIR-V IDs). 479 for (unsigned i = 0; i < I.getNumDefs(); ++i) 480 MRI->setType(I.getOperand(i).getReg(), LLT::scalar(64)); 481 GR.invalidateMachineInstr(&I); 482 I.removeFromParent(); 483 return true; 484 } 485 return false; 486 } 487 488 static bool mayApplyGenericSelection(unsigned Opcode) { 489 switch (Opcode) { 490 case TargetOpcode::G_CONSTANT: 491 return false; 492 case TargetOpcode::G_SADDO: 493 case TargetOpcode::G_SSUBO: 494 return true; 495 } 496 return isTypeFoldingSupported(Opcode); 497 } 498 499 bool SPIRVInstructionSelector::BuildCOPY(Register DestReg, Register SrcReg, 500 MachineInstr &I) const { 501 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DestReg); 502 const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(SrcReg); 503 if (DstRC != SrcRC && SrcRC) 504 MRI->setRegClass(DestReg, SrcRC); 505 return BuildMI(*I.getParent(), I, I.getDebugLoc(), 506 TII.get(TargetOpcode::COPY)) 507 .addDef(DestReg) 508 .addUse(SrcReg) 509 .constrainAllUses(TII, TRI, RBI); 510 } 511 512 bool SPIRVInstructionSelector::spvSelect(Register ResVReg, 513 const SPIRVType *ResType, 514 MachineInstr &I) const { 515 const unsigned Opcode = I.getOpcode(); 516 if (mayApplyGenericSelection(Opcode)) 517 return selectImpl(I, *CoverageInfo); 518 switch (Opcode) { 519 case TargetOpcode::G_CONSTANT: 520 return selectConst(ResVReg, ResType, I.getOperand(1).getCImm()->getValue(), 521 I); 522 case TargetOpcode::G_GLOBAL_VALUE: 523 return selectGlobalValue(ResVReg, I); 524 case TargetOpcode::G_IMPLICIT_DEF: 525 return selectOpUndef(ResVReg, ResType, I); 526 case TargetOpcode::G_FREEZE: 527 return selectFreeze(ResVReg, ResType, I); 528 529 case TargetOpcode::G_INTRINSIC: 530 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: 531 case TargetOpcode::G_INTRINSIC_CONVERGENT: 532 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: 533 return selectIntrinsic(ResVReg, ResType, I); 534 case TargetOpcode::G_BITREVERSE: 535 return selectBitreverse(ResVReg, ResType, I); 536 537 case TargetOpcode::G_BUILD_VECTOR: 538 return selectBuildVector(ResVReg, ResType, I); 539 case TargetOpcode::G_SPLAT_VECTOR: 540 return selectSplatVector(ResVReg, ResType, I); 541 542 case TargetOpcode::G_SHUFFLE_VECTOR: { 543 MachineBasicBlock &BB = *I.getParent(); 544 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorShuffle)) 545 .addDef(ResVReg) 546 .addUse(GR.getSPIRVTypeID(ResType)) 547 .addUse(I.getOperand(1).getReg()) 548 .addUse(I.getOperand(2).getReg()); 549 for (auto V : I.getOperand(3).getShuffleMask()) 550 MIB.addImm(V); 551 return MIB.constrainAllUses(TII, TRI, RBI); 552 } 553 case TargetOpcode::G_MEMMOVE: 554 case TargetOpcode::G_MEMCPY: 555 case TargetOpcode::G_MEMSET: 556 return selectMemOperation(ResVReg, I); 557 558 case TargetOpcode::G_ICMP: 559 return selectICmp(ResVReg, ResType, I); 560 case TargetOpcode::G_FCMP: 561 return selectFCmp(ResVReg, ResType, I); 562 563 case TargetOpcode::G_FRAME_INDEX: 564 return selectFrameIndex(ResVReg, ResType, I); 565 566 case TargetOpcode::G_LOAD: 567 return selectLoad(ResVReg, ResType, I); 568 case TargetOpcode::G_STORE: 569 return selectStore(I); 570 571 case TargetOpcode::G_BR: 572 return selectBranch(I); 573 case TargetOpcode::G_BRCOND: 574 return selectBranchCond(I); 575 576 case TargetOpcode::G_PHI: 577 return selectPhi(ResVReg, ResType, I); 578 579 case TargetOpcode::G_FPTOSI: 580 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToS); 581 case TargetOpcode::G_FPTOUI: 582 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToU); 583 584 case TargetOpcode::G_SITOFP: 585 return selectIToF(ResVReg, ResType, I, true, SPIRV::OpConvertSToF); 586 case TargetOpcode::G_UITOFP: 587 return selectIToF(ResVReg, ResType, I, false, SPIRV::OpConvertUToF); 588 589 case TargetOpcode::G_CTPOP: 590 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitCount); 591 case TargetOpcode::G_SMIN: 592 return selectExtInst(ResVReg, ResType, I, CL::s_min, GL::SMin); 593 case TargetOpcode::G_UMIN: 594 return selectExtInst(ResVReg, ResType, I, CL::u_min, GL::UMin); 595 596 case TargetOpcode::G_SMAX: 597 return selectExtInst(ResVReg, ResType, I, CL::s_max, GL::SMax); 598 case TargetOpcode::G_UMAX: 599 return selectExtInst(ResVReg, ResType, I, CL::u_max, GL::UMax); 600 601 case TargetOpcode::G_SCMP: 602 return selectSUCmp(ResVReg, ResType, I, true); 603 case TargetOpcode::G_UCMP: 604 return selectSUCmp(ResVReg, ResType, I, false); 605 606 case TargetOpcode::G_STRICT_FMA: 607 case TargetOpcode::G_FMA: 608 return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma); 609 610 case TargetOpcode::G_STRICT_FLDEXP: 611 return selectExtInst(ResVReg, ResType, I, CL::ldexp); 612 613 case TargetOpcode::G_FPOW: 614 return selectExtInst(ResVReg, ResType, I, CL::pow, GL::Pow); 615 case TargetOpcode::G_FPOWI: 616 return selectExtInst(ResVReg, ResType, I, CL::pown); 617 618 case TargetOpcode::G_FEXP: 619 return selectExtInst(ResVReg, ResType, I, CL::exp, GL::Exp); 620 case TargetOpcode::G_FEXP2: 621 return selectExtInst(ResVReg, ResType, I, CL::exp2, GL::Exp2); 622 623 case TargetOpcode::G_FLOG: 624 return selectExtInst(ResVReg, ResType, I, CL::log, GL::Log); 625 case TargetOpcode::G_FLOG2: 626 return selectExtInst(ResVReg, ResType, I, CL::log2, GL::Log2); 627 case TargetOpcode::G_FLOG10: 628 return selectLog10(ResVReg, ResType, I); 629 630 case TargetOpcode::G_FABS: 631 return selectExtInst(ResVReg, ResType, I, CL::fabs, GL::FAbs); 632 case TargetOpcode::G_ABS: 633 return selectExtInst(ResVReg, ResType, I, CL::s_abs, GL::SAbs); 634 635 case TargetOpcode::G_FMINNUM: 636 case TargetOpcode::G_FMINIMUM: 637 return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::NMin); 638 case TargetOpcode::G_FMAXNUM: 639 case TargetOpcode::G_FMAXIMUM: 640 return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::NMax); 641 642 case TargetOpcode::G_FCOPYSIGN: 643 return selectExtInst(ResVReg, ResType, I, CL::copysign); 644 645 case TargetOpcode::G_FCEIL: 646 return selectExtInst(ResVReg, ResType, I, CL::ceil, GL::Ceil); 647 case TargetOpcode::G_FFLOOR: 648 return selectExtInst(ResVReg, ResType, I, CL::floor, GL::Floor); 649 650 case TargetOpcode::G_FCOS: 651 return selectExtInst(ResVReg, ResType, I, CL::cos, GL::Cos); 652 case TargetOpcode::G_FSIN: 653 return selectExtInst(ResVReg, ResType, I, CL::sin, GL::Sin); 654 case TargetOpcode::G_FTAN: 655 return selectExtInst(ResVReg, ResType, I, CL::tan, GL::Tan); 656 case TargetOpcode::G_FACOS: 657 return selectExtInst(ResVReg, ResType, I, CL::acos, GL::Acos); 658 case TargetOpcode::G_FASIN: 659 return selectExtInst(ResVReg, ResType, I, CL::asin, GL::Asin); 660 case TargetOpcode::G_FATAN: 661 return selectExtInst(ResVReg, ResType, I, CL::atan, GL::Atan); 662 case TargetOpcode::G_FATAN2: 663 return selectExtInst(ResVReg, ResType, I, CL::atan2, GL::Atan2); 664 case TargetOpcode::G_FCOSH: 665 return selectExtInst(ResVReg, ResType, I, CL::cosh, GL::Cosh); 666 case TargetOpcode::G_FSINH: 667 return selectExtInst(ResVReg, ResType, I, CL::sinh, GL::Sinh); 668 case TargetOpcode::G_FTANH: 669 return selectExtInst(ResVReg, ResType, I, CL::tanh, GL::Tanh); 670 671 case TargetOpcode::G_STRICT_FSQRT: 672 case TargetOpcode::G_FSQRT: 673 return selectExtInst(ResVReg, ResType, I, CL::sqrt, GL::Sqrt); 674 675 case TargetOpcode::G_CTTZ: 676 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 677 return selectExtInst(ResVReg, ResType, I, CL::ctz); 678 case TargetOpcode::G_CTLZ: 679 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 680 return selectExtInst(ResVReg, ResType, I, CL::clz); 681 682 case TargetOpcode::G_INTRINSIC_ROUND: 683 return selectExtInst(ResVReg, ResType, I, CL::round, GL::Round); 684 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 685 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven); 686 case TargetOpcode::G_INTRINSIC_TRUNC: 687 return selectExtInst(ResVReg, ResType, I, CL::trunc, GL::Trunc); 688 case TargetOpcode::G_FRINT: 689 case TargetOpcode::G_FNEARBYINT: 690 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven); 691 692 case TargetOpcode::G_SMULH: 693 return selectExtInst(ResVReg, ResType, I, CL::s_mul_hi); 694 case TargetOpcode::G_UMULH: 695 return selectExtInst(ResVReg, ResType, I, CL::u_mul_hi); 696 697 case TargetOpcode::G_SADDSAT: 698 return selectExtInst(ResVReg, ResType, I, CL::s_add_sat); 699 case TargetOpcode::G_UADDSAT: 700 return selectExtInst(ResVReg, ResType, I, CL::u_add_sat); 701 case TargetOpcode::G_SSUBSAT: 702 return selectExtInst(ResVReg, ResType, I, CL::s_sub_sat); 703 case TargetOpcode::G_USUBSAT: 704 return selectExtInst(ResVReg, ResType, I, CL::u_sub_sat); 705 706 case TargetOpcode::G_UADDO: 707 return selectOverflowArith(ResVReg, ResType, I, 708 ResType->getOpcode() == SPIRV::OpTypeVector 709 ? SPIRV::OpIAddCarryV 710 : SPIRV::OpIAddCarryS); 711 case TargetOpcode::G_USUBO: 712 return selectOverflowArith(ResVReg, ResType, I, 713 ResType->getOpcode() == SPIRV::OpTypeVector 714 ? SPIRV::OpISubBorrowV 715 : SPIRV::OpISubBorrowS); 716 case TargetOpcode::G_UMULO: 717 return selectOverflowArith(ResVReg, ResType, I, SPIRV::OpUMulExtended); 718 case TargetOpcode::G_SMULO: 719 return selectOverflowArith(ResVReg, ResType, I, SPIRV::OpSMulExtended); 720 721 case TargetOpcode::G_SEXT: 722 return selectExt(ResVReg, ResType, I, true); 723 case TargetOpcode::G_ANYEXT: 724 case TargetOpcode::G_ZEXT: 725 return selectExt(ResVReg, ResType, I, false); 726 case TargetOpcode::G_TRUNC: 727 return selectTrunc(ResVReg, ResType, I); 728 case TargetOpcode::G_FPTRUNC: 729 case TargetOpcode::G_FPEXT: 730 return selectUnOp(ResVReg, ResType, I, SPIRV::OpFConvert); 731 732 case TargetOpcode::G_PTRTOINT: 733 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertPtrToU); 734 case TargetOpcode::G_INTTOPTR: 735 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertUToPtr); 736 case TargetOpcode::G_BITCAST: 737 return selectBitcast(ResVReg, ResType, I); 738 case TargetOpcode::G_ADDRSPACE_CAST: 739 return selectAddrSpaceCast(ResVReg, ResType, I); 740 case TargetOpcode::G_PTR_ADD: { 741 // Currently, we get G_PTR_ADD only applied to global variables. 742 assert(I.getOperand(1).isReg() && I.getOperand(2).isReg()); 743 Register GV = I.getOperand(1).getReg(); 744 MachineRegisterInfo::def_instr_iterator II = MRI->def_instr_begin(GV); 745 (void)II; 746 assert(((*II).getOpcode() == TargetOpcode::G_GLOBAL_VALUE || 747 (*II).getOpcode() == TargetOpcode::COPY || 748 (*II).getOpcode() == SPIRV::OpVariable) && 749 isImm(I.getOperand(2), MRI)); 750 // It may be the initialization of a global variable. 751 bool IsGVInit = false; 752 for (MachineRegisterInfo::use_instr_iterator 753 UseIt = MRI->use_instr_begin(I.getOperand(0).getReg()), 754 UseEnd = MRI->use_instr_end(); 755 UseIt != UseEnd; UseIt = std::next(UseIt)) { 756 if ((*UseIt).getOpcode() == TargetOpcode::G_GLOBAL_VALUE || 757 (*UseIt).getOpcode() == SPIRV::OpVariable) { 758 IsGVInit = true; 759 break; 760 } 761 } 762 MachineBasicBlock &BB = *I.getParent(); 763 if (!IsGVInit) { 764 SPIRVType *GVType = GR.getSPIRVTypeForVReg(GV); 765 SPIRVType *GVPointeeType = GR.getPointeeType(GVType); 766 SPIRVType *ResPointeeType = GR.getPointeeType(ResType); 767 if (GVPointeeType && ResPointeeType && GVPointeeType != ResPointeeType) { 768 // Build a new virtual register that is associated with the required 769 // data type. 770 Register NewVReg = MRI->createGenericVirtualRegister(MRI->getType(GV)); 771 MRI->setRegClass(NewVReg, MRI->getRegClass(GV)); 772 // Having a correctly typed base we are ready to build the actually 773 // required GEP. It may not be a constant though, because all Operands 774 // of OpSpecConstantOp is to originate from other const instructions, 775 // and only the AccessChain named opcodes accept a global OpVariable 776 // instruction. We can't use an AccessChain opcode because of the type 777 // mismatch between result and base types. 778 if (!GR.isBitcastCompatible(ResType, GVType)) 779 report_fatal_error( 780 "incompatible result and operand types in a bitcast"); 781 Register ResTypeReg = GR.getSPIRVTypeID(ResType); 782 MachineInstrBuilder MIB = 783 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitcast)) 784 .addDef(NewVReg) 785 .addUse(ResTypeReg) 786 .addUse(GV); 787 return MIB.constrainAllUses(TII, TRI, RBI) && 788 BuildMI(BB, I, I.getDebugLoc(), 789 TII.get(STI.isVulkanEnv() 790 ? SPIRV::OpInBoundsAccessChain 791 : SPIRV::OpInBoundsPtrAccessChain)) 792 .addDef(ResVReg) 793 .addUse(ResTypeReg) 794 .addUse(NewVReg) 795 .addUse(I.getOperand(2).getReg()) 796 .constrainAllUses(TII, TRI, RBI); 797 } else { 798 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) 799 .addDef(ResVReg) 800 .addUse(GR.getSPIRVTypeID(ResType)) 801 .addImm( 802 static_cast<uint32_t>(SPIRV::Opcode::InBoundsPtrAccessChain)) 803 .addUse(GV) 804 .addUse(I.getOperand(2).getReg()) 805 .constrainAllUses(TII, TRI, RBI); 806 } 807 } 808 // It's possible to translate G_PTR_ADD to OpSpecConstantOp: either to 809 // initialize a global variable with a constant expression (e.g., the test 810 // case opencl/basic/progvar_prog_scope_init.ll), or for another use case 811 Register Idx = buildZerosVal(GR.getOrCreateSPIRVIntegerType(32, I, TII), I); 812 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) 813 .addDef(ResVReg) 814 .addUse(GR.getSPIRVTypeID(ResType)) 815 .addImm(static_cast<uint32_t>( 816 SPIRV::Opcode::InBoundsPtrAccessChain)) 817 .addUse(GV) 818 .addUse(Idx) 819 .addUse(I.getOperand(2).getReg()); 820 return MIB.constrainAllUses(TII, TRI, RBI); 821 } 822 823 case TargetOpcode::G_ATOMICRMW_OR: 824 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicOr); 825 case TargetOpcode::G_ATOMICRMW_ADD: 826 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicIAdd); 827 case TargetOpcode::G_ATOMICRMW_AND: 828 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicAnd); 829 case TargetOpcode::G_ATOMICRMW_MAX: 830 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMax); 831 case TargetOpcode::G_ATOMICRMW_MIN: 832 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMin); 833 case TargetOpcode::G_ATOMICRMW_SUB: 834 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicISub); 835 case TargetOpcode::G_ATOMICRMW_XOR: 836 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicXor); 837 case TargetOpcode::G_ATOMICRMW_UMAX: 838 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMax); 839 case TargetOpcode::G_ATOMICRMW_UMIN: 840 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMin); 841 case TargetOpcode::G_ATOMICRMW_XCHG: 842 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicExchange); 843 case TargetOpcode::G_ATOMIC_CMPXCHG: 844 return selectAtomicCmpXchg(ResVReg, ResType, I); 845 846 case TargetOpcode::G_ATOMICRMW_FADD: 847 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT); 848 case TargetOpcode::G_ATOMICRMW_FSUB: 849 // Translate G_ATOMICRMW_FSUB to OpAtomicFAddEXT with negative value operand 850 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT, 851 SPIRV::OpFNegate); 852 case TargetOpcode::G_ATOMICRMW_FMIN: 853 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMinEXT); 854 case TargetOpcode::G_ATOMICRMW_FMAX: 855 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMaxEXT); 856 857 case TargetOpcode::G_FENCE: 858 return selectFence(I); 859 860 case TargetOpcode::G_STACKSAVE: 861 return selectStackSave(ResVReg, ResType, I); 862 case TargetOpcode::G_STACKRESTORE: 863 return selectStackRestore(I); 864 865 case TargetOpcode::G_UNMERGE_VALUES: 866 return selectUnmergeValues(I); 867 868 // Discard gen opcodes for intrinsics which we do not expect to actually 869 // represent code after lowering or intrinsics which are not implemented but 870 // should not crash when found in a customer's LLVM IR input. 871 case TargetOpcode::G_TRAP: 872 case TargetOpcode::G_DEBUGTRAP: 873 case TargetOpcode::G_UBSANTRAP: 874 case TargetOpcode::DBG_LABEL: 875 return true; 876 877 default: 878 return false; 879 } 880 } 881 882 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, 883 const SPIRVType *ResType, 884 MachineInstr &I, 885 GL::GLSLExtInst GLInst) const { 886 return selectExtInst(ResVReg, ResType, I, 887 {{SPIRV::InstructionSet::GLSL_std_450, GLInst}}); 888 } 889 890 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, 891 const SPIRVType *ResType, 892 MachineInstr &I, 893 CL::OpenCLExtInst CLInst) const { 894 return selectExtInst(ResVReg, ResType, I, 895 {{SPIRV::InstructionSet::OpenCL_std, CLInst}}); 896 } 897 898 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, 899 const SPIRVType *ResType, 900 MachineInstr &I, 901 CL::OpenCLExtInst CLInst, 902 GL::GLSLExtInst GLInst) const { 903 ExtInstList ExtInsts = {{SPIRV::InstructionSet::OpenCL_std, CLInst}, 904 {SPIRV::InstructionSet::GLSL_std_450, GLInst}}; 905 return selectExtInst(ResVReg, ResType, I, ExtInsts); 906 } 907 908 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, 909 const SPIRVType *ResType, 910 MachineInstr &I, 911 const ExtInstList &Insts) const { 912 913 for (const auto &Ex : Insts) { 914 SPIRV::InstructionSet::InstructionSet Set = Ex.first; 915 uint32_t Opcode = Ex.second; 916 if (STI.canUseExtInstSet(Set)) { 917 MachineBasicBlock &BB = *I.getParent(); 918 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) 919 .addDef(ResVReg) 920 .addUse(GR.getSPIRVTypeID(ResType)) 921 .addImm(static_cast<uint32_t>(Set)) 922 .addImm(Opcode); 923 const unsigned NumOps = I.getNumOperands(); 924 unsigned Index = 1; 925 if (Index < NumOps && 926 I.getOperand(Index).getType() == 927 MachineOperand::MachineOperandType::MO_IntrinsicID) 928 Index = 2; 929 for (; Index < NumOps; ++Index) 930 MIB.add(I.getOperand(Index)); 931 return MIB.constrainAllUses(TII, TRI, RBI); 932 } 933 } 934 return false; 935 } 936 937 bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg, 938 const SPIRVType *ResType, 939 MachineInstr &I, 940 std::vector<Register> Srcs, 941 unsigned Opcode) const { 942 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) 943 .addDef(ResVReg) 944 .addUse(GR.getSPIRVTypeID(ResType)); 945 for (Register SReg : Srcs) { 946 MIB.addUse(SReg); 947 } 948 return MIB.constrainAllUses(TII, TRI, RBI); 949 } 950 951 bool SPIRVInstructionSelector::selectUnOp(Register ResVReg, 952 const SPIRVType *ResType, 953 MachineInstr &I, 954 unsigned Opcode) const { 955 if (STI.isOpenCLEnv() && I.getOperand(1).isReg()) { 956 Register SrcReg = I.getOperand(1).getReg(); 957 bool IsGV = false; 958 for (MachineRegisterInfo::def_instr_iterator DefIt = 959 MRI->def_instr_begin(SrcReg); 960 DefIt != MRI->def_instr_end(); DefIt = std::next(DefIt)) { 961 if ((*DefIt).getOpcode() == TargetOpcode::G_GLOBAL_VALUE) { 962 IsGV = true; 963 break; 964 } 965 } 966 if (IsGV) { 967 uint32_t SpecOpcode = 0; 968 switch (Opcode) { 969 case SPIRV::OpConvertPtrToU: 970 SpecOpcode = static_cast<uint32_t>(SPIRV::Opcode::ConvertPtrToU); 971 break; 972 case SPIRV::OpConvertUToPtr: 973 SpecOpcode = static_cast<uint32_t>(SPIRV::Opcode::ConvertUToPtr); 974 break; 975 } 976 if (SpecOpcode) 977 return BuildMI(*I.getParent(), I, I.getDebugLoc(), 978 TII.get(SPIRV::OpSpecConstantOp)) 979 .addDef(ResVReg) 980 .addUse(GR.getSPIRVTypeID(ResType)) 981 .addImm(SpecOpcode) 982 .addUse(SrcReg) 983 .constrainAllUses(TII, TRI, RBI); 984 } 985 } 986 return selectOpWithSrcs(ResVReg, ResType, I, {I.getOperand(1).getReg()}, 987 Opcode); 988 } 989 990 bool SPIRVInstructionSelector::selectBitcast(Register ResVReg, 991 const SPIRVType *ResType, 992 MachineInstr &I) const { 993 Register OpReg = I.getOperand(1).getReg(); 994 SPIRVType *OpType = OpReg.isValid() ? GR.getSPIRVTypeForVReg(OpReg) : nullptr; 995 if (!GR.isBitcastCompatible(ResType, OpType)) 996 report_fatal_error("incompatible result and operand types in a bitcast"); 997 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitcast); 998 } 999 1000 static void addMemoryOperands(MachineMemOperand *MemOp, 1001 MachineInstrBuilder &MIB) { 1002 uint32_t SpvMemOp = static_cast<uint32_t>(SPIRV::MemoryOperand::None); 1003 if (MemOp->isVolatile()) 1004 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Volatile); 1005 if (MemOp->isNonTemporal()) 1006 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Nontemporal); 1007 if (MemOp->getAlign().value()) 1008 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Aligned); 1009 1010 if (SpvMemOp != static_cast<uint32_t>(SPIRV::MemoryOperand::None)) { 1011 MIB.addImm(SpvMemOp); 1012 if (SpvMemOp & static_cast<uint32_t>(SPIRV::MemoryOperand::Aligned)) 1013 MIB.addImm(MemOp->getAlign().value()); 1014 } 1015 } 1016 1017 static void addMemoryOperands(uint64_t Flags, MachineInstrBuilder &MIB) { 1018 uint32_t SpvMemOp = static_cast<uint32_t>(SPIRV::MemoryOperand::None); 1019 if (Flags & MachineMemOperand::Flags::MOVolatile) 1020 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Volatile); 1021 if (Flags & MachineMemOperand::Flags::MONonTemporal) 1022 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Nontemporal); 1023 1024 if (SpvMemOp != static_cast<uint32_t>(SPIRV::MemoryOperand::None)) 1025 MIB.addImm(SpvMemOp); 1026 } 1027 1028 bool SPIRVInstructionSelector::selectLoad(Register ResVReg, 1029 const SPIRVType *ResType, 1030 MachineInstr &I) const { 1031 unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0; 1032 Register Ptr = I.getOperand(1 + OpOffset).getReg(); 1033 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) 1034 .addDef(ResVReg) 1035 .addUse(GR.getSPIRVTypeID(ResType)) 1036 .addUse(Ptr); 1037 if (!I.getNumMemOperands()) { 1038 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS || 1039 I.getOpcode() == 1040 TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS); 1041 addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB); 1042 } else { 1043 addMemoryOperands(*I.memoperands_begin(), MIB); 1044 } 1045 return MIB.constrainAllUses(TII, TRI, RBI); 1046 } 1047 1048 bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const { 1049 unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0; 1050 Register StoreVal = I.getOperand(0 + OpOffset).getReg(); 1051 Register Ptr = I.getOperand(1 + OpOffset).getReg(); 1052 MachineBasicBlock &BB = *I.getParent(); 1053 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpStore)) 1054 .addUse(Ptr) 1055 .addUse(StoreVal); 1056 if (!I.getNumMemOperands()) { 1057 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS || 1058 I.getOpcode() == 1059 TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS); 1060 addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB); 1061 } else { 1062 addMemoryOperands(*I.memoperands_begin(), MIB); 1063 } 1064 return MIB.constrainAllUses(TII, TRI, RBI); 1065 } 1066 1067 bool SPIRVInstructionSelector::selectStackSave(Register ResVReg, 1068 const SPIRVType *ResType, 1069 MachineInstr &I) const { 1070 if (!STI.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array)) 1071 report_fatal_error( 1072 "llvm.stacksave intrinsic: this instruction requires the following " 1073 "SPIR-V extension: SPV_INTEL_variable_length_array", 1074 false); 1075 MachineBasicBlock &BB = *I.getParent(); 1076 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSaveMemoryINTEL)) 1077 .addDef(ResVReg) 1078 .addUse(GR.getSPIRVTypeID(ResType)) 1079 .constrainAllUses(TII, TRI, RBI); 1080 } 1081 1082 bool SPIRVInstructionSelector::selectStackRestore(MachineInstr &I) const { 1083 if (!STI.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array)) 1084 report_fatal_error( 1085 "llvm.stackrestore intrinsic: this instruction requires the following " 1086 "SPIR-V extension: SPV_INTEL_variable_length_array", 1087 false); 1088 if (!I.getOperand(0).isReg()) 1089 return false; 1090 MachineBasicBlock &BB = *I.getParent(); 1091 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpRestoreMemoryINTEL)) 1092 .addUse(I.getOperand(0).getReg()) 1093 .constrainAllUses(TII, TRI, RBI); 1094 } 1095 1096 bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg, 1097 MachineInstr &I) const { 1098 MachineBasicBlock &BB = *I.getParent(); 1099 Register SrcReg = I.getOperand(1).getReg(); 1100 bool Result = true; 1101 if (I.getOpcode() == TargetOpcode::G_MEMSET) { 1102 assert(I.getOperand(1).isReg() && I.getOperand(2).isReg()); 1103 unsigned Val = getIConstVal(I.getOperand(1).getReg(), MRI); 1104 unsigned Num = getIConstVal(I.getOperand(2).getReg(), MRI); 1105 SPIRVType *ValTy = GR.getOrCreateSPIRVIntegerType(8, I, TII); 1106 SPIRVType *ArrTy = GR.getOrCreateSPIRVArrayType(ValTy, Num, I, TII); 1107 Register Const = GR.getOrCreateConstIntArray(Val, Num, I, ArrTy, TII); 1108 SPIRVType *VarTy = GR.getOrCreateSPIRVPointerType( 1109 ArrTy, I, TII, SPIRV::StorageClass::UniformConstant); 1110 // TODO: check if we have such GV, add init, use buildGlobalVariable. 1111 Function &CurFunction = GR.CurMF->getFunction(); 1112 Type *LLVMArrTy = 1113 ArrayType::get(IntegerType::get(CurFunction.getContext(), 8), Num); 1114 // Module takes ownership of the global var. 1115 GlobalVariable *GV = new GlobalVariable(*CurFunction.getParent(), LLVMArrTy, 1116 true, GlobalValue::InternalLinkage, 1117 Constant::getNullValue(LLVMArrTy)); 1118 Register VarReg = MRI->createGenericVirtualRegister(LLT::scalar(64)); 1119 GR.add(GV, GR.CurMF, VarReg); 1120 1121 Result &= 1122 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpVariable)) 1123 .addDef(VarReg) 1124 .addUse(GR.getSPIRVTypeID(VarTy)) 1125 .addImm(SPIRV::StorageClass::UniformConstant) 1126 .addUse(Const) 1127 .constrainAllUses(TII, TRI, RBI); 1128 buildOpDecorate(VarReg, I, TII, SPIRV::Decoration::Constant, {}); 1129 SPIRVType *SourceTy = GR.getOrCreateSPIRVPointerType( 1130 ValTy, I, TII, SPIRV::StorageClass::UniformConstant); 1131 SrcReg = MRI->createGenericVirtualRegister(LLT::scalar(64)); 1132 selectOpWithSrcs(SrcReg, SourceTy, I, {VarReg}, SPIRV::OpBitcast); 1133 } 1134 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCopyMemorySized)) 1135 .addUse(I.getOperand(0).getReg()) 1136 .addUse(SrcReg) 1137 .addUse(I.getOperand(2).getReg()); 1138 if (I.getNumMemOperands()) 1139 addMemoryOperands(*I.memoperands_begin(), MIB); 1140 Result &= MIB.constrainAllUses(TII, TRI, RBI); 1141 if (ResVReg.isValid() && ResVReg != MIB->getOperand(0).getReg()) 1142 Result &= BuildCOPY(ResVReg, MIB->getOperand(0).getReg(), I); 1143 return Result; 1144 } 1145 1146 bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, 1147 const SPIRVType *ResType, 1148 MachineInstr &I, 1149 unsigned NewOpcode, 1150 unsigned NegateOpcode) const { 1151 bool Result = true; 1152 assert(I.hasOneMemOperand()); 1153 const MachineMemOperand *MemOp = *I.memoperands_begin(); 1154 uint32_t Scope = static_cast<uint32_t>(getMemScope( 1155 GR.CurMF->getFunction().getContext(), MemOp->getSyncScopeID())); 1156 auto ScopeConstant = buildI32Constant(Scope, I); 1157 Register ScopeReg = ScopeConstant.first; 1158 Result &= ScopeConstant.second; 1159 1160 Register Ptr = I.getOperand(1).getReg(); 1161 // TODO: Changed as it's implemented in the translator. See test/atomicrmw.ll 1162 // auto ScSem = 1163 // getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr)); 1164 AtomicOrdering AO = MemOp->getSuccessOrdering(); 1165 uint32_t MemSem = static_cast<uint32_t>(getMemSemantics(AO)); 1166 auto MemSemConstant = buildI32Constant(MemSem /*| ScSem*/, I); 1167 Register MemSemReg = MemSemConstant.first; 1168 Result &= MemSemConstant.second; 1169 1170 Register ValueReg = I.getOperand(2).getReg(); 1171 if (NegateOpcode != 0) { 1172 // Translation with negative value operand is requested 1173 Register TmpReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass); 1174 Result &= selectOpWithSrcs(TmpReg, ResType, I, {ValueReg}, NegateOpcode); 1175 ValueReg = TmpReg; 1176 } 1177 1178 return Result && 1179 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) 1180 .addDef(ResVReg) 1181 .addUse(GR.getSPIRVTypeID(ResType)) 1182 .addUse(Ptr) 1183 .addUse(ScopeReg) 1184 .addUse(MemSemReg) 1185 .addUse(ValueReg) 1186 .constrainAllUses(TII, TRI, RBI); 1187 } 1188 1189 bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const { 1190 unsigned ArgI = I.getNumOperands() - 1; 1191 Register SrcReg = 1192 I.getOperand(ArgI).isReg() ? I.getOperand(ArgI).getReg() : Register(0); 1193 SPIRVType *DefType = 1194 SrcReg.isValid() ? GR.getSPIRVTypeForVReg(SrcReg) : nullptr; 1195 if (!DefType || DefType->getOpcode() != SPIRV::OpTypeVector) 1196 report_fatal_error( 1197 "cannot select G_UNMERGE_VALUES with a non-vector argument"); 1198 1199 SPIRVType *ScalarType = 1200 GR.getSPIRVTypeForVReg(DefType->getOperand(1).getReg()); 1201 MachineBasicBlock &BB = *I.getParent(); 1202 bool Res = false; 1203 for (unsigned i = 0; i < I.getNumDefs(); ++i) { 1204 Register ResVReg = I.getOperand(i).getReg(); 1205 SPIRVType *ResType = GR.getSPIRVTypeForVReg(ResVReg); 1206 if (!ResType) { 1207 // There was no "assign type" actions, let's fix this now 1208 ResType = ScalarType; 1209 MRI->setRegClass(ResVReg, GR.getRegClass(ResType)); 1210 MRI->setType(ResVReg, LLT::scalar(GR.getScalarOrVectorBitWidth(ResType))); 1211 GR.assignSPIRVTypeToVReg(ResType, ResVReg, *GR.CurMF); 1212 } 1213 auto MIB = 1214 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) 1215 .addDef(ResVReg) 1216 .addUse(GR.getSPIRVTypeID(ResType)) 1217 .addUse(SrcReg) 1218 .addImm(static_cast<int64_t>(i)); 1219 Res |= MIB.constrainAllUses(TII, TRI, RBI); 1220 } 1221 return Res; 1222 } 1223 1224 bool SPIRVInstructionSelector::selectFence(MachineInstr &I) const { 1225 AtomicOrdering AO = AtomicOrdering(I.getOperand(0).getImm()); 1226 uint32_t MemSem = static_cast<uint32_t>(getMemSemantics(AO)); 1227 auto MemSemConstant = buildI32Constant(MemSem, I); 1228 Register MemSemReg = MemSemConstant.first; 1229 bool Result = MemSemConstant.second; 1230 SyncScope::ID Ord = SyncScope::ID(I.getOperand(1).getImm()); 1231 uint32_t Scope = static_cast<uint32_t>( 1232 getMemScope(GR.CurMF->getFunction().getContext(), Ord)); 1233 auto ScopeConstant = buildI32Constant(Scope, I); 1234 Register ScopeReg = ScopeConstant.first; 1235 Result &= ScopeConstant.second; 1236 MachineBasicBlock &BB = *I.getParent(); 1237 return Result && 1238 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpMemoryBarrier)) 1239 .addUse(ScopeReg) 1240 .addUse(MemSemReg) 1241 .constrainAllUses(TII, TRI, RBI); 1242 } 1243 1244 bool SPIRVInstructionSelector::selectOverflowArith(Register ResVReg, 1245 const SPIRVType *ResType, 1246 MachineInstr &I, 1247 unsigned Opcode) const { 1248 Type *ResTy = nullptr; 1249 StringRef ResName; 1250 if (!GR.findValueAttrs(&I, ResTy, ResName)) 1251 report_fatal_error( 1252 "Not enough info to select the arithmetic with overflow instruction"); 1253 if (!ResTy || !ResTy->isStructTy()) 1254 report_fatal_error("Expect struct type result for the arithmetic " 1255 "with overflow instruction"); 1256 // "Result Type must be from OpTypeStruct. The struct must have two members, 1257 // and the two members must be the same type." 1258 Type *ResElemTy = cast<StructType>(ResTy)->getElementType(0); 1259 ResTy = StructType::get(ResElemTy, ResElemTy); 1260 // Build SPIR-V types and constant(s) if needed. 1261 MachineIRBuilder MIRBuilder(I); 1262 SPIRVType *StructType = GR.getOrCreateSPIRVType( 1263 ResTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false); 1264 assert(I.getNumDefs() > 1 && "Not enought operands"); 1265 SPIRVType *BoolType = GR.getOrCreateSPIRVBoolType(I, TII); 1266 unsigned N = GR.getScalarOrVectorComponentCount(ResType); 1267 if (N > 1) 1268 BoolType = GR.getOrCreateSPIRVVectorType(BoolType, N, I, TII); 1269 Register BoolTypeReg = GR.getSPIRVTypeID(BoolType); 1270 Register ZeroReg = buildZerosVal(ResType, I); 1271 // A new virtual register to store the result struct. 1272 Register StructVReg = MRI->createGenericVirtualRegister(LLT::scalar(64)); 1273 MRI->setRegClass(StructVReg, &SPIRV::IDRegClass); 1274 // Build the result name if needed. 1275 if (ResName.size() > 0) 1276 buildOpName(StructVReg, ResName, MIRBuilder); 1277 // Build the arithmetic with overflow instruction. 1278 MachineBasicBlock &BB = *I.getParent(); 1279 auto MIB = 1280 BuildMI(BB, MIRBuilder.getInsertPt(), I.getDebugLoc(), TII.get(Opcode)) 1281 .addDef(StructVReg) 1282 .addUse(GR.getSPIRVTypeID(StructType)); 1283 for (unsigned i = I.getNumDefs(); i < I.getNumOperands(); ++i) 1284 MIB.addUse(I.getOperand(i).getReg()); 1285 bool Result = MIB.constrainAllUses(TII, TRI, RBI); 1286 // Build instructions to extract fields of the instruction's result. 1287 // A new virtual register to store the higher part of the result struct. 1288 Register HigherVReg = MRI->createGenericVirtualRegister(LLT::scalar(64)); 1289 MRI->setRegClass(HigherVReg, &SPIRV::iIDRegClass); 1290 for (unsigned i = 0; i < I.getNumDefs(); ++i) { 1291 auto MIB = 1292 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) 1293 .addDef(i == 1 ? HigherVReg : I.getOperand(i).getReg()) 1294 .addUse(GR.getSPIRVTypeID(ResType)) 1295 .addUse(StructVReg) 1296 .addImm(i); 1297 Result &= MIB.constrainAllUses(TII, TRI, RBI); 1298 } 1299 // Build boolean value from the higher part. 1300 return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual)) 1301 .addDef(I.getOperand(1).getReg()) 1302 .addUse(BoolTypeReg) 1303 .addUse(HigherVReg) 1304 .addUse(ZeroReg) 1305 .constrainAllUses(TII, TRI, RBI); 1306 } 1307 1308 bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg, 1309 const SPIRVType *ResType, 1310 MachineInstr &I) const { 1311 bool Result = true; 1312 Register ScopeReg; 1313 Register MemSemEqReg; 1314 Register MemSemNeqReg; 1315 Register Ptr = I.getOperand(2).getReg(); 1316 if (!isa<GIntrinsic>(I)) { 1317 assert(I.hasOneMemOperand()); 1318 const MachineMemOperand *MemOp = *I.memoperands_begin(); 1319 unsigned Scope = static_cast<uint32_t>(getMemScope( 1320 GR.CurMF->getFunction().getContext(), MemOp->getSyncScopeID())); 1321 auto ScopeConstant = buildI32Constant(Scope, I); 1322 ScopeReg = ScopeConstant.first; 1323 Result &= ScopeConstant.second; 1324 1325 unsigned ScSem = static_cast<uint32_t>( 1326 getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr))); 1327 AtomicOrdering AO = MemOp->getSuccessOrdering(); 1328 unsigned MemSemEq = static_cast<uint32_t>(getMemSemantics(AO)) | ScSem; 1329 auto MemSemEqConstant = buildI32Constant(MemSemEq, I); 1330 MemSemEqReg = MemSemEqConstant.first; 1331 Result &= MemSemEqConstant.second; 1332 AtomicOrdering FO = MemOp->getFailureOrdering(); 1333 unsigned MemSemNeq = static_cast<uint32_t>(getMemSemantics(FO)) | ScSem; 1334 if (MemSemEq == MemSemNeq) 1335 MemSemNeqReg = MemSemEqReg; 1336 else { 1337 auto MemSemNeqConstant = buildI32Constant(MemSemEq, I); 1338 MemSemNeqReg = MemSemNeqConstant.first; 1339 Result &= MemSemNeqConstant.second; 1340 } 1341 } else { 1342 ScopeReg = I.getOperand(5).getReg(); 1343 MemSemEqReg = I.getOperand(6).getReg(); 1344 MemSemNeqReg = I.getOperand(7).getReg(); 1345 } 1346 1347 Register Cmp = I.getOperand(3).getReg(); 1348 Register Val = I.getOperand(4).getReg(); 1349 SPIRVType *SpvValTy = GR.getSPIRVTypeForVReg(Val); 1350 Register ACmpRes = MRI->createVirtualRegister(&SPIRV::iIDRegClass); 1351 const DebugLoc &DL = I.getDebugLoc(); 1352 Result &= 1353 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpAtomicCompareExchange)) 1354 .addDef(ACmpRes) 1355 .addUse(GR.getSPIRVTypeID(SpvValTy)) 1356 .addUse(Ptr) 1357 .addUse(ScopeReg) 1358 .addUse(MemSemEqReg) 1359 .addUse(MemSemNeqReg) 1360 .addUse(Val) 1361 .addUse(Cmp) 1362 .constrainAllUses(TII, TRI, RBI); 1363 Register CmpSuccReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass); 1364 SPIRVType *BoolTy = GR.getOrCreateSPIRVBoolType(I, TII); 1365 Result &= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpIEqual)) 1366 .addDef(CmpSuccReg) 1367 .addUse(GR.getSPIRVTypeID(BoolTy)) 1368 .addUse(ACmpRes) 1369 .addUse(Cmp) 1370 .constrainAllUses(TII, TRI, RBI); 1371 Register TmpReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass); 1372 Result &= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) 1373 .addDef(TmpReg) 1374 .addUse(GR.getSPIRVTypeID(ResType)) 1375 .addUse(ACmpRes) 1376 .addUse(GR.getOrCreateUndef(I, ResType, TII)) 1377 .addImm(0) 1378 .constrainAllUses(TII, TRI, RBI); 1379 return Result && 1380 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) 1381 .addDef(ResVReg) 1382 .addUse(GR.getSPIRVTypeID(ResType)) 1383 .addUse(CmpSuccReg) 1384 .addUse(TmpReg) 1385 .addImm(1) 1386 .constrainAllUses(TII, TRI, RBI); 1387 } 1388 1389 static bool isGenericCastablePtr(SPIRV::StorageClass::StorageClass SC) { 1390 switch (SC) { 1391 case SPIRV::StorageClass::Workgroup: 1392 case SPIRV::StorageClass::CrossWorkgroup: 1393 case SPIRV::StorageClass::Function: 1394 return true; 1395 default: 1396 return false; 1397 } 1398 } 1399 1400 static bool isUSMStorageClass(SPIRV::StorageClass::StorageClass SC) { 1401 switch (SC) { 1402 case SPIRV::StorageClass::DeviceOnlyINTEL: 1403 case SPIRV::StorageClass::HostOnlyINTEL: 1404 return true; 1405 default: 1406 return false; 1407 } 1408 } 1409 1410 // Returns true ResVReg is referred only from global vars and OpName's. 1411 static bool isASCastInGVar(MachineRegisterInfo *MRI, Register ResVReg) { 1412 bool IsGRef = false; 1413 bool IsAllowedRefs = 1414 std::all_of(MRI->use_instr_begin(ResVReg), MRI->use_instr_end(), 1415 [&IsGRef](auto const &It) { 1416 unsigned Opcode = It.getOpcode(); 1417 if (Opcode == SPIRV::OpConstantComposite || 1418 Opcode == SPIRV::OpVariable || 1419 isSpvIntrinsic(It, Intrinsic::spv_init_global)) 1420 return IsGRef = true; 1421 return Opcode == SPIRV::OpName; 1422 }); 1423 return IsAllowedRefs && IsGRef; 1424 } 1425 1426 Register SPIRVInstructionSelector::getUcharPtrTypeReg( 1427 MachineInstr &I, SPIRV::StorageClass::StorageClass SC) const { 1428 return GR.getSPIRVTypeID(GR.getOrCreateSPIRVPointerType( 1429 GR.getOrCreateSPIRVIntegerType(8, I, TII), I, TII, SC)); 1430 } 1431 1432 MachineInstrBuilder 1433 SPIRVInstructionSelector::buildSpecConstantOp(MachineInstr &I, Register Dest, 1434 Register Src, Register DestType, 1435 uint32_t Opcode) const { 1436 return BuildMI(*I.getParent(), I, I.getDebugLoc(), 1437 TII.get(SPIRV::OpSpecConstantOp)) 1438 .addDef(Dest) 1439 .addUse(DestType) 1440 .addImm(Opcode) 1441 .addUse(Src); 1442 } 1443 1444 MachineInstrBuilder 1445 SPIRVInstructionSelector::buildConstGenericPtr(MachineInstr &I, Register SrcPtr, 1446 SPIRVType *SrcPtrTy) const { 1447 SPIRVType *GenericPtrTy = GR.getOrCreateSPIRVPointerType( 1448 GR.getPointeeType(SrcPtrTy), I, TII, SPIRV::StorageClass::Generic); 1449 Register Tmp = MRI->createVirtualRegister(&SPIRV::pIDRegClass); 1450 MRI->setType(Tmp, LLT::pointer(storageClassToAddressSpace( 1451 SPIRV::StorageClass::Generic), 1452 GR.getPointerSize())); 1453 MachineFunction *MF = I.getParent()->getParent(); 1454 GR.assignSPIRVTypeToVReg(GenericPtrTy, Tmp, *MF); 1455 MachineInstrBuilder MIB = buildSpecConstantOp( 1456 I, Tmp, SrcPtr, GR.getSPIRVTypeID(GenericPtrTy), 1457 static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric)); 1458 GR.add(MIB.getInstr(), MF, Tmp); 1459 return MIB; 1460 } 1461 1462 // In SPIR-V address space casting can only happen to and from the Generic 1463 // storage class. We can also only cast Workgroup, CrossWorkgroup, or Function 1464 // pointers to and from Generic pointers. As such, we can convert e.g. from 1465 // Workgroup to Function by going via a Generic pointer as an intermediary. All 1466 // other combinations can only be done by a bitcast, and are probably not safe. 1467 bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg, 1468 const SPIRVType *ResType, 1469 MachineInstr &I) const { 1470 MachineBasicBlock &BB = *I.getParent(); 1471 const DebugLoc &DL = I.getDebugLoc(); 1472 1473 Register SrcPtr = I.getOperand(1).getReg(); 1474 SPIRVType *SrcPtrTy = GR.getSPIRVTypeForVReg(SrcPtr); 1475 1476 // don't generate a cast for a null that may be represented by OpTypeInt 1477 if (SrcPtrTy->getOpcode() != SPIRV::OpTypePointer || 1478 ResType->getOpcode() != SPIRV::OpTypePointer) 1479 return BuildCOPY(ResVReg, SrcPtr, I); 1480 1481 SPIRV::StorageClass::StorageClass SrcSC = GR.getPointerStorageClass(SrcPtrTy); 1482 SPIRV::StorageClass::StorageClass DstSC = GR.getPointerStorageClass(ResType); 1483 1484 if (isASCastInGVar(MRI, ResVReg)) { 1485 // AddrSpaceCast uses within OpVariable and OpConstantComposite instructions 1486 // are expressed by OpSpecConstantOp with an Opcode. 1487 // TODO: maybe insert a check whether the Kernel capability was declared and 1488 // so PtrCastToGeneric/GenericCastToPtr are available. 1489 unsigned SpecOpcode = 1490 DstSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(SrcSC) 1491 ? static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric) 1492 : (SrcSC == SPIRV::StorageClass::Generic && 1493 isGenericCastablePtr(DstSC) 1494 ? static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr) 1495 : 0); 1496 // TODO: OpConstantComposite expects i8*, so we are forced to forget a 1497 // correct value of ResType and use general i8* instead. Maybe this should 1498 // be addressed in the emit-intrinsic step to infer a correct 1499 // OpConstantComposite type. 1500 if (SpecOpcode) { 1501 return buildSpecConstantOp(I, ResVReg, SrcPtr, 1502 getUcharPtrTypeReg(I, DstSC), SpecOpcode) 1503 .constrainAllUses(TII, TRI, RBI); 1504 } else if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) { 1505 MachineInstrBuilder MIB = buildConstGenericPtr(I, SrcPtr, SrcPtrTy); 1506 return MIB.constrainAllUses(TII, TRI, RBI) && 1507 buildSpecConstantOp( 1508 I, ResVReg, MIB->getOperand(0).getReg(), 1509 getUcharPtrTypeReg(I, DstSC), 1510 static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr)) 1511 .constrainAllUses(TII, TRI, RBI); 1512 } 1513 } 1514 1515 // don't generate a cast between identical storage classes 1516 if (SrcSC == DstSC) 1517 return BuildCOPY(ResVReg, SrcPtr, I); 1518 1519 if ((SrcSC == SPIRV::StorageClass::Function && 1520 DstSC == SPIRV::StorageClass::Private) || 1521 (DstSC == SPIRV::StorageClass::Function && 1522 SrcSC == SPIRV::StorageClass::Private)) 1523 return BuildCOPY(ResVReg, SrcPtr, I); 1524 1525 // Casting from an eligible pointer to Generic. 1526 if (DstSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(SrcSC)) 1527 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric); 1528 // Casting from Generic to an eligible pointer. 1529 if (SrcSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(DstSC)) 1530 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr); 1531 // Casting between 2 eligible pointers using Generic as an intermediary. 1532 if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) { 1533 Register Tmp = MRI->createVirtualRegister(&SPIRV::iIDRegClass); 1534 SPIRVType *GenericPtrTy = GR.getOrCreateSPIRVPointerType( 1535 GR.getPointeeType(SrcPtrTy), I, TII, SPIRV::StorageClass::Generic); 1536 bool Result = BuildMI(BB, I, DL, TII.get(SPIRV::OpPtrCastToGeneric)) 1537 .addDef(Tmp) 1538 .addUse(GR.getSPIRVTypeID(GenericPtrTy)) 1539 .addUse(SrcPtr) 1540 .constrainAllUses(TII, TRI, RBI); 1541 return Result && BuildMI(BB, I, DL, TII.get(SPIRV::OpGenericCastToPtr)) 1542 .addDef(ResVReg) 1543 .addUse(GR.getSPIRVTypeID(ResType)) 1544 .addUse(Tmp) 1545 .constrainAllUses(TII, TRI, RBI); 1546 } 1547 1548 // Check if instructions from the SPV_INTEL_usm_storage_classes extension may 1549 // be applied 1550 if (isUSMStorageClass(SrcSC) && DstSC == SPIRV::StorageClass::CrossWorkgroup) 1551 return selectUnOp(ResVReg, ResType, I, 1552 SPIRV::OpPtrCastToCrossWorkgroupINTEL); 1553 if (SrcSC == SPIRV::StorageClass::CrossWorkgroup && isUSMStorageClass(DstSC)) 1554 return selectUnOp(ResVReg, ResType, I, 1555 SPIRV::OpCrossWorkgroupCastToPtrINTEL); 1556 if (isUSMStorageClass(SrcSC) && DstSC == SPIRV::StorageClass::Generic) 1557 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric); 1558 if (SrcSC == SPIRV::StorageClass::Generic && isUSMStorageClass(DstSC)) 1559 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr); 1560 1561 // Bitcast for pointers requires that the address spaces must match 1562 return false; 1563 } 1564 1565 static unsigned getFCmpOpcode(unsigned PredNum) { 1566 auto Pred = static_cast<CmpInst::Predicate>(PredNum); 1567 switch (Pred) { 1568 case CmpInst::FCMP_OEQ: 1569 return SPIRV::OpFOrdEqual; 1570 case CmpInst::FCMP_OGE: 1571 return SPIRV::OpFOrdGreaterThanEqual; 1572 case CmpInst::FCMP_OGT: 1573 return SPIRV::OpFOrdGreaterThan; 1574 case CmpInst::FCMP_OLE: 1575 return SPIRV::OpFOrdLessThanEqual; 1576 case CmpInst::FCMP_OLT: 1577 return SPIRV::OpFOrdLessThan; 1578 case CmpInst::FCMP_ONE: 1579 return SPIRV::OpFOrdNotEqual; 1580 case CmpInst::FCMP_ORD: 1581 return SPIRV::OpOrdered; 1582 case CmpInst::FCMP_UEQ: 1583 return SPIRV::OpFUnordEqual; 1584 case CmpInst::FCMP_UGE: 1585 return SPIRV::OpFUnordGreaterThanEqual; 1586 case CmpInst::FCMP_UGT: 1587 return SPIRV::OpFUnordGreaterThan; 1588 case CmpInst::FCMP_ULE: 1589 return SPIRV::OpFUnordLessThanEqual; 1590 case CmpInst::FCMP_ULT: 1591 return SPIRV::OpFUnordLessThan; 1592 case CmpInst::FCMP_UNE: 1593 return SPIRV::OpFUnordNotEqual; 1594 case CmpInst::FCMP_UNO: 1595 return SPIRV::OpUnordered; 1596 default: 1597 llvm_unreachable("Unknown predicate type for FCmp"); 1598 } 1599 } 1600 1601 static unsigned getICmpOpcode(unsigned PredNum) { 1602 auto Pred = static_cast<CmpInst::Predicate>(PredNum); 1603 switch (Pred) { 1604 case CmpInst::ICMP_EQ: 1605 return SPIRV::OpIEqual; 1606 case CmpInst::ICMP_NE: 1607 return SPIRV::OpINotEqual; 1608 case CmpInst::ICMP_SGE: 1609 return SPIRV::OpSGreaterThanEqual; 1610 case CmpInst::ICMP_SGT: 1611 return SPIRV::OpSGreaterThan; 1612 case CmpInst::ICMP_SLE: 1613 return SPIRV::OpSLessThanEqual; 1614 case CmpInst::ICMP_SLT: 1615 return SPIRV::OpSLessThan; 1616 case CmpInst::ICMP_UGE: 1617 return SPIRV::OpUGreaterThanEqual; 1618 case CmpInst::ICMP_UGT: 1619 return SPIRV::OpUGreaterThan; 1620 case CmpInst::ICMP_ULE: 1621 return SPIRV::OpULessThanEqual; 1622 case CmpInst::ICMP_ULT: 1623 return SPIRV::OpULessThan; 1624 default: 1625 llvm_unreachable("Unknown predicate type for ICmp"); 1626 } 1627 } 1628 1629 static unsigned getPtrCmpOpcode(unsigned Pred) { 1630 switch (static_cast<CmpInst::Predicate>(Pred)) { 1631 case CmpInst::ICMP_EQ: 1632 return SPIRV::OpPtrEqual; 1633 case CmpInst::ICMP_NE: 1634 return SPIRV::OpPtrNotEqual; 1635 default: 1636 llvm_unreachable("Unknown predicate type for pointer comparison"); 1637 } 1638 } 1639 1640 // Return the logical operation, or abort if none exists. 1641 static unsigned getBoolCmpOpcode(unsigned PredNum) { 1642 auto Pred = static_cast<CmpInst::Predicate>(PredNum); 1643 switch (Pred) { 1644 case CmpInst::ICMP_EQ: 1645 return SPIRV::OpLogicalEqual; 1646 case CmpInst::ICMP_NE: 1647 return SPIRV::OpLogicalNotEqual; 1648 default: 1649 llvm_unreachable("Unknown predicate type for Bool comparison"); 1650 } 1651 } 1652 1653 static APFloat getZeroFP(const Type *LLVMFloatTy) { 1654 if (!LLVMFloatTy) 1655 return APFloat::getZero(APFloat::IEEEsingle()); 1656 switch (LLVMFloatTy->getScalarType()->getTypeID()) { 1657 case Type::HalfTyID: 1658 return APFloat::getZero(APFloat::IEEEhalf()); 1659 default: 1660 case Type::FloatTyID: 1661 return APFloat::getZero(APFloat::IEEEsingle()); 1662 case Type::DoubleTyID: 1663 return APFloat::getZero(APFloat::IEEEdouble()); 1664 } 1665 } 1666 1667 static APFloat getOneFP(const Type *LLVMFloatTy) { 1668 if (!LLVMFloatTy) 1669 return APFloat::getOne(APFloat::IEEEsingle()); 1670 switch (LLVMFloatTy->getScalarType()->getTypeID()) { 1671 case Type::HalfTyID: 1672 return APFloat::getOne(APFloat::IEEEhalf()); 1673 default: 1674 case Type::FloatTyID: 1675 return APFloat::getOne(APFloat::IEEEsingle()); 1676 case Type::DoubleTyID: 1677 return APFloat::getOne(APFloat::IEEEdouble()); 1678 } 1679 } 1680 1681 bool SPIRVInstructionSelector::selectAnyOrAll(Register ResVReg, 1682 const SPIRVType *ResType, 1683 MachineInstr &I, 1684 unsigned OpAnyOrAll) const { 1685 assert(I.getNumOperands() == 3); 1686 assert(I.getOperand(2).isReg()); 1687 MachineBasicBlock &BB = *I.getParent(); 1688 Register InputRegister = I.getOperand(2).getReg(); 1689 SPIRVType *InputType = GR.getSPIRVTypeForVReg(InputRegister); 1690 1691 if (!InputType) 1692 report_fatal_error("Input Type could not be determined."); 1693 1694 bool IsBoolTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeBool); 1695 bool IsVectorTy = InputType->getOpcode() == SPIRV::OpTypeVector; 1696 if (IsBoolTy && !IsVectorTy) { 1697 assert(ResVReg == I.getOperand(0).getReg()); 1698 return BuildCOPY(ResVReg, InputRegister, I); 1699 } 1700 1701 bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat); 1702 unsigned SpirvNotEqualId = 1703 IsFloatTy ? SPIRV::OpFOrdNotEqual : SPIRV::OpINotEqual; 1704 SPIRVType *SpvBoolScalarTy = GR.getOrCreateSPIRVBoolType(I, TII); 1705 SPIRVType *SpvBoolTy = SpvBoolScalarTy; 1706 Register NotEqualReg = ResVReg; 1707 1708 if (IsVectorTy) { 1709 NotEqualReg = IsBoolTy ? InputRegister 1710 : MRI->createVirtualRegister(&SPIRV::iIDRegClass); 1711 const unsigned NumElts = InputType->getOperand(2).getImm(); 1712 SpvBoolTy = GR.getOrCreateSPIRVVectorType(SpvBoolTy, NumElts, I, TII); 1713 } 1714 1715 bool Result = true; 1716 if (!IsBoolTy) { 1717 Register ConstZeroReg = 1718 IsFloatTy ? buildZerosValF(InputType, I) : buildZerosVal(InputType, I); 1719 1720 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SpirvNotEqualId)) 1721 .addDef(NotEqualReg) 1722 .addUse(GR.getSPIRVTypeID(SpvBoolTy)) 1723 .addUse(InputRegister) 1724 .addUse(ConstZeroReg) 1725 .constrainAllUses(TII, TRI, RBI); 1726 } 1727 1728 if (!IsVectorTy) 1729 return Result; 1730 1731 return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(OpAnyOrAll)) 1732 .addDef(ResVReg) 1733 .addUse(GR.getSPIRVTypeID(SpvBoolScalarTy)) 1734 .addUse(NotEqualReg) 1735 .constrainAllUses(TII, TRI, RBI); 1736 } 1737 1738 bool SPIRVInstructionSelector::selectAll(Register ResVReg, 1739 const SPIRVType *ResType, 1740 MachineInstr &I) const { 1741 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAll); 1742 } 1743 1744 bool SPIRVInstructionSelector::selectAny(Register ResVReg, 1745 const SPIRVType *ResType, 1746 MachineInstr &I) const { 1747 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAny); 1748 } 1749 1750 // Select the OpDot instruction for the given float dot 1751 bool SPIRVInstructionSelector::selectFloatDot(Register ResVReg, 1752 const SPIRVType *ResType, 1753 MachineInstr &I) const { 1754 assert(I.getNumOperands() == 4); 1755 assert(I.getOperand(2).isReg()); 1756 assert(I.getOperand(3).isReg()); 1757 1758 [[maybe_unused]] SPIRVType *VecType = 1759 GR.getSPIRVTypeForVReg(I.getOperand(2).getReg()); 1760 1761 assert(VecType->getOpcode() == SPIRV::OpTypeVector && 1762 GR.getScalarOrVectorComponentCount(VecType) > 1 && 1763 "dot product requires a vector of at least 2 components"); 1764 1765 [[maybe_unused]] SPIRVType *EltType = 1766 GR.getSPIRVTypeForVReg(VecType->getOperand(1).getReg()); 1767 1768 assert(EltType->getOpcode() == SPIRV::OpTypeFloat); 1769 1770 MachineBasicBlock &BB = *I.getParent(); 1771 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpDot)) 1772 .addDef(ResVReg) 1773 .addUse(GR.getSPIRVTypeID(ResType)) 1774 .addUse(I.getOperand(2).getReg()) 1775 .addUse(I.getOperand(3).getReg()) 1776 .constrainAllUses(TII, TRI, RBI); 1777 } 1778 1779 bool SPIRVInstructionSelector::selectIntegerDot(Register ResVReg, 1780 const SPIRVType *ResType, 1781 MachineInstr &I, 1782 bool Signed) const { 1783 assert(I.getNumOperands() == 4); 1784 assert(I.getOperand(2).isReg()); 1785 assert(I.getOperand(3).isReg()); 1786 MachineBasicBlock &BB = *I.getParent(); 1787 1788 auto DotOp = Signed ? SPIRV::OpSDot : SPIRV::OpUDot; 1789 return BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp)) 1790 .addDef(ResVReg) 1791 .addUse(GR.getSPIRVTypeID(ResType)) 1792 .addUse(I.getOperand(2).getReg()) 1793 .addUse(I.getOperand(3).getReg()) 1794 .constrainAllUses(TII, TRI, RBI); 1795 } 1796 1797 // Since pre-1.6 SPIRV has no integer dot implementation, 1798 // expand by piecewise multiplying and adding the results 1799 bool SPIRVInstructionSelector::selectIntegerDotExpansion( 1800 Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { 1801 assert(I.getNumOperands() == 4); 1802 assert(I.getOperand(2).isReg()); 1803 assert(I.getOperand(3).isReg()); 1804 MachineBasicBlock &BB = *I.getParent(); 1805 1806 // Multiply the vectors, then sum the results 1807 Register Vec0 = I.getOperand(2).getReg(); 1808 Register Vec1 = I.getOperand(3).getReg(); 1809 Register TmpVec = MRI->createVirtualRegister(GR.getRegClass(ResType)); 1810 SPIRVType *VecType = GR.getSPIRVTypeForVReg(Vec0); 1811 1812 bool Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulV)) 1813 .addDef(TmpVec) 1814 .addUse(GR.getSPIRVTypeID(VecType)) 1815 .addUse(Vec0) 1816 .addUse(Vec1) 1817 .constrainAllUses(TII, TRI, RBI); 1818 1819 assert(VecType->getOpcode() == SPIRV::OpTypeVector && 1820 GR.getScalarOrVectorComponentCount(VecType) > 1 && 1821 "dot product requires a vector of at least 2 components"); 1822 1823 Register Res = MRI->createVirtualRegister(GR.getRegClass(ResType)); 1824 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) 1825 .addDef(Res) 1826 .addUse(GR.getSPIRVTypeID(ResType)) 1827 .addUse(TmpVec) 1828 .addImm(0) 1829 .constrainAllUses(TII, TRI, RBI); 1830 1831 for (unsigned i = 1; i < GR.getScalarOrVectorComponentCount(VecType); i++) { 1832 Register Elt = MRI->createVirtualRegister(GR.getRegClass(ResType)); 1833 1834 Result &= 1835 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) 1836 .addDef(Elt) 1837 .addUse(GR.getSPIRVTypeID(ResType)) 1838 .addUse(TmpVec) 1839 .addImm(i) 1840 .constrainAllUses(TII, TRI, RBI); 1841 1842 Register Sum = i < GR.getScalarOrVectorComponentCount(VecType) - 1 1843 ? MRI->createVirtualRegister(GR.getRegClass(ResType)) 1844 : ResVReg; 1845 1846 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) 1847 .addDef(Sum) 1848 .addUse(GR.getSPIRVTypeID(ResType)) 1849 .addUse(Res) 1850 .addUse(Elt) 1851 .constrainAllUses(TII, TRI, RBI); 1852 Res = Sum; 1853 } 1854 1855 return Result; 1856 } 1857 1858 template <bool Signed> 1859 bool SPIRVInstructionSelector::selectDot4AddPacked(Register ResVReg, 1860 const SPIRVType *ResType, 1861 MachineInstr &I) const { 1862 assert(I.getNumOperands() == 5); 1863 assert(I.getOperand(2).isReg()); 1864 assert(I.getOperand(3).isReg()); 1865 assert(I.getOperand(4).isReg()); 1866 MachineBasicBlock &BB = *I.getParent(); 1867 1868 auto DotOp = Signed ? SPIRV::OpSDot : SPIRV::OpUDot; 1869 Register Dot = MRI->createVirtualRegister(GR.getRegClass(ResType)); 1870 bool Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp)) 1871 .addDef(Dot) 1872 .addUse(GR.getSPIRVTypeID(ResType)) 1873 .addUse(I.getOperand(2).getReg()) 1874 .addUse(I.getOperand(3).getReg()) 1875 .constrainAllUses(TII, TRI, RBI); 1876 1877 return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) 1878 .addDef(ResVReg) 1879 .addUse(GR.getSPIRVTypeID(ResType)) 1880 .addUse(Dot) 1881 .addUse(I.getOperand(4).getReg()) 1882 .constrainAllUses(TII, TRI, RBI); 1883 } 1884 1885 // Since pre-1.6 SPIRV has no DotProductInput4x8BitPacked implementation, 1886 // extract the elements of the packed inputs, multiply them and add the result 1887 // to the accumulator. 1888 template <bool Signed> 1889 bool SPIRVInstructionSelector::selectDot4AddPackedExpansion( 1890 Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { 1891 assert(I.getNumOperands() == 5); 1892 assert(I.getOperand(2).isReg()); 1893 assert(I.getOperand(3).isReg()); 1894 assert(I.getOperand(4).isReg()); 1895 MachineBasicBlock &BB = *I.getParent(); 1896 1897 bool Result = true; 1898 1899 // Acc = C 1900 Register Acc = I.getOperand(4).getReg(); 1901 SPIRVType *EltType = GR.getOrCreateSPIRVIntegerType(8, I, TII); 1902 auto ExtractOp = 1903 Signed ? SPIRV::OpBitFieldSExtract : SPIRV::OpBitFieldUExtract; 1904 1905 // Extract the i8 element, multiply and add it to the accumulator 1906 for (unsigned i = 0; i < 4; i++) { 1907 // A[i] 1908 Register AElt = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1909 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp)) 1910 .addDef(AElt) 1911 .addUse(GR.getSPIRVTypeID(ResType)) 1912 .addUse(I.getOperand(2).getReg()) 1913 .addUse(GR.getOrCreateConstInt(i * 8, I, EltType, TII)) 1914 .addUse(GR.getOrCreateConstInt(8, I, EltType, TII)) 1915 .constrainAllUses(TII, TRI, RBI); 1916 1917 // B[i] 1918 Register BElt = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1919 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp)) 1920 .addDef(BElt) 1921 .addUse(GR.getSPIRVTypeID(ResType)) 1922 .addUse(I.getOperand(3).getReg()) 1923 .addUse(GR.getOrCreateConstInt(i * 8, I, EltType, TII)) 1924 .addUse(GR.getOrCreateConstInt(8, I, EltType, TII)) 1925 .constrainAllUses(TII, TRI, RBI); 1926 1927 // A[i] * B[i] 1928 Register Mul = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1929 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulS)) 1930 .addDef(Mul) 1931 .addUse(GR.getSPIRVTypeID(ResType)) 1932 .addUse(AElt) 1933 .addUse(BElt) 1934 .constrainAllUses(TII, TRI, RBI); 1935 1936 // Discard 24 highest-bits so that stored i32 register is i8 equivalent 1937 Register MaskMul = MRI->createVirtualRegister(&SPIRV::IDRegClass); 1938 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp)) 1939 .addDef(MaskMul) 1940 .addUse(GR.getSPIRVTypeID(ResType)) 1941 .addUse(Mul) 1942 .addUse(GR.getOrCreateConstInt(0, I, EltType, TII)) 1943 .addUse(GR.getOrCreateConstInt(8, I, EltType, TII)) 1944 .constrainAllUses(TII, TRI, RBI); 1945 1946 // Acc = Acc + A[i] * B[i] 1947 Register Sum = 1948 i < 3 ? MRI->createVirtualRegister(&SPIRV::IDRegClass) : ResVReg; 1949 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) 1950 .addDef(Sum) 1951 .addUse(GR.getSPIRVTypeID(ResType)) 1952 .addUse(Acc) 1953 .addUse(MaskMul) 1954 .constrainAllUses(TII, TRI, RBI); 1955 1956 Acc = Sum; 1957 } 1958 1959 return Result; 1960 } 1961 1962 /// Transform saturate(x) to clamp(x, 0.0f, 1.0f) as SPIRV 1963 /// does not have a saturate builtin. 1964 bool SPIRVInstructionSelector::selectSaturate(Register ResVReg, 1965 const SPIRVType *ResType, 1966 MachineInstr &I) const { 1967 assert(I.getNumOperands() == 3); 1968 assert(I.getOperand(2).isReg()); 1969 MachineBasicBlock &BB = *I.getParent(); 1970 Register VZero = buildZerosValF(ResType, I); 1971 Register VOne = buildOnesValF(ResType, I); 1972 1973 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) 1974 .addDef(ResVReg) 1975 .addUse(GR.getSPIRVTypeID(ResType)) 1976 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) 1977 .addImm(GL::FClamp) 1978 .addUse(I.getOperand(2).getReg()) 1979 .addUse(VZero) 1980 .addUse(VOne) 1981 .constrainAllUses(TII, TRI, RBI); 1982 } 1983 1984 bool SPIRVInstructionSelector::selectSign(Register ResVReg, 1985 const SPIRVType *ResType, 1986 MachineInstr &I) const { 1987 assert(I.getNumOperands() == 3); 1988 assert(I.getOperand(2).isReg()); 1989 MachineBasicBlock &BB = *I.getParent(); 1990 Register InputRegister = I.getOperand(2).getReg(); 1991 SPIRVType *InputType = GR.getSPIRVTypeForVReg(InputRegister); 1992 auto &DL = I.getDebugLoc(); 1993 1994 if (!InputType) 1995 report_fatal_error("Input Type could not be determined."); 1996 1997 bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat); 1998 1999 unsigned SignBitWidth = GR.getScalarOrVectorBitWidth(InputType); 2000 unsigned ResBitWidth = GR.getScalarOrVectorBitWidth(ResType); 2001 2002 bool NeedsConversion = IsFloatTy || SignBitWidth != ResBitWidth; 2003 2004 auto SignOpcode = IsFloatTy ? GL::FSign : GL::SSign; 2005 Register SignReg = NeedsConversion 2006 ? MRI->createVirtualRegister(&SPIRV::IDRegClass) 2007 : ResVReg; 2008 2009 bool Result = 2010 BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst)) 2011 .addDef(SignReg) 2012 .addUse(GR.getSPIRVTypeID(InputType)) 2013 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) 2014 .addImm(SignOpcode) 2015 .addUse(InputRegister) 2016 .constrainAllUses(TII, TRI, RBI); 2017 2018 if (NeedsConversion) { 2019 auto ConvertOpcode = IsFloatTy ? SPIRV::OpConvertFToS : SPIRV::OpSConvert; 2020 Result &= BuildMI(*I.getParent(), I, DL, TII.get(ConvertOpcode)) 2021 .addDef(ResVReg) 2022 .addUse(GR.getSPIRVTypeID(ResType)) 2023 .addUse(SignReg) 2024 .constrainAllUses(TII, TRI, RBI); 2025 } 2026 2027 return Result; 2028 } 2029 2030 bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg, 2031 const SPIRVType *ResType, 2032 MachineInstr &I, 2033 unsigned Opcode) const { 2034 MachineBasicBlock &BB = *I.getParent(); 2035 SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII); 2036 2037 auto BMI = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) 2038 .addDef(ResVReg) 2039 .addUse(GR.getSPIRVTypeID(ResType)) 2040 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, 2041 IntTy, TII)); 2042 2043 for (unsigned J = 2; J < I.getNumOperands(); J++) { 2044 BMI.addUse(I.getOperand(J).getReg()); 2045 } 2046 2047 return BMI.constrainAllUses(TII, TRI, RBI); 2048 } 2049 2050 bool SPIRVInstructionSelector::selectWaveActiveCountBits( 2051 Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { 2052 2053 SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII); 2054 SPIRVType *BallotType = GR.getOrCreateSPIRVVectorType(IntTy, 4, I, TII); 2055 Register BallotReg = MRI->createVirtualRegister(GR.getRegClass(BallotType)); 2056 bool Result = selectWaveOpInst(BallotReg, BallotType, I, 2057 SPIRV::OpGroupNonUniformBallot); 2058 2059 MachineBasicBlock &BB = *I.getParent(); 2060 Result &= 2061 BuildMI(BB, I, I.getDebugLoc(), 2062 TII.get(SPIRV::OpGroupNonUniformBallotBitCount)) 2063 .addDef(ResVReg) 2064 .addUse(GR.getSPIRVTypeID(ResType)) 2065 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII)) 2066 .addImm(SPIRV::GroupOperation::Reduce) 2067 .addUse(BallotReg) 2068 .constrainAllUses(TII, TRI, RBI); 2069 2070 return Result; 2071 } 2072 2073 bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg, 2074 const SPIRVType *ResType, 2075 MachineInstr &I) const { 2076 MachineBasicBlock &BB = *I.getParent(); 2077 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitReverse)) 2078 .addDef(ResVReg) 2079 .addUse(GR.getSPIRVTypeID(ResType)) 2080 .addUse(I.getOperand(1).getReg()) 2081 .constrainAllUses(TII, TRI, RBI); 2082 } 2083 2084 bool SPIRVInstructionSelector::selectFreeze(Register ResVReg, 2085 const SPIRVType *ResType, 2086 MachineInstr &I) const { 2087 // There is no way to implement `freeze` correctly without support on SPIR-V 2088 // standard side, but we may at least address a simple (static) case when 2089 // undef/poison value presence is obvious. The main benefit of even 2090 // incomplete `freeze` support is preventing of translation from crashing due 2091 // to lack of support on legalization and instruction selection steps. 2092 if (!I.getOperand(0).isReg() || !I.getOperand(1).isReg()) 2093 return false; 2094 Register OpReg = I.getOperand(1).getReg(); 2095 if (MachineInstr *Def = MRI->getVRegDef(OpReg)) { 2096 Register Reg; 2097 switch (Def->getOpcode()) { 2098 case SPIRV::ASSIGN_TYPE: 2099 if (MachineInstr *AssignToDef = 2100 MRI->getVRegDef(Def->getOperand(1).getReg())) { 2101 if (AssignToDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) 2102 Reg = Def->getOperand(2).getReg(); 2103 } 2104 break; 2105 case SPIRV::OpUndef: 2106 Reg = Def->getOperand(1).getReg(); 2107 break; 2108 } 2109 unsigned DestOpCode; 2110 if (Reg.isValid()) { 2111 DestOpCode = SPIRV::OpConstantNull; 2112 } else { 2113 DestOpCode = TargetOpcode::COPY; 2114 Reg = OpReg; 2115 } 2116 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DestOpCode)) 2117 .addDef(I.getOperand(0).getReg()) 2118 .addUse(Reg) 2119 .constrainAllUses(TII, TRI, RBI); 2120 } 2121 return false; 2122 } 2123 2124 static unsigned getArrayComponentCount(MachineRegisterInfo *MRI, 2125 const SPIRVType *ResType) { 2126 Register OpReg = ResType->getOperand(2).getReg(); 2127 SPIRVType *OpDef = MRI->getVRegDef(OpReg); 2128 if (!OpDef) 2129 return 0; 2130 if (OpDef->getOpcode() == SPIRV::ASSIGN_TYPE && 2131 OpDef->getOperand(1).isReg()) { 2132 if (SPIRVType *RefDef = MRI->getVRegDef(OpDef->getOperand(1).getReg())) 2133 OpDef = RefDef; 2134 } 2135 unsigned N = OpDef->getOpcode() == TargetOpcode::G_CONSTANT 2136 ? OpDef->getOperand(1).getCImm()->getValue().getZExtValue() 2137 : 0; 2138 return N; 2139 } 2140 2141 // Return true if the type represents a constant register 2142 static bool isConstReg(MachineRegisterInfo *MRI, SPIRVType *OpDef, 2143 SmallPtrSet<SPIRVType *, 4> &Visited) { 2144 if (OpDef->getOpcode() == SPIRV::ASSIGN_TYPE && 2145 OpDef->getOperand(1).isReg()) { 2146 if (SPIRVType *RefDef = MRI->getVRegDef(OpDef->getOperand(1).getReg())) 2147 OpDef = RefDef; 2148 } 2149 2150 if (Visited.contains(OpDef)) 2151 return true; 2152 Visited.insert(OpDef); 2153 2154 unsigned Opcode = OpDef->getOpcode(); 2155 switch (Opcode) { 2156 case TargetOpcode::G_CONSTANT: 2157 case TargetOpcode::G_FCONSTANT: 2158 return true; 2159 case TargetOpcode::G_INTRINSIC: 2160 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: 2161 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: 2162 return cast<GIntrinsic>(*OpDef).getIntrinsicID() == 2163 Intrinsic::spv_const_composite; 2164 case TargetOpcode::G_BUILD_VECTOR: 2165 case TargetOpcode::G_SPLAT_VECTOR: { 2166 for (unsigned i = OpDef->getNumExplicitDefs(); i < OpDef->getNumOperands(); 2167 i++) { 2168 SPIRVType *OpNestedDef = 2169 OpDef->getOperand(i).isReg() 2170 ? MRI->getVRegDef(OpDef->getOperand(i).getReg()) 2171 : nullptr; 2172 if (OpNestedDef && !isConstReg(MRI, OpNestedDef, Visited)) 2173 return false; 2174 } 2175 return true; 2176 } 2177 } 2178 return false; 2179 } 2180 2181 // Return true if the virtual register represents a constant 2182 static bool isConstReg(MachineRegisterInfo *MRI, Register OpReg) { 2183 SmallPtrSet<SPIRVType *, 4> Visited; 2184 if (SPIRVType *OpDef = MRI->getVRegDef(OpReg)) 2185 return isConstReg(MRI, OpDef, Visited); 2186 return false; 2187 } 2188 2189 bool SPIRVInstructionSelector::selectBuildVector(Register ResVReg, 2190 const SPIRVType *ResType, 2191 MachineInstr &I) const { 2192 unsigned N = 0; 2193 if (ResType->getOpcode() == SPIRV::OpTypeVector) 2194 N = GR.getScalarOrVectorComponentCount(ResType); 2195 else if (ResType->getOpcode() == SPIRV::OpTypeArray) 2196 N = getArrayComponentCount(MRI, ResType); 2197 else 2198 report_fatal_error("Cannot select G_BUILD_VECTOR with a non-vector result"); 2199 if (I.getNumExplicitOperands() - I.getNumExplicitDefs() != N) 2200 report_fatal_error("G_BUILD_VECTOR and the result type are inconsistent"); 2201 2202 // check if we may construct a constant vector 2203 bool IsConst = true; 2204 for (unsigned i = I.getNumExplicitDefs(); 2205 i < I.getNumExplicitOperands() && IsConst; ++i) 2206 if (!isConstReg(MRI, I.getOperand(i).getReg())) 2207 IsConst = false; 2208 2209 if (!IsConst && N < 2) 2210 report_fatal_error( 2211 "There must be at least two constituent operands in a vector"); 2212 2213 MRI->setRegClass(ResVReg, GR.getRegClass(ResType)); 2214 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), 2215 TII.get(IsConst ? SPIRV::OpConstantComposite 2216 : SPIRV::OpCompositeConstruct)) 2217 .addDef(ResVReg) 2218 .addUse(GR.getSPIRVTypeID(ResType)); 2219 for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i) 2220 MIB.addUse(I.getOperand(i).getReg()); 2221 return MIB.constrainAllUses(TII, TRI, RBI); 2222 } 2223 2224 bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg, 2225 const SPIRVType *ResType, 2226 MachineInstr &I) const { 2227 unsigned N = 0; 2228 if (ResType->getOpcode() == SPIRV::OpTypeVector) 2229 N = GR.getScalarOrVectorComponentCount(ResType); 2230 else if (ResType->getOpcode() == SPIRV::OpTypeArray) 2231 N = getArrayComponentCount(MRI, ResType); 2232 else 2233 report_fatal_error("Cannot select G_SPLAT_VECTOR with a non-vector result"); 2234 2235 unsigned OpIdx = I.getNumExplicitDefs(); 2236 if (!I.getOperand(OpIdx).isReg()) 2237 report_fatal_error("Unexpected argument in G_SPLAT_VECTOR"); 2238 2239 // check if we may construct a constant vector 2240 Register OpReg = I.getOperand(OpIdx).getReg(); 2241 bool IsConst = isConstReg(MRI, OpReg); 2242 2243 if (!IsConst && N < 2) 2244 report_fatal_error( 2245 "There must be at least two constituent operands in a vector"); 2246 2247 MRI->setRegClass(ResVReg, GR.getRegClass(ResType)); 2248 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), 2249 TII.get(IsConst ? SPIRV::OpConstantComposite 2250 : SPIRV::OpCompositeConstruct)) 2251 .addDef(ResVReg) 2252 .addUse(GR.getSPIRVTypeID(ResType)); 2253 for (unsigned i = 0; i < N; ++i) 2254 MIB.addUse(OpReg); 2255 return MIB.constrainAllUses(TII, TRI, RBI); 2256 } 2257 2258 bool SPIRVInstructionSelector::selectDiscard(Register ResVReg, 2259 const SPIRVType *ResType, 2260 MachineInstr &I) const { 2261 2262 unsigned Opcode; 2263 2264 if (STI.canUseExtension( 2265 SPIRV::Extension::SPV_EXT_demote_to_helper_invocation) || 2266 STI.isAtLeastSPIRVVer(llvm::VersionTuple(1, 6))) { 2267 Opcode = SPIRV::OpDemoteToHelperInvocation; 2268 } else { 2269 Opcode = SPIRV::OpKill; 2270 // OpKill must be the last operation of any basic block. 2271 if (MachineInstr *NextI = I.getNextNode()) { 2272 GR.invalidateMachineInstr(NextI); 2273 NextI->removeFromParent(); 2274 } 2275 } 2276 2277 MachineBasicBlock &BB = *I.getParent(); 2278 return BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) 2279 .constrainAllUses(TII, TRI, RBI); 2280 } 2281 2282 bool SPIRVInstructionSelector::selectCmp(Register ResVReg, 2283 const SPIRVType *ResType, 2284 unsigned CmpOpc, 2285 MachineInstr &I) const { 2286 Register Cmp0 = I.getOperand(2).getReg(); 2287 Register Cmp1 = I.getOperand(3).getReg(); 2288 assert(GR.getSPIRVTypeForVReg(Cmp0)->getOpcode() == 2289 GR.getSPIRVTypeForVReg(Cmp1)->getOpcode() && 2290 "CMP operands should have the same type"); 2291 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CmpOpc)) 2292 .addDef(ResVReg) 2293 .addUse(GR.getSPIRVTypeID(ResType)) 2294 .addUse(Cmp0) 2295 .addUse(Cmp1) 2296 .constrainAllUses(TII, TRI, RBI); 2297 } 2298 2299 bool SPIRVInstructionSelector::selectICmp(Register ResVReg, 2300 const SPIRVType *ResType, 2301 MachineInstr &I) const { 2302 auto Pred = I.getOperand(1).getPredicate(); 2303 unsigned CmpOpc; 2304 2305 Register CmpOperand = I.getOperand(2).getReg(); 2306 if (GR.isScalarOfType(CmpOperand, SPIRV::OpTypePointer)) 2307 CmpOpc = getPtrCmpOpcode(Pred); 2308 else if (GR.isScalarOrVectorOfType(CmpOperand, SPIRV::OpTypeBool)) 2309 CmpOpc = getBoolCmpOpcode(Pred); 2310 else 2311 CmpOpc = getICmpOpcode(Pred); 2312 return selectCmp(ResVReg, ResType, CmpOpc, I); 2313 } 2314 2315 void SPIRVInstructionSelector::renderFImm64(MachineInstrBuilder &MIB, 2316 const MachineInstr &I, 2317 int OpIdx) const { 2318 assert(I.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1 && 2319 "Expected G_FCONSTANT"); 2320 const ConstantFP *FPImm = I.getOperand(1).getFPImm(); 2321 addNumImm(FPImm->getValueAPF().bitcastToAPInt(), MIB); 2322 } 2323 2324 void SPIRVInstructionSelector::renderImm32(MachineInstrBuilder &MIB, 2325 const MachineInstr &I, 2326 int OpIdx) const { 2327 assert(I.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && 2328 "Expected G_CONSTANT"); 2329 addNumImm(I.getOperand(1).getCImm()->getValue(), MIB); 2330 } 2331 2332 std::pair<Register, bool> 2333 SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I, 2334 const SPIRVType *ResType) const { 2335 Type *LLVMTy = IntegerType::get(GR.CurMF->getFunction().getContext(), 32); 2336 const SPIRVType *SpvI32Ty = 2337 ResType ? ResType : GR.getOrCreateSPIRVIntegerType(32, I, TII); 2338 // Find a constant in DT or build a new one. 2339 auto ConstInt = ConstantInt::get(LLVMTy, Val); 2340 Register NewReg = GR.find(ConstInt, GR.CurMF); 2341 bool Result = true; 2342 if (!NewReg.isValid()) { 2343 NewReg = MRI->createGenericVirtualRegister(LLT::scalar(64)); 2344 GR.add(ConstInt, GR.CurMF, NewReg); 2345 MachineInstr *MI; 2346 MachineBasicBlock &BB = *I.getParent(); 2347 if (Val == 0) { 2348 MI = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) 2349 .addDef(NewReg) 2350 .addUse(GR.getSPIRVTypeID(SpvI32Ty)); 2351 } else { 2352 MI = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI)) 2353 .addDef(NewReg) 2354 .addUse(GR.getSPIRVTypeID(SpvI32Ty)) 2355 .addImm(APInt(32, Val).getZExtValue()); 2356 } 2357 Result &= constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); 2358 } 2359 return {NewReg, Result}; 2360 } 2361 2362 bool SPIRVInstructionSelector::selectFCmp(Register ResVReg, 2363 const SPIRVType *ResType, 2364 MachineInstr &I) const { 2365 unsigned CmpOp = getFCmpOpcode(I.getOperand(1).getPredicate()); 2366 return selectCmp(ResVReg, ResType, CmpOp, I); 2367 } 2368 2369 Register SPIRVInstructionSelector::buildZerosVal(const SPIRVType *ResType, 2370 MachineInstr &I) const { 2371 // OpenCL uses nulls for Zero. In HLSL we don't use null constants. 2372 bool ZeroAsNull = STI.isOpenCLEnv(); 2373 if (ResType->getOpcode() == SPIRV::OpTypeVector) 2374 return GR.getOrCreateConstVector(0UL, I, ResType, TII, ZeroAsNull); 2375 return GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull); 2376 } 2377 2378 Register SPIRVInstructionSelector::buildZerosValF(const SPIRVType *ResType, 2379 MachineInstr &I) const { 2380 // OpenCL uses nulls for Zero. In HLSL we don't use null constants. 2381 bool ZeroAsNull = STI.isOpenCLEnv(); 2382 APFloat VZero = getZeroFP(GR.getTypeForSPIRVType(ResType)); 2383 if (ResType->getOpcode() == SPIRV::OpTypeVector) 2384 return GR.getOrCreateConstVector(VZero, I, ResType, TII, ZeroAsNull); 2385 return GR.getOrCreateConstFP(VZero, I, ResType, TII, ZeroAsNull); 2386 } 2387 2388 Register SPIRVInstructionSelector::buildOnesValF(const SPIRVType *ResType, 2389 MachineInstr &I) const { 2390 // OpenCL uses nulls for Zero. In HLSL we don't use null constants. 2391 bool ZeroAsNull = STI.isOpenCLEnv(); 2392 APFloat VOne = getOneFP(GR.getTypeForSPIRVType(ResType)); 2393 if (ResType->getOpcode() == SPIRV::OpTypeVector) 2394 return GR.getOrCreateConstVector(VOne, I, ResType, TII, ZeroAsNull); 2395 return GR.getOrCreateConstFP(VOne, I, ResType, TII, ZeroAsNull); 2396 } 2397 2398 Register SPIRVInstructionSelector::buildOnesVal(bool AllOnes, 2399 const SPIRVType *ResType, 2400 MachineInstr &I) const { 2401 unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType); 2402 APInt One = 2403 AllOnes ? APInt::getAllOnes(BitWidth) : APInt::getOneBitSet(BitWidth, 0); 2404 if (ResType->getOpcode() == SPIRV::OpTypeVector) 2405 return GR.getOrCreateConstVector(One.getZExtValue(), I, ResType, TII); 2406 return GR.getOrCreateConstInt(One.getZExtValue(), I, ResType, TII); 2407 } 2408 2409 bool SPIRVInstructionSelector::selectSelect(Register ResVReg, 2410 const SPIRVType *ResType, 2411 MachineInstr &I, 2412 bool IsSigned) const { 2413 // To extend a bool, we need to use OpSelect between constants. 2414 Register ZeroReg = buildZerosVal(ResType, I); 2415 Register OneReg = buildOnesVal(IsSigned, ResType, I); 2416 bool IsScalarBool = 2417 GR.isScalarOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool); 2418 unsigned Opcode = 2419 IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectVIVCond; 2420 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) 2421 .addDef(ResVReg) 2422 .addUse(GR.getSPIRVTypeID(ResType)) 2423 .addUse(I.getOperand(1).getReg()) 2424 .addUse(OneReg) 2425 .addUse(ZeroReg) 2426 .constrainAllUses(TII, TRI, RBI); 2427 } 2428 2429 bool SPIRVInstructionSelector::selectIToF(Register ResVReg, 2430 const SPIRVType *ResType, 2431 MachineInstr &I, bool IsSigned, 2432 unsigned Opcode) const { 2433 Register SrcReg = I.getOperand(1).getReg(); 2434 // We can convert bool value directly to float type without OpConvert*ToF, 2435 // however the translator generates OpSelect+OpConvert*ToF, so we do the same. 2436 if (GR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) { 2437 unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType); 2438 SPIRVType *TmpType = GR.getOrCreateSPIRVIntegerType(BitWidth, I, TII); 2439 if (ResType->getOpcode() == SPIRV::OpTypeVector) { 2440 const unsigned NumElts = ResType->getOperand(2).getImm(); 2441 TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII); 2442 } 2443 SrcReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass); 2444 selectSelect(SrcReg, TmpType, I, false); 2445 } 2446 return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, Opcode); 2447 } 2448 2449 bool SPIRVInstructionSelector::selectExt(Register ResVReg, 2450 const SPIRVType *ResType, 2451 MachineInstr &I, bool IsSigned) const { 2452 Register SrcReg = I.getOperand(1).getReg(); 2453 if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool)) 2454 return selectSelect(ResVReg, ResType, I, IsSigned); 2455 2456 SPIRVType *SrcType = GR.getSPIRVTypeForVReg(SrcReg); 2457 if (SrcType == ResType) 2458 return BuildCOPY(ResVReg, SrcReg, I); 2459 2460 unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert; 2461 return selectUnOp(ResVReg, ResType, I, Opcode); 2462 } 2463 2464 bool SPIRVInstructionSelector::selectSUCmp(Register ResVReg, 2465 const SPIRVType *ResType, 2466 MachineInstr &I, 2467 bool IsSigned) const { 2468 MachineIRBuilder MIRBuilder(I); 2469 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); 2470 MachineBasicBlock &BB = *I.getParent(); 2471 // Ensure we have bool. 2472 SPIRVType *BoolType = GR.getOrCreateSPIRVBoolType(I, TII); 2473 unsigned N = GR.getScalarOrVectorComponentCount(ResType); 2474 if (N > 1) 2475 BoolType = GR.getOrCreateSPIRVVectorType(BoolType, N, I, TII); 2476 Register BoolTypeReg = GR.getSPIRVTypeID(BoolType); 2477 // Build less-than-equal and less-than. 2478 // TODO: replace with one-liner createVirtualRegister() from 2479 // llvm/lib/Target/SPIRV/SPIRVUtils.cpp when PR #116609 is merged. 2480 Register IsLessEqReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); 2481 MRI->setType(IsLessEqReg, LLT::scalar(64)); 2482 GR.assignSPIRVTypeToVReg(ResType, IsLessEqReg, MIRBuilder.getMF()); 2483 bool Result = BuildMI(BB, I, I.getDebugLoc(), 2484 TII.get(IsSigned ? SPIRV::OpSLessThanEqual 2485 : SPIRV::OpULessThanEqual)) 2486 .addDef(IsLessEqReg) 2487 .addUse(BoolTypeReg) 2488 .addUse(I.getOperand(1).getReg()) 2489 .addUse(I.getOperand(2).getReg()) 2490 .constrainAllUses(TII, TRI, RBI); 2491 Register IsLessReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); 2492 MRI->setType(IsLessReg, LLT::scalar(64)); 2493 GR.assignSPIRVTypeToVReg(ResType, IsLessReg, MIRBuilder.getMF()); 2494 Result &= BuildMI(BB, I, I.getDebugLoc(), 2495 TII.get(IsSigned ? SPIRV::OpSLessThan : SPIRV::OpULessThan)) 2496 .addDef(IsLessReg) 2497 .addUse(BoolTypeReg) 2498 .addUse(I.getOperand(1).getReg()) 2499 .addUse(I.getOperand(2).getReg()) 2500 .constrainAllUses(TII, TRI, RBI); 2501 // Build selects. 2502 Register ResTypeReg = GR.getSPIRVTypeID(ResType); 2503 Register NegOneOrZeroReg = 2504 MRI->createVirtualRegister(GR.getRegClass(ResType)); 2505 MRI->setType(NegOneOrZeroReg, LLT::scalar(64)); 2506 GR.assignSPIRVTypeToVReg(ResType, NegOneOrZeroReg, MIRBuilder.getMF()); 2507 unsigned SelectOpcode = 2508 N > 1 ? SPIRV::OpSelectVIVCond : SPIRV::OpSelectSISCond; 2509 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode)) 2510 .addDef(NegOneOrZeroReg) 2511 .addUse(ResTypeReg) 2512 .addUse(IsLessReg) 2513 .addUse(buildOnesVal(true, ResType, I)) // -1 2514 .addUse(buildZerosVal(ResType, I)) 2515 .constrainAllUses(TII, TRI, RBI); 2516 return Result & BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode)) 2517 .addDef(ResVReg) 2518 .addUse(ResTypeReg) 2519 .addUse(IsLessEqReg) 2520 .addUse(NegOneOrZeroReg) // -1 or 0 2521 .addUse(buildOnesVal(false, ResType, I)) 2522 .constrainAllUses(TII, TRI, RBI); 2523 } 2524 2525 bool SPIRVInstructionSelector::selectIntToBool(Register IntReg, 2526 Register ResVReg, 2527 MachineInstr &I, 2528 const SPIRVType *IntTy, 2529 const SPIRVType *BoolTy) const { 2530 // To truncate to a bool, we use OpBitwiseAnd 1 and OpINotEqual to zero. 2531 Register BitIntReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass); 2532 bool IsVectorTy = IntTy->getOpcode() == SPIRV::OpTypeVector; 2533 unsigned Opcode = IsVectorTy ? SPIRV::OpBitwiseAndV : SPIRV::OpBitwiseAndS; 2534 Register Zero = buildZerosVal(IntTy, I); 2535 Register One = buildOnesVal(false, IntTy, I); 2536 MachineBasicBlock &BB = *I.getParent(); 2537 bool Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) 2538 .addDef(BitIntReg) 2539 .addUse(GR.getSPIRVTypeID(IntTy)) 2540 .addUse(IntReg) 2541 .addUse(One) 2542 .constrainAllUses(TII, TRI, RBI); 2543 return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual)) 2544 .addDef(ResVReg) 2545 .addUse(GR.getSPIRVTypeID(BoolTy)) 2546 .addUse(BitIntReg) 2547 .addUse(Zero) 2548 .constrainAllUses(TII, TRI, RBI); 2549 } 2550 2551 bool SPIRVInstructionSelector::selectTrunc(Register ResVReg, 2552 const SPIRVType *ResType, 2553 MachineInstr &I) const { 2554 Register IntReg = I.getOperand(1).getReg(); 2555 const SPIRVType *ArgType = GR.getSPIRVTypeForVReg(IntReg); 2556 if (GR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool)) 2557 return selectIntToBool(IntReg, ResVReg, I, ArgType, ResType); 2558 if (ArgType == ResType) 2559 return BuildCOPY(ResVReg, IntReg, I); 2560 bool IsSigned = GR.isScalarOrVectorSigned(ResType); 2561 unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert; 2562 return selectUnOp(ResVReg, ResType, I, Opcode); 2563 } 2564 2565 bool SPIRVInstructionSelector::selectConst(Register ResVReg, 2566 const SPIRVType *ResType, 2567 const APInt &Imm, 2568 MachineInstr &I) const { 2569 unsigned TyOpcode = ResType->getOpcode(); 2570 assert(TyOpcode != SPIRV::OpTypePointer || Imm.isZero()); 2571 MachineBasicBlock &BB = *I.getParent(); 2572 if ((TyOpcode == SPIRV::OpTypePointer || TyOpcode == SPIRV::OpTypeEvent) && 2573 Imm.isZero()) 2574 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) 2575 .addDef(ResVReg) 2576 .addUse(GR.getSPIRVTypeID(ResType)) 2577 .constrainAllUses(TII, TRI, RBI); 2578 if (TyOpcode == SPIRV::OpTypeInt) { 2579 assert(Imm.getBitWidth() <= 64 && "Unsupported integer width!"); 2580 Register Reg = GR.getOrCreateConstInt(Imm.getZExtValue(), I, ResType, TII); 2581 return Reg == ResVReg ? true : BuildCOPY(ResVReg, Reg, I); 2582 } 2583 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI)) 2584 .addDef(ResVReg) 2585 .addUse(GR.getSPIRVTypeID(ResType)); 2586 // <=32-bit integers should be caught by the sdag pattern. 2587 assert(Imm.getBitWidth() > 32); 2588 addNumImm(Imm, MIB); 2589 return MIB.constrainAllUses(TII, TRI, RBI); 2590 } 2591 2592 bool SPIRVInstructionSelector::selectOpUndef(Register ResVReg, 2593 const SPIRVType *ResType, 2594 MachineInstr &I) const { 2595 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) 2596 .addDef(ResVReg) 2597 .addUse(GR.getSPIRVTypeID(ResType)) 2598 .constrainAllUses(TII, TRI, RBI); 2599 } 2600 2601 static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI) { 2602 assert(MO.isReg()); 2603 const SPIRVType *TypeInst = MRI->getVRegDef(MO.getReg()); 2604 if (TypeInst->getOpcode() == SPIRV::ASSIGN_TYPE) { 2605 assert(TypeInst->getOperand(1).isReg()); 2606 MachineInstr *ImmInst = MRI->getVRegDef(TypeInst->getOperand(1).getReg()); 2607 return ImmInst->getOpcode() == TargetOpcode::G_CONSTANT; 2608 } 2609 return TypeInst->getOpcode() == SPIRV::OpConstantI; 2610 } 2611 2612 static int64_t foldImm(const MachineOperand &MO, MachineRegisterInfo *MRI) { 2613 const SPIRVType *TypeInst = MRI->getVRegDef(MO.getReg()); 2614 if (TypeInst->getOpcode() == SPIRV::OpConstantI) 2615 return TypeInst->getOperand(2).getImm(); 2616 MachineInstr *ImmInst = MRI->getVRegDef(TypeInst->getOperand(1).getReg()); 2617 assert(ImmInst->getOpcode() == TargetOpcode::G_CONSTANT); 2618 return ImmInst->getOperand(1).getCImm()->getZExtValue(); 2619 } 2620 2621 bool SPIRVInstructionSelector::selectInsertVal(Register ResVReg, 2622 const SPIRVType *ResType, 2623 MachineInstr &I) const { 2624 MachineBasicBlock &BB = *I.getParent(); 2625 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeInsert)) 2626 .addDef(ResVReg) 2627 .addUse(GR.getSPIRVTypeID(ResType)) 2628 // object to insert 2629 .addUse(I.getOperand(3).getReg()) 2630 // composite to insert into 2631 .addUse(I.getOperand(2).getReg()); 2632 for (unsigned i = 4; i < I.getNumOperands(); i++) 2633 MIB.addImm(foldImm(I.getOperand(i), MRI)); 2634 return MIB.constrainAllUses(TII, TRI, RBI); 2635 } 2636 2637 bool SPIRVInstructionSelector::selectExtractVal(Register ResVReg, 2638 const SPIRVType *ResType, 2639 MachineInstr &I) const { 2640 MachineBasicBlock &BB = *I.getParent(); 2641 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) 2642 .addDef(ResVReg) 2643 .addUse(GR.getSPIRVTypeID(ResType)) 2644 .addUse(I.getOperand(2).getReg()); 2645 for (unsigned i = 3; i < I.getNumOperands(); i++) 2646 MIB.addImm(foldImm(I.getOperand(i), MRI)); 2647 return MIB.constrainAllUses(TII, TRI, RBI); 2648 } 2649 2650 bool SPIRVInstructionSelector::selectInsertElt(Register ResVReg, 2651 const SPIRVType *ResType, 2652 MachineInstr &I) const { 2653 if (isImm(I.getOperand(4), MRI)) 2654 return selectInsertVal(ResVReg, ResType, I); 2655 MachineBasicBlock &BB = *I.getParent(); 2656 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorInsertDynamic)) 2657 .addDef(ResVReg) 2658 .addUse(GR.getSPIRVTypeID(ResType)) 2659 .addUse(I.getOperand(2).getReg()) 2660 .addUse(I.getOperand(3).getReg()) 2661 .addUse(I.getOperand(4).getReg()) 2662 .constrainAllUses(TII, TRI, RBI); 2663 } 2664 2665 bool SPIRVInstructionSelector::selectExtractElt(Register ResVReg, 2666 const SPIRVType *ResType, 2667 MachineInstr &I) const { 2668 if (isImm(I.getOperand(3), MRI)) 2669 return selectExtractVal(ResVReg, ResType, I); 2670 MachineBasicBlock &BB = *I.getParent(); 2671 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorExtractDynamic)) 2672 .addDef(ResVReg) 2673 .addUse(GR.getSPIRVTypeID(ResType)) 2674 .addUse(I.getOperand(2).getReg()) 2675 .addUse(I.getOperand(3).getReg()) 2676 .constrainAllUses(TII, TRI, RBI); 2677 } 2678 2679 bool SPIRVInstructionSelector::selectGEP(Register ResVReg, 2680 const SPIRVType *ResType, 2681 MachineInstr &I) const { 2682 const bool IsGEPInBounds = I.getOperand(2).getImm(); 2683 2684 // OpAccessChain could be used for OpenCL, but the SPIRV-LLVM Translator only 2685 // relies on PtrAccessChain, so we'll try not to deviate. For Vulkan however, 2686 // we have to use Op[InBounds]AccessChain. 2687 const unsigned Opcode = STI.isVulkanEnv() 2688 ? (IsGEPInBounds ? SPIRV::OpInBoundsAccessChain 2689 : SPIRV::OpAccessChain) 2690 : (IsGEPInBounds ? SPIRV::OpInBoundsPtrAccessChain 2691 : SPIRV::OpPtrAccessChain); 2692 2693 auto Res = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) 2694 .addDef(ResVReg) 2695 .addUse(GR.getSPIRVTypeID(ResType)) 2696 // Object to get a pointer to. 2697 .addUse(I.getOperand(3).getReg()); 2698 // Adding indices. 2699 const unsigned StartingIndex = 2700 (Opcode == SPIRV::OpAccessChain || Opcode == SPIRV::OpInBoundsAccessChain) 2701 ? 5 2702 : 4; 2703 for (unsigned i = StartingIndex; i < I.getNumExplicitOperands(); ++i) 2704 Res.addUse(I.getOperand(i).getReg()); 2705 return Res.constrainAllUses(TII, TRI, RBI); 2706 } 2707 2708 // Maybe wrap a value into OpSpecConstantOp 2709 bool SPIRVInstructionSelector::wrapIntoSpecConstantOp( 2710 MachineInstr &I, SmallVector<Register> &CompositeArgs) const { 2711 bool Result = true; 2712 unsigned Lim = I.getNumExplicitOperands(); 2713 for (unsigned i = I.getNumExplicitDefs() + 1; i < Lim; ++i) { 2714 Register OpReg = I.getOperand(i).getReg(); 2715 SPIRVType *OpDefine = MRI->getVRegDef(OpReg); 2716 SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpReg); 2717 SmallPtrSet<SPIRVType *, 4> Visited; 2718 if (!OpDefine || !OpType || isConstReg(MRI, OpDefine, Visited) || 2719 OpDefine->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST || 2720 GR.isAggregateType(OpType)) { 2721 // The case of G_ADDRSPACE_CAST inside spv_const_composite() is processed 2722 // by selectAddrSpaceCast() 2723 CompositeArgs.push_back(OpReg); 2724 continue; 2725 } 2726 MachineFunction *MF = I.getMF(); 2727 Register WrapReg = GR.find(OpDefine, MF); 2728 if (WrapReg.isValid()) { 2729 CompositeArgs.push_back(WrapReg); 2730 continue; 2731 } 2732 // Create a new register for the wrapper 2733 WrapReg = MRI->createVirtualRegister(GR.getRegClass(OpType)); 2734 GR.add(OpDefine, MF, WrapReg); 2735 CompositeArgs.push_back(WrapReg); 2736 // Decorate the wrapper register and generate a new instruction 2737 MRI->setType(WrapReg, LLT::pointer(0, 64)); 2738 GR.assignSPIRVTypeToVReg(OpType, WrapReg, *MF); 2739 MachineBasicBlock &BB = *I.getParent(); 2740 Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) 2741 .addDef(WrapReg) 2742 .addUse(GR.getSPIRVTypeID(OpType)) 2743 .addImm(static_cast<uint32_t>(SPIRV::Opcode::Bitcast)) 2744 .addUse(OpReg) 2745 .constrainAllUses(TII, TRI, RBI); 2746 if (!Result) 2747 break; 2748 } 2749 return Result; 2750 } 2751 2752 bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, 2753 const SPIRVType *ResType, 2754 MachineInstr &I) const { 2755 MachineBasicBlock &BB = *I.getParent(); 2756 Intrinsic::ID IID = cast<GIntrinsic>(I).getIntrinsicID(); 2757 switch (IID) { 2758 case Intrinsic::spv_load: 2759 return selectLoad(ResVReg, ResType, I); 2760 case Intrinsic::spv_store: 2761 return selectStore(I); 2762 case Intrinsic::spv_extractv: 2763 return selectExtractVal(ResVReg, ResType, I); 2764 case Intrinsic::spv_insertv: 2765 return selectInsertVal(ResVReg, ResType, I); 2766 case Intrinsic::spv_extractelt: 2767 return selectExtractElt(ResVReg, ResType, I); 2768 case Intrinsic::spv_insertelt: 2769 return selectInsertElt(ResVReg, ResType, I); 2770 case Intrinsic::spv_gep: 2771 return selectGEP(ResVReg, ResType, I); 2772 case Intrinsic::spv_unref_global: 2773 case Intrinsic::spv_init_global: { 2774 MachineInstr *MI = MRI->getVRegDef(I.getOperand(1).getReg()); 2775 MachineInstr *Init = I.getNumExplicitOperands() > 2 2776 ? MRI->getVRegDef(I.getOperand(2).getReg()) 2777 : nullptr; 2778 assert(MI); 2779 return selectGlobalValue(MI->getOperand(0).getReg(), *MI, Init); 2780 } 2781 case Intrinsic::spv_undef: { 2782 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) 2783 .addDef(ResVReg) 2784 .addUse(GR.getSPIRVTypeID(ResType)); 2785 return MIB.constrainAllUses(TII, TRI, RBI); 2786 } 2787 case Intrinsic::spv_const_composite: { 2788 // If no values are attached, the composite is null constant. 2789 bool IsNull = I.getNumExplicitDefs() + 1 == I.getNumExplicitOperands(); 2790 // Select a proper instruction. 2791 unsigned Opcode = SPIRV::OpConstantNull; 2792 SmallVector<Register> CompositeArgs; 2793 if (!IsNull) { 2794 Opcode = SPIRV::OpConstantComposite; 2795 if (!wrapIntoSpecConstantOp(I, CompositeArgs)) 2796 return false; 2797 } 2798 MRI->setRegClass(ResVReg, GR.getRegClass(ResType)); 2799 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) 2800 .addDef(ResVReg) 2801 .addUse(GR.getSPIRVTypeID(ResType)); 2802 // skip type MD node we already used when generated assign.type for this 2803 if (!IsNull) { 2804 for (Register OpReg : CompositeArgs) 2805 MIB.addUse(OpReg); 2806 } 2807 return MIB.constrainAllUses(TII, TRI, RBI); 2808 } 2809 case Intrinsic::spv_assign_name: { 2810 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpName)); 2811 MIB.addUse(I.getOperand(I.getNumExplicitDefs() + 1).getReg()); 2812 for (unsigned i = I.getNumExplicitDefs() + 2; 2813 i < I.getNumExplicitOperands(); ++i) { 2814 MIB.addImm(I.getOperand(i).getImm()); 2815 } 2816 return MIB.constrainAllUses(TII, TRI, RBI); 2817 } 2818 case Intrinsic::spv_switch: { 2819 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSwitch)); 2820 for (unsigned i = 1; i < I.getNumExplicitOperands(); ++i) { 2821 if (I.getOperand(i).isReg()) 2822 MIB.addReg(I.getOperand(i).getReg()); 2823 else if (I.getOperand(i).isCImm()) 2824 addNumImm(I.getOperand(i).getCImm()->getValue(), MIB); 2825 else if (I.getOperand(i).isMBB()) 2826 MIB.addMBB(I.getOperand(i).getMBB()); 2827 else 2828 llvm_unreachable("Unexpected OpSwitch operand"); 2829 } 2830 return MIB.constrainAllUses(TII, TRI, RBI); 2831 } 2832 case Intrinsic::spv_loop_merge: { 2833 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLoopMerge)); 2834 for (unsigned i = 1; i < I.getNumExplicitOperands(); ++i) { 2835 assert(I.getOperand(i).isMBB()); 2836 MIB.addMBB(I.getOperand(i).getMBB()); 2837 } 2838 MIB.addImm(SPIRV::SelectionControl::None); 2839 return MIB.constrainAllUses(TII, TRI, RBI); 2840 } 2841 case Intrinsic::spv_selection_merge: { 2842 auto MIB = 2843 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSelectionMerge)); 2844 assert(I.getOperand(1).isMBB() && 2845 "operand 1 to spv_selection_merge must be a basic block"); 2846 MIB.addMBB(I.getOperand(1).getMBB()); 2847 MIB.addImm(getSelectionOperandForImm(I.getOperand(2).getImm())); 2848 return MIB.constrainAllUses(TII, TRI, RBI); 2849 } 2850 case Intrinsic::spv_cmpxchg: 2851 return selectAtomicCmpXchg(ResVReg, ResType, I); 2852 case Intrinsic::spv_unreachable: 2853 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUnreachable)) 2854 .constrainAllUses(TII, TRI, RBI); 2855 case Intrinsic::spv_alloca: 2856 return selectFrameIndex(ResVReg, ResType, I); 2857 case Intrinsic::spv_alloca_array: 2858 return selectAllocaArray(ResVReg, ResType, I); 2859 case Intrinsic::spv_assume: 2860 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) 2861 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpAssumeTrueKHR)) 2862 .addUse(I.getOperand(1).getReg()) 2863 .constrainAllUses(TII, TRI, RBI); 2864 break; 2865 case Intrinsic::spv_expect: 2866 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) 2867 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExpectKHR)) 2868 .addDef(ResVReg) 2869 .addUse(GR.getSPIRVTypeID(ResType)) 2870 .addUse(I.getOperand(2).getReg()) 2871 .addUse(I.getOperand(3).getReg()) 2872 .constrainAllUses(TII, TRI, RBI); 2873 break; 2874 case Intrinsic::arithmetic_fence: 2875 if (STI.canUseExtension(SPIRV::Extension::SPV_EXT_arithmetic_fence)) 2876 return BuildMI(BB, I, I.getDebugLoc(), 2877 TII.get(SPIRV::OpArithmeticFenceEXT)) 2878 .addDef(ResVReg) 2879 .addUse(GR.getSPIRVTypeID(ResType)) 2880 .addUse(I.getOperand(2).getReg()) 2881 .constrainAllUses(TII, TRI, RBI); 2882 else 2883 return BuildCOPY(ResVReg, I.getOperand(2).getReg(), I); 2884 break; 2885 case Intrinsic::spv_thread_id: 2886 // The HLSL SV_DispatchThreadID semantic is lowered to llvm.spv.thread.id 2887 // intrinsic in LLVM IR for SPIR-V backend. 2888 // 2889 // In SPIR-V backend, llvm.spv.thread.id is now correctly translated to a 2890 // `GlobalInvocationId` builtin variable 2891 return loadVec3BuiltinInputID(SPIRV::BuiltIn::GlobalInvocationId, ResVReg, 2892 ResType, I); 2893 case Intrinsic::spv_thread_id_in_group: 2894 // The HLSL SV_GroupThreadId semantic is lowered to 2895 // llvm.spv.thread.id.in.group intrinsic in LLVM IR for SPIR-V backend. 2896 // 2897 // In SPIR-V backend, llvm.spv.thread.id.in.group is now correctly 2898 // translated to a `LocalInvocationId` builtin variable 2899 return loadVec3BuiltinInputID(SPIRV::BuiltIn::LocalInvocationId, ResVReg, 2900 ResType, I); 2901 case Intrinsic::spv_group_id: 2902 // The HLSL SV_GroupId semantic is lowered to 2903 // llvm.spv.group.id intrinsic in LLVM IR for SPIR-V backend. 2904 // 2905 // In SPIR-V backend, llvm.spv.group.id is now translated to a `WorkgroupId` 2906 // builtin variable 2907 return loadVec3BuiltinInputID(SPIRV::BuiltIn::WorkgroupId, ResVReg, ResType, 2908 I); 2909 case Intrinsic::spv_fdot: 2910 return selectFloatDot(ResVReg, ResType, I); 2911 case Intrinsic::spv_udot: 2912 case Intrinsic::spv_sdot: 2913 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_integer_dot_product) || 2914 STI.isAtLeastSPIRVVer(VersionTuple(1, 6))) 2915 return selectIntegerDot(ResVReg, ResType, I, 2916 /*Signed=*/IID == Intrinsic::spv_sdot); 2917 return selectIntegerDotExpansion(ResVReg, ResType, I); 2918 case Intrinsic::spv_dot4add_i8packed: 2919 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_integer_dot_product) || 2920 STI.isAtLeastSPIRVVer(VersionTuple(1, 6))) 2921 return selectDot4AddPacked<true>(ResVReg, ResType, I); 2922 return selectDot4AddPackedExpansion<true>(ResVReg, ResType, I); 2923 case Intrinsic::spv_dot4add_u8packed: 2924 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_integer_dot_product) || 2925 STI.isAtLeastSPIRVVer(VersionTuple(1, 6))) 2926 return selectDot4AddPacked<false>(ResVReg, ResType, I); 2927 return selectDot4AddPackedExpansion<false>(ResVReg, ResType, I); 2928 case Intrinsic::spv_all: 2929 return selectAll(ResVReg, ResType, I); 2930 case Intrinsic::spv_any: 2931 return selectAny(ResVReg, ResType, I); 2932 case Intrinsic::spv_cross: 2933 return selectExtInst(ResVReg, ResType, I, CL::cross, GL::Cross); 2934 case Intrinsic::spv_distance: 2935 return selectExtInst(ResVReg, ResType, I, CL::distance, GL::Distance); 2936 case Intrinsic::spv_lerp: 2937 return selectExtInst(ResVReg, ResType, I, CL::mix, GL::FMix); 2938 case Intrinsic::spv_length: 2939 return selectExtInst(ResVReg, ResType, I, CL::length, GL::Length); 2940 case Intrinsic::spv_degrees: 2941 return selectExtInst(ResVReg, ResType, I, CL::degrees, GL::Degrees); 2942 case Intrinsic::spv_frac: 2943 return selectExtInst(ResVReg, ResType, I, CL::fract, GL::Fract); 2944 case Intrinsic::spv_normalize: 2945 return selectExtInst(ResVReg, ResType, I, CL::normalize, GL::Normalize); 2946 case Intrinsic::spv_rsqrt: 2947 return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt); 2948 case Intrinsic::spv_sign: 2949 return selectSign(ResVReg, ResType, I); 2950 case Intrinsic::spv_firstbituhigh: // There is no CL equivalent of FindUMsb 2951 return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/false); 2952 case Intrinsic::spv_firstbitshigh: // There is no CL equivalent of FindSMsb 2953 return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/true); 2954 case Intrinsic::spv_group_memory_barrier_with_group_sync: { 2955 bool Result = true; 2956 auto MemSemConstant = 2957 buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I); 2958 Register MemSemReg = MemSemConstant.first; 2959 Result &= MemSemConstant.second; 2960 auto ScopeConstant = buildI32Constant(SPIRV::Scope::Workgroup, I); 2961 Register ScopeReg = ScopeConstant.first; 2962 Result &= ScopeConstant.second; 2963 MachineBasicBlock &BB = *I.getParent(); 2964 return Result && 2965 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpControlBarrier)) 2966 .addUse(ScopeReg) 2967 .addUse(ScopeReg) 2968 .addUse(MemSemReg) 2969 .constrainAllUses(TII, TRI, RBI); 2970 } 2971 case Intrinsic::spv_lifetime_start: 2972 case Intrinsic::spv_lifetime_end: { 2973 unsigned Op = IID == Intrinsic::spv_lifetime_start ? SPIRV::OpLifetimeStart 2974 : SPIRV::OpLifetimeStop; 2975 int64_t Size = I.getOperand(I.getNumExplicitDefs() + 1).getImm(); 2976 Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 2).getReg(); 2977 if (Size == -1) 2978 Size = 0; 2979 return BuildMI(BB, I, I.getDebugLoc(), TII.get(Op)) 2980 .addUse(PtrReg) 2981 .addImm(Size) 2982 .constrainAllUses(TII, TRI, RBI); 2983 } 2984 case Intrinsic::spv_saturate: 2985 return selectSaturate(ResVReg, ResType, I); 2986 case Intrinsic::spv_nclamp: 2987 return selectExtInst(ResVReg, ResType, I, CL::fclamp, GL::NClamp); 2988 case Intrinsic::spv_uclamp: 2989 return selectExtInst(ResVReg, ResType, I, CL::u_clamp, GL::UClamp); 2990 case Intrinsic::spv_sclamp: 2991 return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp); 2992 case Intrinsic::spv_wave_active_countbits: 2993 return selectWaveActiveCountBits(ResVReg, ResType, I); 2994 case Intrinsic::spv_wave_all: 2995 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAll); 2996 case Intrinsic::spv_wave_any: 2997 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny); 2998 case Intrinsic::spv_wave_is_first_lane: 2999 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect); 3000 case Intrinsic::spv_wave_readlane: 3001 return selectWaveOpInst(ResVReg, ResType, I, 3002 SPIRV::OpGroupNonUniformShuffle); 3003 case Intrinsic::spv_step: 3004 return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step); 3005 case Intrinsic::spv_radians: 3006 return selectExtInst(ResVReg, ResType, I, CL::radians, GL::Radians); 3007 // Discard intrinsics which we do not expect to actually represent code after 3008 // lowering or intrinsics which are not implemented but should not crash when 3009 // found in a customer's LLVM IR input. 3010 case Intrinsic::instrprof_increment: 3011 case Intrinsic::instrprof_increment_step: 3012 case Intrinsic::instrprof_value_profile: 3013 break; 3014 // Discard internal intrinsics. 3015 case Intrinsic::spv_value_md: 3016 break; 3017 case Intrinsic::spv_resource_handlefrombinding: { 3018 return selectHandleFromBinding(ResVReg, ResType, I); 3019 } 3020 case Intrinsic::spv_resource_store_typedbuffer: { 3021 selectImageWriteIntrinsic(I); 3022 return true; 3023 } 3024 case Intrinsic::spv_resource_load_typedbuffer: { 3025 selectReadImageIntrinsic(ResVReg, ResType, I); 3026 return true; 3027 } 3028 case Intrinsic::spv_discard: { 3029 return selectDiscard(ResVReg, ResType, I); 3030 } 3031 default: { 3032 std::string DiagMsg; 3033 raw_string_ostream OS(DiagMsg); 3034 I.print(OS); 3035 DiagMsg = "Intrinsic selection not implemented: " + DiagMsg; 3036 report_fatal_error(DiagMsg.c_str(), false); 3037 } 3038 } 3039 return true; 3040 } 3041 3042 bool SPIRVInstructionSelector::selectHandleFromBinding(Register &ResVReg, 3043 const SPIRVType *ResType, 3044 MachineInstr &I) const { 3045 3046 uint32_t Set = foldImm(I.getOperand(2), MRI); 3047 uint32_t Binding = foldImm(I.getOperand(3), MRI); 3048 uint32_t ArraySize = foldImm(I.getOperand(4), MRI); 3049 Register IndexReg = I.getOperand(5).getReg(); 3050 bool IsNonUniform = ArraySize > 1 && foldImm(I.getOperand(6), MRI); 3051 3052 MachineIRBuilder MIRBuilder(I); 3053 Register VarReg = buildPointerToResource(ResType, Set, Binding, ArraySize, 3054 IndexReg, IsNonUniform, MIRBuilder); 3055 3056 if (IsNonUniform) 3057 buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::NonUniformEXT, {}); 3058 3059 // TODO: For now we assume the resource is an image, which needs to be 3060 // loaded to get the handle. That will not be true for storage buffers. 3061 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) 3062 .addDef(ResVReg) 3063 .addUse(GR.getSPIRVTypeID(ResType)) 3064 .addUse(VarReg) 3065 .constrainAllUses(TII, TRI, RBI); 3066 } 3067 3068 void SPIRVInstructionSelector::selectReadImageIntrinsic( 3069 Register &ResVReg, const SPIRVType *ResType, MachineInstr &I) const { 3070 3071 // If the load of the image is in a different basic block, then 3072 // this will generate invalid code. A proper solution is to move 3073 // the OpLoad from selectHandleFromBinding here. However, to do 3074 // that we will need to change the return type of the intrinsic. 3075 // We will do that when we can, but for now trying to move forward with other 3076 // issues. 3077 Register ImageReg = I.getOperand(2).getReg(); 3078 assert(MRI->getVRegDef(ImageReg)->getParent() == I.getParent() && 3079 "The image must be loaded in the same basic block as its use."); 3080 3081 uint64_t ResultSize = GR.getScalarOrVectorComponentCount(ResType); 3082 if (ResultSize == 4) { 3083 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpImageRead)) 3084 .addDef(ResVReg) 3085 .addUse(GR.getSPIRVTypeID(ResType)) 3086 .addUse(ImageReg) 3087 .addUse(I.getOperand(3).getReg()); 3088 return; 3089 } 3090 3091 SPIRVType *ReadType = widenTypeToVec4(ResType, I); 3092 Register ReadReg = MRI->createVirtualRegister(GR.getRegClass(ReadType)); 3093 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpImageRead)) 3094 .addDef(ReadReg) 3095 .addUse(GR.getSPIRVTypeID(ReadType)) 3096 .addUse(ImageReg) 3097 .addUse(I.getOperand(3).getReg()); 3098 3099 if (ResultSize == 1) { 3100 BuildMI(*I.getParent(), I, I.getDebugLoc(), 3101 TII.get(SPIRV::OpCompositeExtract)) 3102 .addDef(ResVReg) 3103 .addUse(GR.getSPIRVTypeID(ResType)) 3104 .addUse(ReadReg) 3105 .addImm(0); 3106 return; 3107 } 3108 extractSubvector(ResVReg, ResType, ReadReg, I); 3109 } 3110 3111 void SPIRVInstructionSelector::extractSubvector( 3112 Register &ResVReg, const SPIRVType *ResType, Register &ReadReg, 3113 MachineInstr &InsertionPoint) const { 3114 SPIRVType *InputType = GR.getResultType(ReadReg); 3115 [[maybe_unused]] uint64_t InputSize = 3116 GR.getScalarOrVectorComponentCount(InputType); 3117 uint64_t ResultSize = GR.getScalarOrVectorComponentCount(ResType); 3118 assert(InputSize > 1 && "The input must be a vector."); 3119 assert(ResultSize > 1 && "The result must be a vector."); 3120 assert(ResultSize < InputSize && 3121 "Cannot extract more element than there are in the input."); 3122 SmallVector<Register> ComponentRegisters; 3123 SPIRVType *ScalarType = GR.getScalarOrVectorComponentType(ResType); 3124 const TargetRegisterClass *ScalarRegClass = GR.getRegClass(ScalarType); 3125 for (uint64_t I = 0; I < ResultSize; I++) { 3126 Register ComponentReg = MRI->createVirtualRegister(ScalarRegClass); 3127 BuildMI(*InsertionPoint.getParent(), InsertionPoint, 3128 InsertionPoint.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) 3129 .addDef(ComponentReg) 3130 .addUse(ScalarType->getOperand(0).getReg()) 3131 .addUse(ReadReg) 3132 .addImm(I); 3133 ComponentRegisters.emplace_back(ComponentReg); 3134 } 3135 3136 MachineInstrBuilder MIB = BuildMI(*InsertionPoint.getParent(), InsertionPoint, 3137 InsertionPoint.getDebugLoc(), 3138 TII.get(SPIRV::OpCompositeConstruct)) 3139 .addDef(ResVReg) 3140 .addUse(GR.getSPIRVTypeID(ResType)); 3141 3142 for (Register ComponentReg : ComponentRegisters) 3143 MIB.addUse(ComponentReg); 3144 } 3145 3146 void SPIRVInstructionSelector::selectImageWriteIntrinsic( 3147 MachineInstr &I) const { 3148 // If the load of the image is in a different basic block, then 3149 // this will generate invalid code. A proper solution is to move 3150 // the OpLoad from selectHandleFromBinding here. However, to do 3151 // that we will need to change the return type of the intrinsic. 3152 // We will do that when we can, but for now trying to move forward with other 3153 // issues. 3154 Register ImageReg = I.getOperand(1).getReg(); 3155 assert(MRI->getVRegDef(ImageReg)->getParent() == I.getParent() && 3156 "The image must be loaded in the same basic block as its use."); 3157 Register CoordinateReg = I.getOperand(2).getReg(); 3158 Register DataReg = I.getOperand(3).getReg(); 3159 assert(GR.getResultType(DataReg)->getOpcode() == SPIRV::OpTypeVector); 3160 assert(GR.getScalarOrVectorComponentCount(GR.getResultType(DataReg)) == 4); 3161 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpImageWrite)) 3162 .addUse(ImageReg) 3163 .addUse(CoordinateReg) 3164 .addUse(DataReg); 3165 } 3166 3167 Register SPIRVInstructionSelector::buildPointerToResource( 3168 const SPIRVType *ResType, uint32_t Set, uint32_t Binding, 3169 uint32_t ArraySize, Register IndexReg, bool IsNonUniform, 3170 MachineIRBuilder MIRBuilder) const { 3171 if (ArraySize == 1) 3172 return GR.getOrCreateGlobalVariableWithBinding(ResType, Set, Binding, 3173 MIRBuilder); 3174 3175 const SPIRVType *VarType = GR.getOrCreateSPIRVArrayType( 3176 ResType, ArraySize, *MIRBuilder.getInsertPt(), TII); 3177 Register VarReg = GR.getOrCreateGlobalVariableWithBinding( 3178 VarType, Set, Binding, MIRBuilder); 3179 3180 SPIRVType *ResPointerType = GR.getOrCreateSPIRVPointerType( 3181 ResType, MIRBuilder, SPIRV::StorageClass::UniformConstant); 3182 3183 Register AcReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass); 3184 if (IsNonUniform) { 3185 // It is unclear which value needs to be marked an non-uniform, so both 3186 // the index and the access changed are decorated as non-uniform. 3187 buildOpDecorate(IndexReg, MIRBuilder, SPIRV::Decoration::NonUniformEXT, {}); 3188 buildOpDecorate(AcReg, MIRBuilder, SPIRV::Decoration::NonUniformEXT, {}); 3189 } 3190 3191 MIRBuilder.buildInstr(SPIRV::OpAccessChain) 3192 .addDef(AcReg) 3193 .addUse(GR.getSPIRVTypeID(ResPointerType)) 3194 .addUse(VarReg) 3195 .addUse(IndexReg); 3196 3197 return AcReg; 3198 } 3199 3200 bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg, 3201 const SPIRVType *ResType, 3202 MachineInstr &I, 3203 bool IsSigned) const { 3204 unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert; 3205 // zero or sign extend 3206 Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); 3207 bool Result = 3208 selectOpWithSrcs(ExtReg, ResType, I, {I.getOperand(2).getReg()}, Opcode); 3209 return Result && selectFirstBitHigh32(ResVReg, ResType, I, ExtReg, IsSigned); 3210 } 3211 3212 bool SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg, 3213 const SPIRVType *ResType, 3214 MachineInstr &I, 3215 Register SrcReg, 3216 bool IsSigned) const { 3217 unsigned Opcode = IsSigned ? GL::FindSMsb : GL::FindUMsb; 3218 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) 3219 .addDef(ResVReg) 3220 .addUse(GR.getSPIRVTypeID(ResType)) 3221 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) 3222 .addImm(Opcode) 3223 .addUse(SrcReg) 3224 .constrainAllUses(TII, TRI, RBI); 3225 } 3226 3227 bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg, 3228 const SPIRVType *ResType, 3229 MachineInstr &I, 3230 bool IsSigned) const { 3231 Register OpReg = I.getOperand(2).getReg(); 3232 // 1. split our int64 into 2 pieces using a bitcast 3233 unsigned count = GR.getScalarOrVectorComponentCount(ResType); 3234 SPIRVType *baseType = GR.retrieveScalarOrVectorIntType(ResType); 3235 MachineIRBuilder MIRBuilder(I); 3236 SPIRVType *postCastT = 3237 GR.getOrCreateSPIRVVectorType(baseType, 2 * count, MIRBuilder); 3238 Register bitcastReg = MRI->createVirtualRegister(GR.getRegClass(postCastT)); 3239 bool Result = 3240 selectOpWithSrcs(bitcastReg, postCastT, I, {OpReg}, SPIRV::OpBitcast); 3241 3242 // 2. call firstbithigh 3243 Register FBHReg = MRI->createVirtualRegister(GR.getRegClass(postCastT)); 3244 Result &= selectFirstBitHigh32(FBHReg, postCastT, I, bitcastReg, IsSigned); 3245 3246 // 3. split result vector into high bits and low bits 3247 Register HighReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); 3248 Register LowReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); 3249 3250 bool ZeroAsNull = STI.isOpenCLEnv(); 3251 bool isScalarRes = ResType->getOpcode() != SPIRV::OpTypeVector; 3252 if (isScalarRes) { 3253 // if scalar do a vector extract 3254 Result &= selectOpWithSrcs( 3255 HighReg, ResType, I, 3256 {FBHReg, GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull)}, 3257 SPIRV::OpVectorExtractDynamic); 3258 Result &= selectOpWithSrcs( 3259 LowReg, ResType, I, 3260 {FBHReg, GR.getOrCreateConstInt(1, I, ResType, TII, ZeroAsNull)}, 3261 SPIRV::OpVectorExtractDynamic); 3262 } else { // vector case do a shufflevector 3263 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), 3264 TII.get(SPIRV::OpVectorShuffle)) 3265 .addDef(HighReg) 3266 .addUse(GR.getSPIRVTypeID(ResType)) 3267 .addUse(FBHReg) 3268 .addUse(FBHReg); 3269 // ^^ this vector will not be selected from; could be empty 3270 unsigned j; 3271 for (j = 0; j < count * 2; j += 2) { 3272 MIB.addImm(j); 3273 } 3274 Result &= MIB.constrainAllUses(TII, TRI, RBI); 3275 3276 // get low bits 3277 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), 3278 TII.get(SPIRV::OpVectorShuffle)) 3279 .addDef(LowReg) 3280 .addUse(GR.getSPIRVTypeID(ResType)) 3281 .addUse(FBHReg) 3282 .addUse(FBHReg); 3283 // ^^ this vector will not be selected from; could be empty 3284 for (j = 1; j < count * 2; j += 2) { 3285 MIB.addImm(j); 3286 } 3287 Result &= MIB.constrainAllUses(TII, TRI, RBI); 3288 } 3289 3290 // 4. check if result of each top 32 bits is == -1 3291 SPIRVType *BoolType = GR.getOrCreateSPIRVBoolType(I, TII); 3292 Register NegOneReg; 3293 Register Reg0; 3294 Register Reg32; 3295 unsigned selectOp; 3296 unsigned addOp; 3297 if (isScalarRes) { 3298 NegOneReg = 3299 GR.getOrCreateConstInt((unsigned)-1, I, ResType, TII, ZeroAsNull); 3300 Reg0 = GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull); 3301 Reg32 = GR.getOrCreateConstInt(32, I, ResType, TII, ZeroAsNull); 3302 selectOp = SPIRV::OpSelectSISCond; 3303 addOp = SPIRV::OpIAddS; 3304 } else { 3305 BoolType = GR.getOrCreateSPIRVVectorType(BoolType, count, MIRBuilder); 3306 NegOneReg = 3307 GR.getOrCreateConstVector((unsigned)-1, I, ResType, TII, ZeroAsNull); 3308 Reg0 = GR.getOrCreateConstVector(0, I, ResType, TII, ZeroAsNull); 3309 Reg32 = GR.getOrCreateConstVector(32, I, ResType, TII, ZeroAsNull); 3310 selectOp = SPIRV::OpSelectVIVCond; 3311 addOp = SPIRV::OpIAddV; 3312 } 3313 3314 // check if the high bits are == -1; true if -1 3315 Register BReg = MRI->createVirtualRegister(GR.getRegClass(BoolType)); 3316 Result &= selectOpWithSrcs(BReg, BoolType, I, {HighReg, NegOneReg}, 3317 SPIRV::OpIEqual); 3318 3319 // Select low bits if true in BReg, otherwise high bits 3320 Register TmpReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); 3321 Result &= 3322 selectOpWithSrcs(TmpReg, ResType, I, {BReg, LowReg, HighReg}, selectOp); 3323 3324 // Add 32 for high bits, 0 for low bits 3325 Register ValReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); 3326 Result &= selectOpWithSrcs(ValReg, ResType, I, {BReg, Reg0, Reg32}, selectOp); 3327 3328 return Result && 3329 selectOpWithSrcs(ResVReg, ResType, I, {ValReg, TmpReg}, addOp); 3330 } 3331 3332 bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg, 3333 const SPIRVType *ResType, 3334 MachineInstr &I, 3335 bool IsSigned) const { 3336 // FindUMsb and FindSMsb intrinsics only support 32 bit integers 3337 Register OpReg = I.getOperand(2).getReg(); 3338 SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpReg); 3339 3340 switch (GR.getScalarOrVectorBitWidth(OpType)) { 3341 case 16: 3342 return selectFirstBitHigh16(ResVReg, ResType, I, IsSigned); 3343 case 32: 3344 return selectFirstBitHigh32(ResVReg, ResType, I, OpReg, IsSigned); 3345 case 64: 3346 return selectFirstBitHigh64(ResVReg, ResType, I, IsSigned); 3347 default: 3348 report_fatal_error( 3349 "spv_firstbituhigh and spv_firstbitshigh only support 16,32,64 bits."); 3350 } 3351 } 3352 3353 bool SPIRVInstructionSelector::selectAllocaArray(Register ResVReg, 3354 const SPIRVType *ResType, 3355 MachineInstr &I) const { 3356 // there was an allocation size parameter to the allocation instruction 3357 // that is not 1 3358 MachineBasicBlock &BB = *I.getParent(); 3359 bool Res = BuildMI(BB, I, I.getDebugLoc(), 3360 TII.get(SPIRV::OpVariableLengthArrayINTEL)) 3361 .addDef(ResVReg) 3362 .addUse(GR.getSPIRVTypeID(ResType)) 3363 .addUse(I.getOperand(2).getReg()) 3364 .constrainAllUses(TII, TRI, RBI); 3365 if (!STI.isVulkanEnv()) { 3366 unsigned Alignment = I.getOperand(3).getImm(); 3367 buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::Alignment, {Alignment}); 3368 } 3369 return Res; 3370 } 3371 3372 bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg, 3373 const SPIRVType *ResType, 3374 MachineInstr &I) const { 3375 // Change order of instructions if needed: all OpVariable instructions in a 3376 // function must be the first instructions in the first block 3377 auto It = getOpVariableMBBIt(I); 3378 bool Res = BuildMI(*It->getParent(), It, It->getDebugLoc(), 3379 TII.get(SPIRV::OpVariable)) 3380 .addDef(ResVReg) 3381 .addUse(GR.getSPIRVTypeID(ResType)) 3382 .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function)) 3383 .constrainAllUses(TII, TRI, RBI); 3384 if (!STI.isVulkanEnv()) { 3385 unsigned Alignment = I.getOperand(2).getImm(); 3386 buildOpDecorate(ResVReg, *It, TII, SPIRV::Decoration::Alignment, 3387 {Alignment}); 3388 } 3389 return Res; 3390 } 3391 3392 bool SPIRVInstructionSelector::selectBranch(MachineInstr &I) const { 3393 // InstructionSelector walks backwards through the instructions. We can use 3394 // both a G_BR and a G_BRCOND to create an OpBranchConditional. We hit G_BR 3395 // first, so can generate an OpBranchConditional here. If there is no 3396 // G_BRCOND, we just use OpBranch for a regular unconditional branch. 3397 const MachineInstr *PrevI = I.getPrevNode(); 3398 MachineBasicBlock &MBB = *I.getParent(); 3399 if (PrevI != nullptr && PrevI->getOpcode() == TargetOpcode::G_BRCOND) { 3400 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional)) 3401 .addUse(PrevI->getOperand(0).getReg()) 3402 .addMBB(PrevI->getOperand(1).getMBB()) 3403 .addMBB(I.getOperand(0).getMBB()) 3404 .constrainAllUses(TII, TRI, RBI); 3405 } 3406 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranch)) 3407 .addMBB(I.getOperand(0).getMBB()) 3408 .constrainAllUses(TII, TRI, RBI); 3409 } 3410 3411 bool SPIRVInstructionSelector::selectBranchCond(MachineInstr &I) const { 3412 // InstructionSelector walks backwards through the instructions. For an 3413 // explicit conditional branch with no fallthrough, we use both a G_BR and a 3414 // G_BRCOND to create an OpBranchConditional. We should hit G_BR first, and 3415 // generate the OpBranchConditional in selectBranch above. 3416 // 3417 // If an OpBranchConditional has been generated, we simply return, as the work 3418 // is alread done. If there is no OpBranchConditional, LLVM must be relying on 3419 // implicit fallthrough to the next basic block, so we need to create an 3420 // OpBranchConditional with an explicit "false" argument pointing to the next 3421 // basic block that LLVM would fall through to. 3422 const MachineInstr *NextI = I.getNextNode(); 3423 // Check if this has already been successfully selected. 3424 if (NextI != nullptr && NextI->getOpcode() == SPIRV::OpBranchConditional) 3425 return true; 3426 // Must be relying on implicit block fallthrough, so generate an 3427 // OpBranchConditional with the "next" basic block as the "false" target. 3428 MachineBasicBlock &MBB = *I.getParent(); 3429 unsigned NextMBBNum = MBB.getNextNode()->getNumber(); 3430 MachineBasicBlock *NextMBB = I.getMF()->getBlockNumbered(NextMBBNum); 3431 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional)) 3432 .addUse(I.getOperand(0).getReg()) 3433 .addMBB(I.getOperand(1).getMBB()) 3434 .addMBB(NextMBB) 3435 .constrainAllUses(TII, TRI, RBI); 3436 } 3437 3438 bool SPIRVInstructionSelector::selectPhi(Register ResVReg, 3439 const SPIRVType *ResType, 3440 MachineInstr &I) const { 3441 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpPhi)) 3442 .addDef(ResVReg) 3443 .addUse(GR.getSPIRVTypeID(ResType)); 3444 const unsigned NumOps = I.getNumOperands(); 3445 for (unsigned i = 1; i < NumOps; i += 2) { 3446 MIB.addUse(I.getOperand(i + 0).getReg()); 3447 MIB.addMBB(I.getOperand(i + 1).getMBB()); 3448 } 3449 bool Res = MIB.constrainAllUses(TII, TRI, RBI); 3450 MIB->setDesc(TII.get(TargetOpcode::PHI)); 3451 MIB->removeOperand(1); 3452 return Res; 3453 } 3454 3455 bool SPIRVInstructionSelector::selectGlobalValue( 3456 Register ResVReg, MachineInstr &I, const MachineInstr *Init) const { 3457 // FIXME: don't use MachineIRBuilder here, replace it with BuildMI. 3458 MachineIRBuilder MIRBuilder(I); 3459 const GlobalValue *GV = I.getOperand(1).getGlobal(); 3460 Type *GVType = toTypedPointer(GR.getDeducedGlobalValueType(GV)); 3461 SPIRVType *PointerBaseType; 3462 if (GVType->isArrayTy()) { 3463 SPIRVType *ArrayElementType = 3464 GR.getOrCreateSPIRVType(GVType->getArrayElementType(), MIRBuilder, 3465 SPIRV::AccessQualifier::ReadWrite, false); 3466 PointerBaseType = GR.getOrCreateSPIRVArrayType( 3467 ArrayElementType, GVType->getArrayNumElements(), I, TII); 3468 } else { 3469 PointerBaseType = GR.getOrCreateSPIRVType( 3470 GVType, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false); 3471 } 3472 3473 std::string GlobalIdent; 3474 if (!GV->hasName()) { 3475 unsigned &ID = UnnamedGlobalIDs[GV]; 3476 if (ID == 0) 3477 ID = UnnamedGlobalIDs.size(); 3478 GlobalIdent = "__unnamed_" + Twine(ID).str(); 3479 } else { 3480 GlobalIdent = GV->getGlobalIdentifier(); 3481 } 3482 3483 // Behaviour of functions as operands depends on availability of the 3484 // corresponding extension (SPV_INTEL_function_pointers): 3485 // - If there is an extension to operate with functions as operands: 3486 // We create a proper constant operand and evaluate a correct type for a 3487 // function pointer. 3488 // - Without the required extension: 3489 // We have functions as operands in tests with blocks of instruction e.g. in 3490 // transcoding/global_block.ll. These operands are not used and should be 3491 // substituted by zero constants. Their type is expected to be always 3492 // OpTypePointer Function %uchar. 3493 if (isa<Function>(GV)) { 3494 const Constant *ConstVal = GV; 3495 MachineBasicBlock &BB = *I.getParent(); 3496 Register NewReg = GR.find(ConstVal, GR.CurMF); 3497 if (!NewReg.isValid()) { 3498 Register NewReg = ResVReg; 3499 GR.add(ConstVal, GR.CurMF, NewReg); 3500 const Function *GVFun = 3501 STI.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers) 3502 ? dyn_cast<Function>(GV) 3503 : nullptr; 3504 SPIRVType *ResType = GR.getOrCreateSPIRVPointerType( 3505 PointerBaseType, I, TII, 3506 GVFun ? SPIRV::StorageClass::CodeSectionINTEL 3507 : addressSpaceToStorageClass(GV->getAddressSpace(), STI)); 3508 if (GVFun) { 3509 // References to a function via function pointers generate virtual 3510 // registers without a definition. We will resolve it later, during 3511 // module analysis stage. 3512 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); 3513 Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(64)); 3514 MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass); 3515 MachineInstrBuilder MB = 3516 BuildMI(BB, I, I.getDebugLoc(), 3517 TII.get(SPIRV::OpConstantFunctionPointerINTEL)) 3518 .addDef(NewReg) 3519 .addUse(GR.getSPIRVTypeID(ResType)) 3520 .addUse(FuncVReg); 3521 // mapping the function pointer to the used Function 3522 GR.recordFunctionPointer(&MB.getInstr()->getOperand(2), GVFun); 3523 return MB.constrainAllUses(TII, TRI, RBI); 3524 } 3525 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) 3526 .addDef(NewReg) 3527 .addUse(GR.getSPIRVTypeID(ResType)) 3528 .constrainAllUses(TII, TRI, RBI); 3529 } 3530 assert(NewReg != ResVReg); 3531 return BuildCOPY(ResVReg, NewReg, I); 3532 } 3533 auto GlobalVar = cast<GlobalVariable>(GV); 3534 assert(GlobalVar->getName() != "llvm.global.annotations"); 3535 3536 bool HasInit = GlobalVar->hasInitializer() && 3537 !isa<UndefValue>(GlobalVar->getInitializer()); 3538 // Skip empty declaration for GVs with initilaizers till we get the decl with 3539 // passed initializer. 3540 if (HasInit && !Init) 3541 return true; 3542 3543 bool HasLnkTy = GV->getLinkage() != GlobalValue::InternalLinkage; 3544 SPIRV::LinkageType::LinkageType LnkType = 3545 (GV->isDeclaration() || GV->hasAvailableExternallyLinkage()) 3546 ? SPIRV::LinkageType::Import 3547 : (GV->getLinkage() == GlobalValue::LinkOnceODRLinkage && 3548 STI.canUseExtension(SPIRV::Extension::SPV_KHR_linkonce_odr) 3549 ? SPIRV::LinkageType::LinkOnceODR 3550 : SPIRV::LinkageType::Export); 3551 3552 const unsigned AddrSpace = GV->getAddressSpace(); 3553 SPIRV::StorageClass::StorageClass StorageClass = 3554 addressSpaceToStorageClass(AddrSpace, STI); 3555 SPIRVType *ResType = 3556 GR.getOrCreateSPIRVPointerType(PointerBaseType, I, TII, StorageClass); 3557 Register Reg = GR.buildGlobalVariable( 3558 ResVReg, ResType, GlobalIdent, GV, StorageClass, Init, 3559 GlobalVar->isConstant(), HasLnkTy, LnkType, MIRBuilder, true); 3560 return Reg.isValid(); 3561 } 3562 3563 bool SPIRVInstructionSelector::selectLog10(Register ResVReg, 3564 const SPIRVType *ResType, 3565 MachineInstr &I) const { 3566 if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) { 3567 return selectExtInst(ResVReg, ResType, I, CL::log10); 3568 } 3569 3570 // There is no log10 instruction in the GLSL Extended Instruction set, so it 3571 // is implemented as: 3572 // log10(x) = log2(x) * (1 / log2(10)) 3573 // = log2(x) * 0.30103 3574 3575 MachineIRBuilder MIRBuilder(I); 3576 MachineBasicBlock &BB = *I.getParent(); 3577 3578 // Build log2(x). 3579 Register VarReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); 3580 bool Result = 3581 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) 3582 .addDef(VarReg) 3583 .addUse(GR.getSPIRVTypeID(ResType)) 3584 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) 3585 .addImm(GL::Log2) 3586 .add(I.getOperand(1)) 3587 .constrainAllUses(TII, TRI, RBI); 3588 3589 // Build 0.30103. 3590 assert(ResType->getOpcode() == SPIRV::OpTypeVector || 3591 ResType->getOpcode() == SPIRV::OpTypeFloat); 3592 // TODO: Add matrix implementation once supported by the HLSL frontend. 3593 const SPIRVType *SpirvScalarType = 3594 ResType->getOpcode() == SPIRV::OpTypeVector 3595 ? GR.getSPIRVTypeForVReg(ResType->getOperand(1).getReg()) 3596 : ResType; 3597 Register ScaleReg = 3598 GR.buildConstantFP(APFloat(0.30103f), MIRBuilder, SpirvScalarType); 3599 3600 // Multiply log2(x) by 0.30103 to get log10(x) result. 3601 auto Opcode = ResType->getOpcode() == SPIRV::OpTypeVector 3602 ? SPIRV::OpVectorTimesScalar 3603 : SPIRV::OpFMulS; 3604 return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) 3605 .addDef(ResVReg) 3606 .addUse(GR.getSPIRVTypeID(ResType)) 3607 .addUse(VarReg) 3608 .addUse(ScaleReg) 3609 .constrainAllUses(TII, TRI, RBI); 3610 } 3611 3612 // Generate the instructions to load 3-element vector builtin input 3613 // IDs/Indices. 3614 // Like: GlobalInvocationId, LocalInvocationId, etc.... 3615 bool SPIRVInstructionSelector::loadVec3BuiltinInputID( 3616 SPIRV::BuiltIn::BuiltIn BuiltInValue, Register ResVReg, 3617 const SPIRVType *ResType, MachineInstr &I) const { 3618 MachineIRBuilder MIRBuilder(I); 3619 const SPIRVType *U32Type = GR.getOrCreateSPIRVIntegerType(32, MIRBuilder); 3620 const SPIRVType *Vec3Ty = 3621 GR.getOrCreateSPIRVVectorType(U32Type, 3, MIRBuilder); 3622 const SPIRVType *PtrType = GR.getOrCreateSPIRVPointerType( 3623 Vec3Ty, MIRBuilder, SPIRV::StorageClass::Input); 3624 3625 // Create new register for the input ID builtin variable. 3626 Register NewRegister = 3627 MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass); 3628 MIRBuilder.getMRI()->setType(NewRegister, LLT::pointer(0, 64)); 3629 GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF()); 3630 3631 // Build global variable with the necessary decorations for the input ID 3632 // builtin variable. 3633 Register Variable = GR.buildGlobalVariable( 3634 NewRegister, PtrType, getLinkStringForBuiltIn(BuiltInValue), nullptr, 3635 SPIRV::StorageClass::Input, nullptr, true, true, 3636 SPIRV::LinkageType::Import, MIRBuilder, false); 3637 3638 // Create new register for loading value. 3639 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); 3640 Register LoadedRegister = MRI->createVirtualRegister(&SPIRV::iIDRegClass); 3641 MIRBuilder.getMRI()->setType(LoadedRegister, LLT::pointer(0, 64)); 3642 GR.assignSPIRVTypeToVReg(Vec3Ty, LoadedRegister, MIRBuilder.getMF()); 3643 3644 // Load v3uint value from the global variable. 3645 bool Result = 3646 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) 3647 .addDef(LoadedRegister) 3648 .addUse(GR.getSPIRVTypeID(Vec3Ty)) 3649 .addUse(Variable); 3650 3651 // Get the input ID index. Expecting operand is a constant immediate value, 3652 // wrapped in a type assignment. 3653 assert(I.getOperand(2).isReg()); 3654 const uint32_t ThreadId = foldImm(I.getOperand(2), MRI); 3655 3656 // Extract the input ID from the loaded vector value. 3657 MachineBasicBlock &BB = *I.getParent(); 3658 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) 3659 .addDef(ResVReg) 3660 .addUse(GR.getSPIRVTypeID(ResType)) 3661 .addUse(LoadedRegister) 3662 .addImm(ThreadId); 3663 return Result && MIB.constrainAllUses(TII, TRI, RBI); 3664 } 3665 3666 SPIRVType *SPIRVInstructionSelector::widenTypeToVec4(const SPIRVType *Type, 3667 MachineInstr &I) const { 3668 MachineIRBuilder MIRBuilder(I); 3669 if (Type->getOpcode() != SPIRV::OpTypeVector) 3670 return GR.getOrCreateSPIRVVectorType(Type, 4, MIRBuilder); 3671 3672 uint64_t VectorSize = Type->getOperand(2).getImm(); 3673 if (VectorSize == 4) 3674 return Type; 3675 3676 Register ScalarTypeReg = Type->getOperand(1).getReg(); 3677 const SPIRVType *ScalarType = GR.getSPIRVTypeForVReg(ScalarTypeReg); 3678 return GR.getOrCreateSPIRVVectorType(ScalarType, 4, MIRBuilder); 3679 } 3680 3681 namespace llvm { 3682 InstructionSelector * 3683 createSPIRVInstructionSelector(const SPIRVTargetMachine &TM, 3684 const SPIRVSubtarget &Subtarget, 3685 const RegisterBankInfo &RBI) { 3686 return new SPIRVInstructionSelector(TM, Subtarget, RBI); 3687 } 3688 } // namespace llvm 3689