1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "PPCTargetTransformInfo.h" 10 #include "llvm/Analysis/CodeMetrics.h" 11 #include "llvm/Analysis/TargetLibraryInfo.h" 12 #include "llvm/Analysis/TargetTransformInfo.h" 13 #include "llvm/CodeGen/BasicTTIImpl.h" 14 #include "llvm/CodeGen/CostTable.h" 15 #include "llvm/CodeGen/TargetLowering.h" 16 #include "llvm/CodeGen/TargetSchedule.h" 17 #include "llvm/IR/IntrinsicsPowerPC.h" 18 #include "llvm/IR/ProfDataUtils.h" 19 #include "llvm/Support/CommandLine.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/KnownBits.h" 22 #include "llvm/Transforms/InstCombine/InstCombiner.h" 23 #include "llvm/Transforms/Utils/Local.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "ppctti" 28 29 static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting", 30 cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden); 31 32 static cl::opt<bool> 33 EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false), 34 cl::desc("Enable using coldcc calling conv for cold " 35 "internal functions")); 36 37 static cl::opt<bool> 38 LsrNoInsnsCost("ppc-lsr-no-insns-cost", cl::Hidden, cl::init(false), 39 cl::desc("Do not add instruction count to lsr cost model")); 40 41 // The latency of mtctr is only justified if there are more than 4 42 // comparisons that will be removed as a result. 43 static cl::opt<unsigned> 44 SmallCTRLoopThreshold("min-ctr-loop-threshold", cl::init(4), cl::Hidden, 45 cl::desc("Loops with a constant trip count smaller than " 46 "this value will not use the count register.")); 47 48 //===----------------------------------------------------------------------===// 49 // 50 // PPC cost model. 51 // 52 //===----------------------------------------------------------------------===// 53 54 TargetTransformInfo::PopcntSupportKind 55 PPCTTIImpl::getPopcntSupport(unsigned TyWidth) { 56 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 57 if (ST->hasPOPCNTD() != PPCSubtarget::POPCNTD_Unavailable && TyWidth <= 64) 58 return ST->hasPOPCNTD() == PPCSubtarget::POPCNTD_Slow ? 59 TTI::PSK_SlowHardware : TTI::PSK_FastHardware; 60 return TTI::PSK_Software; 61 } 62 63 Optional<Instruction *> 64 PPCTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { 65 Intrinsic::ID IID = II.getIntrinsicID(); 66 switch (IID) { 67 default: 68 break; 69 case Intrinsic::ppc_altivec_lvx: 70 case Intrinsic::ppc_altivec_lvxl: 71 // Turn PPC lvx -> load if the pointer is known aligned. 72 if (getOrEnforceKnownAlignment( 73 II.getArgOperand(0), Align(16), IC.getDataLayout(), &II, 74 &IC.getAssumptionCache(), &IC.getDominatorTree()) >= 16) { 75 Value *Ptr = IC.Builder.CreateBitCast( 76 II.getArgOperand(0), PointerType::getUnqual(II.getType())); 77 return new LoadInst(II.getType(), Ptr, "", false, Align(16)); 78 } 79 break; 80 case Intrinsic::ppc_vsx_lxvw4x: 81 case Intrinsic::ppc_vsx_lxvd2x: { 82 // Turn PPC VSX loads into normal loads. 83 Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(0), 84 PointerType::getUnqual(II.getType())); 85 return new LoadInst(II.getType(), Ptr, Twine(""), false, Align(1)); 86 } 87 case Intrinsic::ppc_altivec_stvx: 88 case Intrinsic::ppc_altivec_stvxl: 89 // Turn stvx -> store if the pointer is known aligned. 90 if (getOrEnforceKnownAlignment( 91 II.getArgOperand(1), Align(16), IC.getDataLayout(), &II, 92 &IC.getAssumptionCache(), &IC.getDominatorTree()) >= 16) { 93 Type *OpPtrTy = PointerType::getUnqual(II.getArgOperand(0)->getType()); 94 Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(1), OpPtrTy); 95 return new StoreInst(II.getArgOperand(0), Ptr, false, Align(16)); 96 } 97 break; 98 case Intrinsic::ppc_vsx_stxvw4x: 99 case Intrinsic::ppc_vsx_stxvd2x: { 100 // Turn PPC VSX stores into normal stores. 101 Type *OpPtrTy = PointerType::getUnqual(II.getArgOperand(0)->getType()); 102 Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(1), OpPtrTy); 103 return new StoreInst(II.getArgOperand(0), Ptr, false, Align(1)); 104 } 105 case Intrinsic::ppc_altivec_vperm: 106 // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant. 107 // Note that ppc_altivec_vperm has a big-endian bias, so when creating 108 // a vectorshuffle for little endian, we must undo the transformation 109 // performed on vec_perm in altivec.h. That is, we must complement 110 // the permutation mask with respect to 31 and reverse the order of 111 // V1 and V2. 112 if (Constant *Mask = dyn_cast<Constant>(II.getArgOperand(2))) { 113 assert(cast<FixedVectorType>(Mask->getType())->getNumElements() == 16 && 114 "Bad type for intrinsic!"); 115 116 // Check that all of the elements are integer constants or undefs. 117 bool AllEltsOk = true; 118 for (unsigned i = 0; i != 16; ++i) { 119 Constant *Elt = Mask->getAggregateElement(i); 120 if (!Elt || !(isa<ConstantInt>(Elt) || isa<UndefValue>(Elt))) { 121 AllEltsOk = false; 122 break; 123 } 124 } 125 126 if (AllEltsOk) { 127 // Cast the input vectors to byte vectors. 128 Value *Op0 = 129 IC.Builder.CreateBitCast(II.getArgOperand(0), Mask->getType()); 130 Value *Op1 = 131 IC.Builder.CreateBitCast(II.getArgOperand(1), Mask->getType()); 132 Value *Result = UndefValue::get(Op0->getType()); 133 134 // Only extract each element once. 135 Value *ExtractedElts[32]; 136 memset(ExtractedElts, 0, sizeof(ExtractedElts)); 137 138 for (unsigned i = 0; i != 16; ++i) { 139 if (isa<UndefValue>(Mask->getAggregateElement(i))) 140 continue; 141 unsigned Idx = 142 cast<ConstantInt>(Mask->getAggregateElement(i))->getZExtValue(); 143 Idx &= 31; // Match the hardware behavior. 144 if (DL.isLittleEndian()) 145 Idx = 31 - Idx; 146 147 if (!ExtractedElts[Idx]) { 148 Value *Op0ToUse = (DL.isLittleEndian()) ? Op1 : Op0; 149 Value *Op1ToUse = (DL.isLittleEndian()) ? Op0 : Op1; 150 ExtractedElts[Idx] = IC.Builder.CreateExtractElement( 151 Idx < 16 ? Op0ToUse : Op1ToUse, IC.Builder.getInt32(Idx & 15)); 152 } 153 154 // Insert this value into the result vector. 155 Result = IC.Builder.CreateInsertElement(Result, ExtractedElts[Idx], 156 IC.Builder.getInt32(i)); 157 } 158 return CastInst::Create(Instruction::BitCast, Result, II.getType()); 159 } 160 } 161 break; 162 } 163 return None; 164 } 165 166 InstructionCost PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 167 TTI::TargetCostKind CostKind) { 168 if (DisablePPCConstHoist) 169 return BaseT::getIntImmCost(Imm, Ty, CostKind); 170 171 assert(Ty->isIntegerTy()); 172 173 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 174 if (BitSize == 0) 175 return ~0U; 176 177 if (Imm == 0) 178 return TTI::TCC_Free; 179 180 if (Imm.getBitWidth() <= 64) { 181 if (isInt<16>(Imm.getSExtValue())) 182 return TTI::TCC_Basic; 183 184 if (isInt<32>(Imm.getSExtValue())) { 185 // A constant that can be materialized using lis. 186 if ((Imm.getZExtValue() & 0xFFFF) == 0) 187 return TTI::TCC_Basic; 188 189 return 2 * TTI::TCC_Basic; 190 } 191 } 192 193 return 4 * TTI::TCC_Basic; 194 } 195 196 InstructionCost PPCTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 197 const APInt &Imm, Type *Ty, 198 TTI::TargetCostKind CostKind) { 199 if (DisablePPCConstHoist) 200 return BaseT::getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind); 201 202 assert(Ty->isIntegerTy()); 203 204 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 205 if (BitSize == 0) 206 return ~0U; 207 208 switch (IID) { 209 default: 210 return TTI::TCC_Free; 211 case Intrinsic::sadd_with_overflow: 212 case Intrinsic::uadd_with_overflow: 213 case Intrinsic::ssub_with_overflow: 214 case Intrinsic::usub_with_overflow: 215 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())) 216 return TTI::TCC_Free; 217 break; 218 case Intrinsic::experimental_stackmap: 219 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 220 return TTI::TCC_Free; 221 break; 222 case Intrinsic::experimental_patchpoint_void: 223 case Intrinsic::experimental_patchpoint_i64: 224 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 225 return TTI::TCC_Free; 226 break; 227 } 228 return PPCTTIImpl::getIntImmCost(Imm, Ty, CostKind); 229 } 230 231 InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 232 const APInt &Imm, Type *Ty, 233 TTI::TargetCostKind CostKind, 234 Instruction *Inst) { 235 if (DisablePPCConstHoist) 236 return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst); 237 238 assert(Ty->isIntegerTy()); 239 240 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 241 if (BitSize == 0) 242 return ~0U; 243 244 unsigned ImmIdx = ~0U; 245 bool ShiftedFree = false, RunFree = false, UnsignedFree = false, 246 ZeroFree = false; 247 switch (Opcode) { 248 default: 249 return TTI::TCC_Free; 250 case Instruction::GetElementPtr: 251 // Always hoist the base address of a GetElementPtr. This prevents the 252 // creation of new constants for every base constant that gets constant 253 // folded with the offset. 254 if (Idx == 0) 255 return 2 * TTI::TCC_Basic; 256 return TTI::TCC_Free; 257 case Instruction::And: 258 RunFree = true; // (for the rotate-and-mask instructions) 259 [[fallthrough]]; 260 case Instruction::Add: 261 case Instruction::Or: 262 case Instruction::Xor: 263 ShiftedFree = true; 264 [[fallthrough]]; 265 case Instruction::Sub: 266 case Instruction::Mul: 267 case Instruction::Shl: 268 case Instruction::LShr: 269 case Instruction::AShr: 270 ImmIdx = 1; 271 break; 272 case Instruction::ICmp: 273 UnsignedFree = true; 274 ImmIdx = 1; 275 // Zero comparisons can use record-form instructions. 276 [[fallthrough]]; 277 case Instruction::Select: 278 ZeroFree = true; 279 break; 280 case Instruction::PHI: 281 case Instruction::Call: 282 case Instruction::Ret: 283 case Instruction::Load: 284 case Instruction::Store: 285 break; 286 } 287 288 if (ZeroFree && Imm == 0) 289 return TTI::TCC_Free; 290 291 if (Idx == ImmIdx && Imm.getBitWidth() <= 64) { 292 if (isInt<16>(Imm.getSExtValue())) 293 return TTI::TCC_Free; 294 295 if (RunFree) { 296 if (Imm.getBitWidth() <= 32 && 297 (isShiftedMask_32(Imm.getZExtValue()) || 298 isShiftedMask_32(~Imm.getZExtValue()))) 299 return TTI::TCC_Free; 300 301 if (ST->isPPC64() && 302 (isShiftedMask_64(Imm.getZExtValue()) || 303 isShiftedMask_64(~Imm.getZExtValue()))) 304 return TTI::TCC_Free; 305 } 306 307 if (UnsignedFree && isUInt<16>(Imm.getZExtValue())) 308 return TTI::TCC_Free; 309 310 if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0) 311 return TTI::TCC_Free; 312 } 313 314 return PPCTTIImpl::getIntImmCost(Imm, Ty, CostKind); 315 } 316 317 // Check if the current Type is an MMA vector type. Valid MMA types are 318 // v256i1 and v512i1 respectively. 319 static bool isMMAType(Type *Ty) { 320 return Ty->isVectorTy() && (Ty->getScalarSizeInBits() == 1) && 321 (Ty->getPrimitiveSizeInBits() > 128); 322 } 323 324 InstructionCost PPCTTIImpl::getInstructionCost(const User *U, 325 ArrayRef<const Value *> Operands, 326 TTI::TargetCostKind CostKind) { 327 // We already implement getCastInstrCost and getMemoryOpCost where we perform 328 // the vector adjustment there. 329 if (isa<CastInst>(U) || isa<LoadInst>(U) || isa<StoreInst>(U)) 330 return BaseT::getInstructionCost(U, Operands, CostKind); 331 332 if (U->getType()->isVectorTy()) { 333 // Instructions that need to be split should cost more. 334 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(U->getType()); 335 return LT.first * BaseT::getInstructionCost(U, Operands, CostKind); 336 } 337 338 return BaseT::getInstructionCost(U, Operands, CostKind); 339 } 340 341 // Determining the address of a TLS variable results in a function call in 342 // certain TLS models. 343 static bool memAddrUsesCTR(const Value *MemAddr, const PPCTargetMachine &TM, 344 SmallPtrSetImpl<const Value *> &Visited) { 345 // No need to traverse again if we already checked this operand. 346 if (!Visited.insert(MemAddr).second) 347 return false; 348 const auto *GV = dyn_cast<GlobalValue>(MemAddr); 349 if (!GV) { 350 // Recurse to check for constants that refer to TLS global variables. 351 if (const auto *CV = dyn_cast<Constant>(MemAddr)) 352 for (const auto &CO : CV->operands()) 353 if (memAddrUsesCTR(CO, TM, Visited)) 354 return true; 355 return false; 356 } 357 358 if (!GV->isThreadLocal()) 359 return false; 360 TLSModel::Model Model = TM.getTLSModel(GV); 361 return Model == TLSModel::GeneralDynamic || Model == TLSModel::LocalDynamic; 362 } 363 364 bool PPCTTIImpl::mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo, 365 SmallPtrSetImpl<const Value *> &Visited) { 366 const PPCTargetMachine &TM = ST->getTargetMachine(); 367 368 // Loop through the inline asm constraints and look for something that 369 // clobbers ctr. 370 auto asmClobbersCTR = [](InlineAsm *IA) { 371 InlineAsm::ConstraintInfoVector CIV = IA->ParseConstraints(); 372 for (const InlineAsm::ConstraintInfo &C : CIV) { 373 if (C.Type != InlineAsm::isInput) 374 for (const auto &Code : C.Codes) 375 if (StringRef(Code).equals_insensitive("{ctr}")) 376 return true; 377 } 378 return false; 379 }; 380 381 auto isLargeIntegerTy = [](bool Is32Bit, Type *Ty) { 382 if (IntegerType *ITy = dyn_cast<IntegerType>(Ty)) 383 return ITy->getBitWidth() > (Is32Bit ? 32U : 64U); 384 385 return false; 386 }; 387 388 auto supportedHalfPrecisionOp = [](Instruction *Inst) { 389 switch (Inst->getOpcode()) { 390 default: 391 return false; 392 case Instruction::FPTrunc: 393 case Instruction::FPExt: 394 case Instruction::Load: 395 case Instruction::Store: 396 case Instruction::FPToUI: 397 case Instruction::UIToFP: 398 case Instruction::FPToSI: 399 case Instruction::SIToFP: 400 return true; 401 } 402 }; 403 404 for (BasicBlock::iterator J = BB->begin(), JE = BB->end(); 405 J != JE; ++J) { 406 // There are no direct operations on half precision so assume that 407 // anything with that type requires a call except for a few select 408 // operations with Power9. 409 if (Instruction *CurrInst = dyn_cast<Instruction>(J)) { 410 for (const auto &Op : CurrInst->operands()) { 411 if (Op->getType()->getScalarType()->isHalfTy() || 412 CurrInst->getType()->getScalarType()->isHalfTy()) 413 return !(ST->isISA3_0() && supportedHalfPrecisionOp(CurrInst)); 414 } 415 } 416 if (CallInst *CI = dyn_cast<CallInst>(J)) { 417 // Inline ASM is okay, unless it clobbers the ctr register. 418 if (InlineAsm *IA = dyn_cast<InlineAsm>(CI->getCalledOperand())) { 419 if (asmClobbersCTR(IA)) 420 return true; 421 continue; 422 } 423 424 if (Function *F = CI->getCalledFunction()) { 425 // Most intrinsics don't become function calls, but some might. 426 // sin, cos, exp and log are always calls. 427 unsigned Opcode = 0; 428 if (F->getIntrinsicID() != Intrinsic::not_intrinsic) { 429 switch (F->getIntrinsicID()) { 430 default: continue; 431 // If we have a call to loop_decrement or set_loop_iterations, 432 // we're definitely using CTR. 433 case Intrinsic::set_loop_iterations: 434 case Intrinsic::loop_decrement: 435 return true; 436 437 // Binary operations on 128-bit value will use CTR. 438 case Intrinsic::experimental_constrained_fadd: 439 case Intrinsic::experimental_constrained_fsub: 440 case Intrinsic::experimental_constrained_fmul: 441 case Intrinsic::experimental_constrained_fdiv: 442 case Intrinsic::experimental_constrained_frem: 443 if (F->getType()->getScalarType()->isFP128Ty() || 444 F->getType()->getScalarType()->isPPC_FP128Ty()) 445 return true; 446 break; 447 448 case Intrinsic::experimental_constrained_fptosi: 449 case Intrinsic::experimental_constrained_fptoui: 450 case Intrinsic::experimental_constrained_sitofp: 451 case Intrinsic::experimental_constrained_uitofp: { 452 Type *SrcType = CI->getArgOperand(0)->getType()->getScalarType(); 453 Type *DstType = CI->getType()->getScalarType(); 454 if (SrcType->isPPC_FP128Ty() || DstType->isPPC_FP128Ty() || 455 isLargeIntegerTy(!TM.isPPC64(), SrcType) || 456 isLargeIntegerTy(!TM.isPPC64(), DstType)) 457 return true; 458 break; 459 } 460 461 // Exclude eh_sjlj_setjmp; we don't need to exclude eh_sjlj_longjmp 462 // because, although it does clobber the counter register, the 463 // control can't then return to inside the loop unless there is also 464 // an eh_sjlj_setjmp. 465 case Intrinsic::eh_sjlj_setjmp: 466 467 case Intrinsic::memcpy: 468 case Intrinsic::memmove: 469 case Intrinsic::memset: 470 case Intrinsic::powi: 471 case Intrinsic::log: 472 case Intrinsic::log2: 473 case Intrinsic::log10: 474 case Intrinsic::exp: 475 case Intrinsic::exp2: 476 case Intrinsic::pow: 477 case Intrinsic::sin: 478 case Intrinsic::cos: 479 case Intrinsic::experimental_constrained_powi: 480 case Intrinsic::experimental_constrained_log: 481 case Intrinsic::experimental_constrained_log2: 482 case Intrinsic::experimental_constrained_log10: 483 case Intrinsic::experimental_constrained_exp: 484 case Intrinsic::experimental_constrained_exp2: 485 case Intrinsic::experimental_constrained_pow: 486 case Intrinsic::experimental_constrained_sin: 487 case Intrinsic::experimental_constrained_cos: 488 return true; 489 case Intrinsic::copysign: 490 if (CI->getArgOperand(0)->getType()->getScalarType()-> 491 isPPC_FP128Ty()) 492 return true; 493 else 494 continue; // ISD::FCOPYSIGN is never a library call. 495 case Intrinsic::fmuladd: 496 case Intrinsic::fma: Opcode = ISD::FMA; break; 497 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 498 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 499 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 500 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 501 case Intrinsic::rint: Opcode = ISD::FRINT; break; 502 case Intrinsic::lrint: Opcode = ISD::LRINT; break; 503 case Intrinsic::llrint: Opcode = ISD::LLRINT; break; 504 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; 505 case Intrinsic::round: Opcode = ISD::FROUND; break; 506 case Intrinsic::lround: Opcode = ISD::LROUND; break; 507 case Intrinsic::llround: Opcode = ISD::LLROUND; break; 508 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; 509 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; 510 case Intrinsic::experimental_constrained_fcmp: 511 Opcode = ISD::STRICT_FSETCC; 512 break; 513 case Intrinsic::experimental_constrained_fcmps: 514 Opcode = ISD::STRICT_FSETCCS; 515 break; 516 case Intrinsic::experimental_constrained_fma: 517 Opcode = ISD::STRICT_FMA; 518 break; 519 case Intrinsic::experimental_constrained_sqrt: 520 Opcode = ISD::STRICT_FSQRT; 521 break; 522 case Intrinsic::experimental_constrained_floor: 523 Opcode = ISD::STRICT_FFLOOR; 524 break; 525 case Intrinsic::experimental_constrained_ceil: 526 Opcode = ISD::STRICT_FCEIL; 527 break; 528 case Intrinsic::experimental_constrained_trunc: 529 Opcode = ISD::STRICT_FTRUNC; 530 break; 531 case Intrinsic::experimental_constrained_rint: 532 Opcode = ISD::STRICT_FRINT; 533 break; 534 case Intrinsic::experimental_constrained_lrint: 535 Opcode = ISD::STRICT_LRINT; 536 break; 537 case Intrinsic::experimental_constrained_llrint: 538 Opcode = ISD::STRICT_LLRINT; 539 break; 540 case Intrinsic::experimental_constrained_nearbyint: 541 Opcode = ISD::STRICT_FNEARBYINT; 542 break; 543 case Intrinsic::experimental_constrained_round: 544 Opcode = ISD::STRICT_FROUND; 545 break; 546 case Intrinsic::experimental_constrained_lround: 547 Opcode = ISD::STRICT_LROUND; 548 break; 549 case Intrinsic::experimental_constrained_llround: 550 Opcode = ISD::STRICT_LLROUND; 551 break; 552 case Intrinsic::experimental_constrained_minnum: 553 Opcode = ISD::STRICT_FMINNUM; 554 break; 555 case Intrinsic::experimental_constrained_maxnum: 556 Opcode = ISD::STRICT_FMAXNUM; 557 break; 558 case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break; 559 case Intrinsic::smul_with_overflow: Opcode = ISD::SMULO; break; 560 } 561 } 562 563 // PowerPC does not use [US]DIVREM or other library calls for 564 // operations on regular types which are not otherwise library calls 565 // (i.e. soft float or atomics). If adapting for targets that do, 566 // additional care is required here. 567 568 LibFunc Func; 569 if (!F->hasLocalLinkage() && F->hasName() && LibInfo && 570 LibInfo->getLibFunc(F->getName(), Func) && 571 LibInfo->hasOptimizedCodeGen(Func)) { 572 // Non-read-only functions are never treated as intrinsics. 573 if (!CI->onlyReadsMemory()) 574 return true; 575 576 // Conversion happens only for FP calls. 577 if (!CI->getArgOperand(0)->getType()->isFloatingPointTy()) 578 return true; 579 580 switch (Func) { 581 default: return true; 582 case LibFunc_copysign: 583 case LibFunc_copysignf: 584 continue; // ISD::FCOPYSIGN is never a library call. 585 case LibFunc_copysignl: 586 return true; 587 case LibFunc_fabs: 588 case LibFunc_fabsf: 589 case LibFunc_fabsl: 590 continue; // ISD::FABS is never a library call. 591 case LibFunc_sqrt: 592 case LibFunc_sqrtf: 593 case LibFunc_sqrtl: 594 Opcode = ISD::FSQRT; break; 595 case LibFunc_floor: 596 case LibFunc_floorf: 597 case LibFunc_floorl: 598 Opcode = ISD::FFLOOR; break; 599 case LibFunc_nearbyint: 600 case LibFunc_nearbyintf: 601 case LibFunc_nearbyintl: 602 Opcode = ISD::FNEARBYINT; break; 603 case LibFunc_ceil: 604 case LibFunc_ceilf: 605 case LibFunc_ceill: 606 Opcode = ISD::FCEIL; break; 607 case LibFunc_rint: 608 case LibFunc_rintf: 609 case LibFunc_rintl: 610 Opcode = ISD::FRINT; break; 611 case LibFunc_round: 612 case LibFunc_roundf: 613 case LibFunc_roundl: 614 Opcode = ISD::FROUND; break; 615 case LibFunc_trunc: 616 case LibFunc_truncf: 617 case LibFunc_truncl: 618 Opcode = ISD::FTRUNC; break; 619 case LibFunc_fmin: 620 case LibFunc_fminf: 621 case LibFunc_fminl: 622 Opcode = ISD::FMINNUM; break; 623 case LibFunc_fmax: 624 case LibFunc_fmaxf: 625 case LibFunc_fmaxl: 626 Opcode = ISD::FMAXNUM; break; 627 } 628 } 629 630 if (Opcode) { 631 EVT EVTy = 632 TLI->getValueType(DL, CI->getArgOperand(0)->getType(), true); 633 634 if (EVTy == MVT::Other) 635 return true; 636 637 if (TLI->isOperationLegalOrCustom(Opcode, EVTy)) 638 continue; 639 else if (EVTy.isVector() && 640 TLI->isOperationLegalOrCustom(Opcode, EVTy.getScalarType())) 641 continue; 642 643 return true; 644 } 645 } 646 647 return true; 648 } else if ((J->getType()->getScalarType()->isFP128Ty() || 649 J->getType()->getScalarType()->isPPC_FP128Ty())) { 650 // Most operations on f128 or ppc_f128 values become calls. 651 return true; 652 } else if (isa<FCmpInst>(J) && 653 J->getOperand(0)->getType()->getScalarType()->isFP128Ty()) { 654 return true; 655 } else if ((isa<FPTruncInst>(J) || isa<FPExtInst>(J)) && 656 (cast<CastInst>(J)->getSrcTy()->getScalarType()->isFP128Ty() || 657 cast<CastInst>(J)->getDestTy()->getScalarType()->isFP128Ty())) { 658 return true; 659 } else if (isa<UIToFPInst>(J) || isa<SIToFPInst>(J) || 660 isa<FPToUIInst>(J) || isa<FPToSIInst>(J)) { 661 CastInst *CI = cast<CastInst>(J); 662 if (CI->getSrcTy()->getScalarType()->isPPC_FP128Ty() || 663 CI->getDestTy()->getScalarType()->isPPC_FP128Ty() || 664 isLargeIntegerTy(!TM.isPPC64(), CI->getSrcTy()->getScalarType()) || 665 isLargeIntegerTy(!TM.isPPC64(), CI->getDestTy()->getScalarType())) 666 return true; 667 } else if (isLargeIntegerTy(!TM.isPPC64(), 668 J->getType()->getScalarType()) && 669 (J->getOpcode() == Instruction::UDiv || 670 J->getOpcode() == Instruction::SDiv || 671 J->getOpcode() == Instruction::URem || 672 J->getOpcode() == Instruction::SRem)) { 673 return true; 674 } else if (!TM.isPPC64() && 675 isLargeIntegerTy(false, J->getType()->getScalarType()) && 676 (J->getOpcode() == Instruction::Shl || 677 J->getOpcode() == Instruction::AShr || 678 J->getOpcode() == Instruction::LShr)) { 679 // Only on PPC32, for 128-bit integers (specifically not 64-bit 680 // integers), these might be runtime calls. 681 return true; 682 } else if (isa<IndirectBrInst>(J) || isa<InvokeInst>(J)) { 683 // On PowerPC, indirect jumps use the counter register. 684 return true; 685 } else if (SwitchInst *SI = dyn_cast<SwitchInst>(J)) { 686 if (SI->getNumCases() + 1 >= (unsigned)TLI->getMinimumJumpTableEntries()) 687 return true; 688 } 689 690 // FREM is always a call. 691 if (J->getOpcode() == Instruction::FRem) 692 return true; 693 694 if (ST->useSoftFloat()) { 695 switch(J->getOpcode()) { 696 case Instruction::FAdd: 697 case Instruction::FSub: 698 case Instruction::FMul: 699 case Instruction::FDiv: 700 case Instruction::FPTrunc: 701 case Instruction::FPExt: 702 case Instruction::FPToUI: 703 case Instruction::FPToSI: 704 case Instruction::UIToFP: 705 case Instruction::SIToFP: 706 case Instruction::FCmp: 707 return true; 708 } 709 } 710 711 for (Value *Operand : J->operands()) 712 if (memAddrUsesCTR(Operand, TM, Visited)) 713 return true; 714 } 715 716 return false; 717 } 718 719 bool PPCTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, 720 AssumptionCache &AC, 721 TargetLibraryInfo *LibInfo, 722 HardwareLoopInfo &HWLoopInfo) { 723 const PPCTargetMachine &TM = ST->getTargetMachine(); 724 TargetSchedModel SchedModel; 725 SchedModel.init(ST); 726 727 // Do not convert small short loops to CTR loop. 728 unsigned ConstTripCount = SE.getSmallConstantTripCount(L); 729 if (ConstTripCount && ConstTripCount < SmallCTRLoopThreshold) { 730 SmallPtrSet<const Value *, 32> EphValues; 731 CodeMetrics::collectEphemeralValues(L, &AC, EphValues); 732 CodeMetrics Metrics; 733 for (BasicBlock *BB : L->blocks()) 734 Metrics.analyzeBasicBlock(BB, *this, EphValues); 735 // 6 is an approximate latency for the mtctr instruction. 736 if (Metrics.NumInsts <= (6 * SchedModel.getIssueWidth())) 737 return false; 738 } 739 740 // We don't want to spill/restore the counter register, and so we don't 741 // want to use the counter register if the loop contains calls. 742 SmallPtrSet<const Value *, 4> Visited; 743 for (Loop::block_iterator I = L->block_begin(), IE = L->block_end(); 744 I != IE; ++I) 745 if (mightUseCTR(*I, LibInfo, Visited)) 746 return false; 747 748 SmallVector<BasicBlock*, 4> ExitingBlocks; 749 L->getExitingBlocks(ExitingBlocks); 750 751 // If there is an exit edge known to be frequently taken, 752 // we should not transform this loop. 753 for (auto &BB : ExitingBlocks) { 754 Instruction *TI = BB->getTerminator(); 755 if (!TI) continue; 756 757 if (BranchInst *BI = dyn_cast<BranchInst>(TI)) { 758 uint64_t TrueWeight = 0, FalseWeight = 0; 759 if (!BI->isConditional() || 760 !extractBranchWeights(*BI, TrueWeight, FalseWeight)) 761 continue; 762 763 // If the exit path is more frequent than the loop path, 764 // we return here without further analysis for this loop. 765 bool TrueIsExit = !L->contains(BI->getSuccessor(0)); 766 if (( TrueIsExit && FalseWeight < TrueWeight) || 767 (!TrueIsExit && FalseWeight > TrueWeight)) 768 return false; 769 } 770 } 771 772 // If an exit block has a PHI that accesses a TLS variable as one of the 773 // incoming values from the loop, we cannot produce a CTR loop because the 774 // address for that value will be computed in the loop. 775 SmallVector<BasicBlock *, 4> ExitBlocks; 776 L->getExitBlocks(ExitBlocks); 777 for (auto &BB : ExitBlocks) { 778 for (auto &PHI : BB->phis()) { 779 for (int Idx = 0, EndIdx = PHI.getNumIncomingValues(); Idx < EndIdx; 780 Idx++) { 781 const BasicBlock *IncomingBB = PHI.getIncomingBlock(Idx); 782 const Value *IncomingValue = PHI.getIncomingValue(Idx); 783 if (L->contains(IncomingBB) && 784 memAddrUsesCTR(IncomingValue, TM, Visited)) 785 return false; 786 } 787 } 788 } 789 790 LLVMContext &C = L->getHeader()->getContext(); 791 HWLoopInfo.CountType = TM.isPPC64() ? 792 Type::getInt64Ty(C) : Type::getInt32Ty(C); 793 HWLoopInfo.LoopDecrement = ConstantInt::get(HWLoopInfo.CountType, 1); 794 return true; 795 } 796 797 void PPCTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, 798 TTI::UnrollingPreferences &UP, 799 OptimizationRemarkEmitter *ORE) { 800 if (ST->getCPUDirective() == PPC::DIR_A2) { 801 // The A2 is in-order with a deep pipeline, and concatenation unrolling 802 // helps expose latency-hiding opportunities to the instruction scheduler. 803 UP.Partial = UP.Runtime = true; 804 805 // We unroll a lot on the A2 (hundreds of instructions), and the benefits 806 // often outweigh the cost of a division to compute the trip count. 807 UP.AllowExpensiveTripCount = true; 808 } 809 810 BaseT::getUnrollingPreferences(L, SE, UP, ORE); 811 } 812 813 void PPCTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE, 814 TTI::PeelingPreferences &PP) { 815 BaseT::getPeelingPreferences(L, SE, PP); 816 } 817 // This function returns true to allow using coldcc calling convention. 818 // Returning true results in coldcc being used for functions which are cold at 819 // all call sites when the callers of the functions are not calling any other 820 // non coldcc functions. 821 bool PPCTTIImpl::useColdCCForColdCall(Function &F) { 822 return EnablePPCColdCC; 823 } 824 825 bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) { 826 // On the A2, always unroll aggressively. 827 if (ST->getCPUDirective() == PPC::DIR_A2) 828 return true; 829 830 return LoopHasReductions; 831 } 832 833 PPCTTIImpl::TTI::MemCmpExpansionOptions 834 PPCTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 835 TTI::MemCmpExpansionOptions Options; 836 Options.LoadSizes = {8, 4, 2, 1}; 837 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 838 return Options; 839 } 840 841 bool PPCTTIImpl::enableInterleavedAccessVectorization() { 842 return true; 843 } 844 845 unsigned PPCTTIImpl::getNumberOfRegisters(unsigned ClassID) const { 846 assert(ClassID == GPRRC || ClassID == FPRRC || 847 ClassID == VRRC || ClassID == VSXRC); 848 if (ST->hasVSX()) { 849 assert(ClassID == GPRRC || ClassID == VSXRC || ClassID == VRRC); 850 return ClassID == VSXRC ? 64 : 32; 851 } 852 assert(ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC); 853 return 32; 854 } 855 856 unsigned PPCTTIImpl::getRegisterClassForType(bool Vector, Type *Ty) const { 857 if (Vector) 858 return ST->hasVSX() ? VSXRC : VRRC; 859 else if (Ty && (Ty->getScalarType()->isFloatTy() || 860 Ty->getScalarType()->isDoubleTy())) 861 return ST->hasVSX() ? VSXRC : FPRRC; 862 else if (Ty && (Ty->getScalarType()->isFP128Ty() || 863 Ty->getScalarType()->isPPC_FP128Ty())) 864 return VRRC; 865 else if (Ty && Ty->getScalarType()->isHalfTy()) 866 return VSXRC; 867 else 868 return GPRRC; 869 } 870 871 const char* PPCTTIImpl::getRegisterClassName(unsigned ClassID) const { 872 873 switch (ClassID) { 874 default: 875 llvm_unreachable("unknown register class"); 876 return "PPC::unknown register class"; 877 case GPRRC: return "PPC::GPRRC"; 878 case FPRRC: return "PPC::FPRRC"; 879 case VRRC: return "PPC::VRRC"; 880 case VSXRC: return "PPC::VSXRC"; 881 } 882 } 883 884 TypeSize 885 PPCTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 886 switch (K) { 887 case TargetTransformInfo::RGK_Scalar: 888 return TypeSize::getFixed(ST->isPPC64() ? 64 : 32); 889 case TargetTransformInfo::RGK_FixedWidthVector: 890 return TypeSize::getFixed(ST->hasAltivec() ? 128 : 0); 891 case TargetTransformInfo::RGK_ScalableVector: 892 return TypeSize::getScalable(0); 893 } 894 895 llvm_unreachable("Unsupported register kind"); 896 } 897 898 unsigned PPCTTIImpl::getCacheLineSize() const { 899 // Starting with P7 we have a cache line size of 128. 900 unsigned Directive = ST->getCPUDirective(); 901 // Assume that Future CPU has the same cache line size as the others. 902 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 || 903 Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 || 904 Directive == PPC::DIR_PWR_FUTURE) 905 return 128; 906 907 // On other processors return a default of 64 bytes. 908 return 64; 909 } 910 911 unsigned PPCTTIImpl::getPrefetchDistance() const { 912 return 300; 913 } 914 915 unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) { 916 unsigned Directive = ST->getCPUDirective(); 917 // The 440 has no SIMD support, but floating-point instructions 918 // have a 5-cycle latency, so unroll by 5x for latency hiding. 919 if (Directive == PPC::DIR_440) 920 return 5; 921 922 // The A2 has no SIMD support, but floating-point instructions 923 // have a 6-cycle latency, so unroll by 6x for latency hiding. 924 if (Directive == PPC::DIR_A2) 925 return 6; 926 927 // FIXME: For lack of any better information, do no harm... 928 if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) 929 return 1; 930 931 // For P7 and P8, floating-point instructions have a 6-cycle latency and 932 // there are two execution units, so unroll by 12x for latency hiding. 933 // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready 934 // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready 935 // Assume that future is the same as the others. 936 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 || 937 Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 || 938 Directive == PPC::DIR_PWR_FUTURE) 939 return 12; 940 941 // For most things, modern systems have two execution units (and 942 // out-of-order execution). 943 return 2; 944 } 945 946 // Returns a cost adjustment factor to adjust the cost of vector instructions 947 // on targets which there is overlap between the vector and scalar units, 948 // thereby reducing the overall throughput of vector code wrt. scalar code. 949 // An invalid instruction cost is returned if the type is an MMA vector type. 950 InstructionCost PPCTTIImpl::vectorCostAdjustmentFactor(unsigned Opcode, 951 Type *Ty1, Type *Ty2) { 952 // If the vector type is of an MMA type (v256i1, v512i1), an invalid 953 // instruction cost is returned. This is to signify to other cost computing 954 // functions to return the maximum instruction cost in order to prevent any 955 // opportunities for the optimizer to produce MMA types within the IR. 956 if (isMMAType(Ty1)) 957 return InstructionCost::getInvalid(); 958 959 if (!ST->vectorsUseTwoUnits() || !Ty1->isVectorTy()) 960 return InstructionCost(1); 961 962 std::pair<InstructionCost, MVT> LT1 = getTypeLegalizationCost(Ty1); 963 // If type legalization involves splitting the vector, we don't want to 964 // double the cost at every step - only the last step. 965 if (LT1.first != 1 || !LT1.second.isVector()) 966 return InstructionCost(1); 967 968 int ISD = TLI->InstructionOpcodeToISD(Opcode); 969 if (TLI->isOperationExpand(ISD, LT1.second)) 970 return InstructionCost(1); 971 972 if (Ty2) { 973 std::pair<InstructionCost, MVT> LT2 = getTypeLegalizationCost(Ty2); 974 if (LT2.first != 1 || !LT2.second.isVector()) 975 return InstructionCost(1); 976 } 977 978 return InstructionCost(2); 979 } 980 981 InstructionCost PPCTTIImpl::getArithmeticInstrCost( 982 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 983 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 984 TTI::OperandValueProperties Opd1PropInfo, 985 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 986 const Instruction *CxtI) { 987 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); 988 989 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Ty, nullptr); 990 if (!CostFactor.isValid()) 991 return InstructionCost::getMax(); 992 993 // TODO: Handle more cost kinds. 994 if (CostKind != TTI::TCK_RecipThroughput) 995 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 996 Op2Info, Opd1PropInfo, 997 Opd2PropInfo, Args, CxtI); 998 999 // Fallback to the default implementation. 1000 InstructionCost Cost = BaseT::getArithmeticInstrCost( 1001 Opcode, Ty, CostKind, Op1Info, Op2Info, Opd1PropInfo, Opd2PropInfo); 1002 return Cost * CostFactor; 1003 } 1004 1005 InstructionCost PPCTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, 1006 ArrayRef<int> Mask, 1007 TTI::TargetCostKind CostKind, 1008 int Index, Type *SubTp, 1009 ArrayRef<const Value *> Args) { 1010 1011 InstructionCost CostFactor = 1012 vectorCostAdjustmentFactor(Instruction::ShuffleVector, Tp, nullptr); 1013 if (!CostFactor.isValid()) 1014 return InstructionCost::getMax(); 1015 1016 // Legalize the type. 1017 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Tp); 1018 1019 // PPC, for both Altivec/VSX, support cheap arbitrary permutations 1020 // (at least in the sense that there need only be one non-loop-invariant 1021 // instruction). We need one such shuffle instruction for each actual 1022 // register (this is not true for arbitrary shuffles, but is true for the 1023 // structured types of shuffles covered by TTI::ShuffleKind). 1024 return LT.first * CostFactor; 1025 } 1026 1027 InstructionCost PPCTTIImpl::getCFInstrCost(unsigned Opcode, 1028 TTI::TargetCostKind CostKind, 1029 const Instruction *I) { 1030 if (CostKind != TTI::TCK_RecipThroughput) 1031 return Opcode == Instruction::PHI ? 0 : 1; 1032 // Branches are assumed to be predicted. 1033 return 0; 1034 } 1035 1036 InstructionCost PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1037 Type *Src, 1038 TTI::CastContextHint CCH, 1039 TTI::TargetCostKind CostKind, 1040 const Instruction *I) { 1041 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); 1042 1043 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Dst, Src); 1044 if (!CostFactor.isValid()) 1045 return InstructionCost::getMax(); 1046 1047 InstructionCost Cost = 1048 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); 1049 Cost *= CostFactor; 1050 // TODO: Allow non-throughput costs that aren't binary. 1051 if (CostKind != TTI::TCK_RecipThroughput) 1052 return Cost == 0 ? 0 : 1; 1053 return Cost; 1054 } 1055 1056 InstructionCost PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 1057 Type *CondTy, 1058 CmpInst::Predicate VecPred, 1059 TTI::TargetCostKind CostKind, 1060 const Instruction *I) { 1061 InstructionCost CostFactor = 1062 vectorCostAdjustmentFactor(Opcode, ValTy, nullptr); 1063 if (!CostFactor.isValid()) 1064 return InstructionCost::getMax(); 1065 1066 InstructionCost Cost = 1067 BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 1068 // TODO: Handle other cost kinds. 1069 if (CostKind != TTI::TCK_RecipThroughput) 1070 return Cost; 1071 return Cost * CostFactor; 1072 } 1073 1074 InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 1075 unsigned Index) { 1076 assert(Val->isVectorTy() && "This must be a vector type"); 1077 1078 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1079 assert(ISD && "Invalid opcode"); 1080 1081 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Val, nullptr); 1082 if (!CostFactor.isValid()) 1083 return InstructionCost::getMax(); 1084 1085 InstructionCost Cost = BaseT::getVectorInstrCost(Opcode, Val, Index); 1086 Cost *= CostFactor; 1087 1088 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) { 1089 // Double-precision scalars are already located in index #0 (or #1 if LE). 1090 if (ISD == ISD::EXTRACT_VECTOR_ELT && 1091 Index == (ST->isLittleEndian() ? 1 : 0)) 1092 return 0; 1093 1094 return Cost; 1095 1096 } else if (Val->getScalarType()->isIntegerTy() && Index != -1U) { 1097 if (ST->hasP9Altivec()) { 1098 if (ISD == ISD::INSERT_VECTOR_ELT) 1099 // A move-to VSR and a permute/insert. Assume vector operation cost 1100 // for both (cost will be 2x on P9). 1101 return 2 * CostFactor; 1102 1103 // It's an extract. Maybe we can do a cheap move-from VSR. 1104 unsigned EltSize = Val->getScalarSizeInBits(); 1105 if (EltSize == 64) { 1106 unsigned MfvsrdIndex = ST->isLittleEndian() ? 1 : 0; 1107 if (Index == MfvsrdIndex) 1108 return 1; 1109 } else if (EltSize == 32) { 1110 unsigned MfvsrwzIndex = ST->isLittleEndian() ? 2 : 1; 1111 if (Index == MfvsrwzIndex) 1112 return 1; 1113 } 1114 1115 // We need a vector extract (or mfvsrld). Assume vector operation cost. 1116 // The cost of the load constant for a vector extract is disregarded 1117 // (invariant, easily schedulable). 1118 return CostFactor; 1119 1120 } else if (ST->hasDirectMove()) 1121 // Assume permute has standard cost. 1122 // Assume move-to/move-from VSR have 2x standard cost. 1123 return 3; 1124 } 1125 1126 // Estimated cost of a load-hit-store delay. This was obtained 1127 // experimentally as a minimum needed to prevent unprofitable 1128 // vectorization for the paq8p benchmark. It may need to be 1129 // raised further if other unprofitable cases remain. 1130 unsigned LHSPenalty = 2; 1131 if (ISD == ISD::INSERT_VECTOR_ELT) 1132 LHSPenalty += 7; 1133 1134 // Vector element insert/extract with Altivec is very expensive, 1135 // because they require store and reload with the attendant 1136 // processor stall for load-hit-store. Until VSX is available, 1137 // these need to be estimated as very costly. 1138 if (ISD == ISD::EXTRACT_VECTOR_ELT || 1139 ISD == ISD::INSERT_VECTOR_ELT) 1140 return LHSPenalty + Cost; 1141 1142 return Cost; 1143 } 1144 1145 InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 1146 MaybeAlign Alignment, 1147 unsigned AddressSpace, 1148 TTI::TargetCostKind CostKind, 1149 TTI::OperandValueKind OpdInfo, 1150 const Instruction *I) { 1151 1152 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Src, nullptr); 1153 if (!CostFactor.isValid()) 1154 return InstructionCost::getMax(); 1155 1156 if (TLI->getValueType(DL, Src, true) == MVT::Other) 1157 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 1158 CostKind); 1159 // Legalize the type. 1160 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Src); 1161 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 1162 "Invalid Opcode"); 1163 1164 InstructionCost Cost = 1165 BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind); 1166 // TODO: Handle other cost kinds. 1167 if (CostKind != TTI::TCK_RecipThroughput) 1168 return Cost; 1169 1170 Cost *= CostFactor; 1171 1172 bool IsAltivecType = ST->hasAltivec() && 1173 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 || 1174 LT.second == MVT::v4i32 || LT.second == MVT::v4f32); 1175 bool IsVSXType = ST->hasVSX() && 1176 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64); 1177 1178 // VSX has 32b/64b load instructions. Legalization can handle loading of 1179 // 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and 1180 // PPCTargetLowering can't compute the cost appropriately. So here we 1181 // explicitly check this case. 1182 unsigned MemBytes = Src->getPrimitiveSizeInBits(); 1183 if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType && 1184 (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32))) 1185 return 1; 1186 1187 // Aligned loads and stores are easy. 1188 unsigned SrcBytes = LT.second.getStoreSize(); 1189 if (!SrcBytes || !Alignment || *Alignment >= SrcBytes) 1190 return Cost; 1191 1192 // If we can use the permutation-based load sequence, then this is also 1193 // relatively cheap (not counting loop-invariant instructions): one load plus 1194 // one permute (the last load in a series has extra cost, but we're 1195 // neglecting that here). Note that on the P7, we could do unaligned loads 1196 // for Altivec types using the VSX instructions, but that's more expensive 1197 // than using the permutation-based load sequence. On the P8, that's no 1198 // longer true. 1199 if (Opcode == Instruction::Load && (!ST->hasP8Vector() && IsAltivecType) && 1200 *Alignment >= LT.second.getScalarType().getStoreSize()) 1201 return Cost + LT.first; // Add the cost of the permutations. 1202 1203 // For VSX, we can do unaligned loads and stores on Altivec/VSX types. On the 1204 // P7, unaligned vector loads are more expensive than the permutation-based 1205 // load sequence, so that might be used instead, but regardless, the net cost 1206 // is about the same (not counting loop-invariant instructions). 1207 if (IsVSXType || (ST->hasVSX() && IsAltivecType)) 1208 return Cost; 1209 1210 // Newer PPC supports unaligned memory access. 1211 if (TLI->allowsMisalignedMemoryAccesses(LT.second, 0)) 1212 return Cost; 1213 1214 // PPC in general does not support unaligned loads and stores. They'll need 1215 // to be decomposed based on the alignment factor. 1216 1217 // Add the cost of each scalar load or store. 1218 assert(Alignment); 1219 Cost += LT.first * ((SrcBytes / Alignment->value()) - 1); 1220 1221 // For a vector type, there is also scalarization overhead (only for 1222 // stores, loads are expanded using the vector-load + permutation sequence, 1223 // which is much less expensive). 1224 if (Src->isVectorTy() && Opcode == Instruction::Store) 1225 for (int i = 0, e = cast<FixedVectorType>(Src)->getNumElements(); i < e; 1226 ++i) 1227 Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i); 1228 1229 return Cost; 1230 } 1231 1232 InstructionCost PPCTTIImpl::getInterleavedMemoryOpCost( 1233 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 1234 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 1235 bool UseMaskForCond, bool UseMaskForGaps) { 1236 InstructionCost CostFactor = 1237 vectorCostAdjustmentFactor(Opcode, VecTy, nullptr); 1238 if (!CostFactor.isValid()) 1239 return InstructionCost::getMax(); 1240 1241 if (UseMaskForCond || UseMaskForGaps) 1242 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 1243 Alignment, AddressSpace, CostKind, 1244 UseMaskForCond, UseMaskForGaps); 1245 1246 assert(isa<VectorType>(VecTy) && 1247 "Expect a vector type for interleaved memory op"); 1248 1249 // Legalize the type. 1250 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(VecTy); 1251 1252 // Firstly, the cost of load/store operation. 1253 InstructionCost Cost = getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment), 1254 AddressSpace, CostKind); 1255 1256 // PPC, for both Altivec/VSX, support cheap arbitrary permutations 1257 // (at least in the sense that there need only be one non-loop-invariant 1258 // instruction). For each result vector, we need one shuffle per incoming 1259 // vector (except that the first shuffle can take two incoming vectors 1260 // because it does not need to take itself). 1261 Cost += Factor*(LT.first-1); 1262 1263 return Cost; 1264 } 1265 1266 InstructionCost 1267 PPCTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 1268 TTI::TargetCostKind CostKind) { 1269 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 1270 } 1271 1272 bool PPCTTIImpl::areTypesABICompatible(const Function *Caller, 1273 const Function *Callee, 1274 const ArrayRef<Type *> &Types) const { 1275 1276 // We need to ensure that argument promotion does not 1277 // attempt to promote pointers to MMA types (__vector_pair 1278 // and __vector_quad) since these types explicitly cannot be 1279 // passed as arguments. Both of these types are larger than 1280 // the 128-bit Altivec vectors and have a scalar size of 1 bit. 1281 if (!BaseT::areTypesABICompatible(Caller, Callee, Types)) 1282 return false; 1283 1284 return llvm::none_of(Types, [](Type *Ty) { 1285 if (Ty->isSized()) 1286 return Ty->isIntOrIntVectorTy(1) && Ty->getPrimitiveSizeInBits() > 128; 1287 return false; 1288 }); 1289 } 1290 1291 bool PPCTTIImpl::canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, 1292 LoopInfo *LI, DominatorTree *DT, 1293 AssumptionCache *AC, TargetLibraryInfo *LibInfo) { 1294 // Process nested loops first. 1295 for (Loop *I : *L) 1296 if (canSaveCmp(I, BI, SE, LI, DT, AC, LibInfo)) 1297 return false; // Stop search. 1298 1299 HardwareLoopInfo HWLoopInfo(L); 1300 1301 if (!HWLoopInfo.canAnalyze(*LI)) 1302 return false; 1303 1304 if (!isHardwareLoopProfitable(L, *SE, *AC, LibInfo, HWLoopInfo)) 1305 return false; 1306 1307 if (!HWLoopInfo.isHardwareLoopCandidate(*SE, *LI, *DT)) 1308 return false; 1309 1310 *BI = HWLoopInfo.ExitBranch; 1311 return true; 1312 } 1313 1314 bool PPCTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1, 1315 const TargetTransformInfo::LSRCost &C2) { 1316 // PowerPC default behaviour here is "instruction number 1st priority". 1317 // If LsrNoInsnsCost is set, call default implementation. 1318 if (!LsrNoInsnsCost) 1319 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, 1320 C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 1321 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, 1322 C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost); 1323 else 1324 return TargetTransformInfoImplBase::isLSRCostLess(C1, C2); 1325 } 1326 1327 bool PPCTTIImpl::isNumRegsMajorCostOfLSR() { 1328 return false; 1329 } 1330 1331 bool PPCTTIImpl::shouldBuildRelLookupTables() const { 1332 const PPCTargetMachine &TM = ST->getTargetMachine(); 1333 // XCOFF hasn't implemented lowerRelativeReference, disable non-ELF for now. 1334 if (!TM.isELFv2ABI()) 1335 return false; 1336 return BaseT::shouldBuildRelLookupTables(); 1337 } 1338 1339 bool PPCTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst, 1340 MemIntrinsicInfo &Info) { 1341 switch (Inst->getIntrinsicID()) { 1342 case Intrinsic::ppc_altivec_lvx: 1343 case Intrinsic::ppc_altivec_lvxl: 1344 case Intrinsic::ppc_altivec_lvebx: 1345 case Intrinsic::ppc_altivec_lvehx: 1346 case Intrinsic::ppc_altivec_lvewx: 1347 case Intrinsic::ppc_vsx_lxvd2x: 1348 case Intrinsic::ppc_vsx_lxvw4x: 1349 case Intrinsic::ppc_vsx_lxvd2x_be: 1350 case Intrinsic::ppc_vsx_lxvw4x_be: 1351 case Intrinsic::ppc_vsx_lxvl: 1352 case Intrinsic::ppc_vsx_lxvll: 1353 case Intrinsic::ppc_vsx_lxvp: { 1354 Info.PtrVal = Inst->getArgOperand(0); 1355 Info.ReadMem = true; 1356 Info.WriteMem = false; 1357 return true; 1358 } 1359 case Intrinsic::ppc_altivec_stvx: 1360 case Intrinsic::ppc_altivec_stvxl: 1361 case Intrinsic::ppc_altivec_stvebx: 1362 case Intrinsic::ppc_altivec_stvehx: 1363 case Intrinsic::ppc_altivec_stvewx: 1364 case Intrinsic::ppc_vsx_stxvd2x: 1365 case Intrinsic::ppc_vsx_stxvw4x: 1366 case Intrinsic::ppc_vsx_stxvd2x_be: 1367 case Intrinsic::ppc_vsx_stxvw4x_be: 1368 case Intrinsic::ppc_vsx_stxvl: 1369 case Intrinsic::ppc_vsx_stxvll: 1370 case Intrinsic::ppc_vsx_stxvp: { 1371 Info.PtrVal = Inst->getArgOperand(1); 1372 Info.ReadMem = false; 1373 Info.WriteMem = true; 1374 return true; 1375 } 1376 default: 1377 break; 1378 } 1379 1380 return false; 1381 } 1382 1383 bool PPCTTIImpl::hasActiveVectorLength(unsigned Opcode, Type *DataType, 1384 Align Alignment) const { 1385 // Only load and stores instructions can have variable vector length on Power. 1386 if (Opcode != Instruction::Load && Opcode != Instruction::Store) 1387 return false; 1388 // Loads/stores with length instructions use bits 0-7 of the GPR operand and 1389 // therefore cannot be used in 32-bit mode. 1390 if ((!ST->hasP9Vector() && !ST->hasP10Vector()) || !ST->isPPC64()) 1391 return false; 1392 if (isa<FixedVectorType>(DataType)) { 1393 unsigned VecWidth = DataType->getPrimitiveSizeInBits(); 1394 return VecWidth == 128; 1395 } 1396 Type *ScalarTy = DataType->getScalarType(); 1397 1398 if (ScalarTy->isPointerTy()) 1399 return true; 1400 1401 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 1402 return true; 1403 1404 if (!ScalarTy->isIntegerTy()) 1405 return false; 1406 1407 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 1408 return IntWidth == 8 || IntWidth == 16 || IntWidth == 32 || IntWidth == 64; 1409 } 1410 1411 InstructionCost PPCTTIImpl::getVPMemoryOpCost(unsigned Opcode, Type *Src, 1412 Align Alignment, 1413 unsigned AddressSpace, 1414 TTI::TargetCostKind CostKind, 1415 const Instruction *I) { 1416 InstructionCost Cost = BaseT::getVPMemoryOpCost(Opcode, Src, Alignment, 1417 AddressSpace, CostKind, I); 1418 if (TLI->getValueType(DL, Src, true) == MVT::Other) 1419 return Cost; 1420 // TODO: Handle other cost kinds. 1421 if (CostKind != TTI::TCK_RecipThroughput) 1422 return Cost; 1423 1424 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 1425 "Invalid Opcode"); 1426 1427 auto *SrcVTy = dyn_cast<FixedVectorType>(Src); 1428 assert(SrcVTy && "Expected a vector type for VP memory operations"); 1429 1430 if (hasActiveVectorLength(Opcode, Src, Alignment)) { 1431 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(SrcVTy); 1432 1433 InstructionCost CostFactor = 1434 vectorCostAdjustmentFactor(Opcode, Src, nullptr); 1435 if (!CostFactor.isValid()) 1436 return InstructionCost::getMax(); 1437 1438 InstructionCost Cost = LT.first * CostFactor; 1439 assert(Cost.isValid() && "Expected valid cost"); 1440 1441 // On P9 but not on P10, if the op is misaligned then it will cause a 1442 // pipeline flush. Otherwise the VSX masked memops cost the same as unmasked 1443 // ones. 1444 const Align DesiredAlignment(16); 1445 if (Alignment >= DesiredAlignment || ST->getCPUDirective() != PPC::DIR_PWR9) 1446 return Cost; 1447 1448 // Since alignment may be under estimated, we try to compute the probability 1449 // that the actual address is aligned to the desired boundary. For example 1450 // an 8-byte aligned load is assumed to be actually 16-byte aligned half the 1451 // time, while a 4-byte aligned load has a 25% chance of being 16-byte 1452 // aligned. 1453 float AlignmentProb = ((float)Alignment.value()) / DesiredAlignment.value(); 1454 float MisalignmentProb = 1.0 - AlignmentProb; 1455 return (MisalignmentProb * P9PipelineFlushEstimate) + 1456 (AlignmentProb * *Cost.getValue()); 1457 } 1458 1459 // Usually we should not get to this point, but the following is an attempt to 1460 // model the cost of legalization. Currently we can only lower intrinsics with 1461 // evl but no mask, on Power 9/10. Otherwise, we must scalarize. 1462 return getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind); 1463 } 1464 1465 bool PPCTTIImpl::supportsTailCallFor(const CallBase *CB) const { 1466 // Subtargets using PC-Relative addressing supported. 1467 if (ST->isUsingPCRelativeCalls()) 1468 return true; 1469 1470 const Function *Callee = CB->getCalledFunction(); 1471 // Indirect calls and variadic argument functions not supported. 1472 if (!Callee || Callee->isVarArg()) 1473 return false; 1474 1475 const Function *Caller = CB->getCaller(); 1476 // Support if we can share TOC base. 1477 return ST->getTargetMachine().shouldAssumeDSOLocal(*Caller->getParent(), 1478 Callee); 1479 } 1480