1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "PPCTargetTransformInfo.h" 10 #include "llvm/Analysis/CodeMetrics.h" 11 #include "llvm/Analysis/TargetLibraryInfo.h" 12 #include "llvm/Analysis/TargetTransformInfo.h" 13 #include "llvm/CodeGen/BasicTTIImpl.h" 14 #include "llvm/CodeGen/CostTable.h" 15 #include "llvm/CodeGen/TargetLowering.h" 16 #include "llvm/CodeGen/TargetSchedule.h" 17 #include "llvm/IR/IntrinsicsPowerPC.h" 18 #include "llvm/Support/CommandLine.h" 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Transforms/InstCombine/InstCombiner.h" 21 #include "llvm/Transforms/Utils/Local.h" 22 23 using namespace llvm; 24 25 #define DEBUG_TYPE "ppctti" 26 27 static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting", 28 cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden); 29 30 // This is currently only used for the data prefetch pass 31 static cl::opt<unsigned> 32 CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64), 33 cl::desc("The loop prefetch cache line size")); 34 35 static cl::opt<bool> 36 EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false), 37 cl::desc("Enable using coldcc calling conv for cold " 38 "internal functions")); 39 40 static cl::opt<bool> 41 LsrNoInsnsCost("ppc-lsr-no-insns-cost", cl::Hidden, cl::init(false), 42 cl::desc("Do not add instruction count to lsr cost model")); 43 44 // The latency of mtctr is only justified if there are more than 4 45 // comparisons that will be removed as a result. 46 static cl::opt<unsigned> 47 SmallCTRLoopThreshold("min-ctr-loop-threshold", cl::init(4), cl::Hidden, 48 cl::desc("Loops with a constant trip count smaller than " 49 "this value will not use the count register.")); 50 51 //===----------------------------------------------------------------------===// 52 // 53 // PPC cost model. 54 // 55 //===----------------------------------------------------------------------===// 56 57 TargetTransformInfo::PopcntSupportKind 58 PPCTTIImpl::getPopcntSupport(unsigned TyWidth) { 59 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 60 if (ST->hasPOPCNTD() != PPCSubtarget::POPCNTD_Unavailable && TyWidth <= 64) 61 return ST->hasPOPCNTD() == PPCSubtarget::POPCNTD_Slow ? 62 TTI::PSK_SlowHardware : TTI::PSK_FastHardware; 63 return TTI::PSK_Software; 64 } 65 66 Optional<Instruction *> 67 PPCTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { 68 Intrinsic::ID IID = II.getIntrinsicID(); 69 switch (IID) { 70 default: 71 break; 72 case Intrinsic::ppc_altivec_lvx: 73 case Intrinsic::ppc_altivec_lvxl: 74 // Turn PPC lvx -> load if the pointer is known aligned. 75 if (getOrEnforceKnownAlignment( 76 II.getArgOperand(0), Align(16), IC.getDataLayout(), &II, 77 &IC.getAssumptionCache(), &IC.getDominatorTree()) >= 16) { 78 Value *Ptr = IC.Builder.CreateBitCast( 79 II.getArgOperand(0), PointerType::getUnqual(II.getType())); 80 return new LoadInst(II.getType(), Ptr, "", false, Align(16)); 81 } 82 break; 83 case Intrinsic::ppc_vsx_lxvw4x: 84 case Intrinsic::ppc_vsx_lxvd2x: { 85 // Turn PPC VSX loads into normal loads. 86 Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(0), 87 PointerType::getUnqual(II.getType())); 88 return new LoadInst(II.getType(), Ptr, Twine(""), false, Align(1)); 89 } 90 case Intrinsic::ppc_altivec_stvx: 91 case Intrinsic::ppc_altivec_stvxl: 92 // Turn stvx -> store if the pointer is known aligned. 93 if (getOrEnforceKnownAlignment( 94 II.getArgOperand(1), Align(16), IC.getDataLayout(), &II, 95 &IC.getAssumptionCache(), &IC.getDominatorTree()) >= 16) { 96 Type *OpPtrTy = PointerType::getUnqual(II.getArgOperand(0)->getType()); 97 Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(1), OpPtrTy); 98 return new StoreInst(II.getArgOperand(0), Ptr, false, Align(16)); 99 } 100 break; 101 case Intrinsic::ppc_vsx_stxvw4x: 102 case Intrinsic::ppc_vsx_stxvd2x: { 103 // Turn PPC VSX stores into normal stores. 104 Type *OpPtrTy = PointerType::getUnqual(II.getArgOperand(0)->getType()); 105 Value *Ptr = IC.Builder.CreateBitCast(II.getArgOperand(1), OpPtrTy); 106 return new StoreInst(II.getArgOperand(0), Ptr, false, Align(1)); 107 } 108 case Intrinsic::ppc_altivec_vperm: 109 // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant. 110 // Note that ppc_altivec_vperm has a big-endian bias, so when creating 111 // a vectorshuffle for little endian, we must undo the transformation 112 // performed on vec_perm in altivec.h. That is, we must complement 113 // the permutation mask with respect to 31 and reverse the order of 114 // V1 and V2. 115 if (Constant *Mask = dyn_cast<Constant>(II.getArgOperand(2))) { 116 assert(cast<VectorType>(Mask->getType())->getNumElements() == 16 && 117 "Bad type for intrinsic!"); 118 119 // Check that all of the elements are integer constants or undefs. 120 bool AllEltsOk = true; 121 for (unsigned i = 0; i != 16; ++i) { 122 Constant *Elt = Mask->getAggregateElement(i); 123 if (!Elt || !(isa<ConstantInt>(Elt) || isa<UndefValue>(Elt))) { 124 AllEltsOk = false; 125 break; 126 } 127 } 128 129 if (AllEltsOk) { 130 // Cast the input vectors to byte vectors. 131 Value *Op0 = 132 IC.Builder.CreateBitCast(II.getArgOperand(0), Mask->getType()); 133 Value *Op1 = 134 IC.Builder.CreateBitCast(II.getArgOperand(1), Mask->getType()); 135 Value *Result = UndefValue::get(Op0->getType()); 136 137 // Only extract each element once. 138 Value *ExtractedElts[32]; 139 memset(ExtractedElts, 0, sizeof(ExtractedElts)); 140 141 for (unsigned i = 0; i != 16; ++i) { 142 if (isa<UndefValue>(Mask->getAggregateElement(i))) 143 continue; 144 unsigned Idx = 145 cast<ConstantInt>(Mask->getAggregateElement(i))->getZExtValue(); 146 Idx &= 31; // Match the hardware behavior. 147 if (DL.isLittleEndian()) 148 Idx = 31 - Idx; 149 150 if (!ExtractedElts[Idx]) { 151 Value *Op0ToUse = (DL.isLittleEndian()) ? Op1 : Op0; 152 Value *Op1ToUse = (DL.isLittleEndian()) ? Op0 : Op1; 153 ExtractedElts[Idx] = IC.Builder.CreateExtractElement( 154 Idx < 16 ? Op0ToUse : Op1ToUse, IC.Builder.getInt32(Idx & 15)); 155 } 156 157 // Insert this value into the result vector. 158 Result = IC.Builder.CreateInsertElement(Result, ExtractedElts[Idx], 159 IC.Builder.getInt32(i)); 160 } 161 return CastInst::Create(Instruction::BitCast, Result, II.getType()); 162 } 163 } 164 break; 165 } 166 return None; 167 } 168 169 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 170 TTI::TargetCostKind CostKind) { 171 if (DisablePPCConstHoist) 172 return BaseT::getIntImmCost(Imm, Ty, CostKind); 173 174 assert(Ty->isIntegerTy()); 175 176 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 177 if (BitSize == 0) 178 return ~0U; 179 180 if (Imm == 0) 181 return TTI::TCC_Free; 182 183 if (Imm.getBitWidth() <= 64) { 184 if (isInt<16>(Imm.getSExtValue())) 185 return TTI::TCC_Basic; 186 187 if (isInt<32>(Imm.getSExtValue())) { 188 // A constant that can be materialized using lis. 189 if ((Imm.getZExtValue() & 0xFFFF) == 0) 190 return TTI::TCC_Basic; 191 192 return 2 * TTI::TCC_Basic; 193 } 194 } 195 196 return 4 * TTI::TCC_Basic; 197 } 198 199 int PPCTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 200 const APInt &Imm, Type *Ty, 201 TTI::TargetCostKind CostKind) { 202 if (DisablePPCConstHoist) 203 return BaseT::getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind); 204 205 assert(Ty->isIntegerTy()); 206 207 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 208 if (BitSize == 0) 209 return ~0U; 210 211 switch (IID) { 212 default: 213 return TTI::TCC_Free; 214 case Intrinsic::sadd_with_overflow: 215 case Intrinsic::uadd_with_overflow: 216 case Intrinsic::ssub_with_overflow: 217 case Intrinsic::usub_with_overflow: 218 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())) 219 return TTI::TCC_Free; 220 break; 221 case Intrinsic::experimental_stackmap: 222 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 223 return TTI::TCC_Free; 224 break; 225 case Intrinsic::experimental_patchpoint_void: 226 case Intrinsic::experimental_patchpoint_i64: 227 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 228 return TTI::TCC_Free; 229 break; 230 } 231 return PPCTTIImpl::getIntImmCost(Imm, Ty, CostKind); 232 } 233 234 int PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 235 const APInt &Imm, Type *Ty, 236 TTI::TargetCostKind CostKind) { 237 if (DisablePPCConstHoist) 238 return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind); 239 240 assert(Ty->isIntegerTy()); 241 242 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 243 if (BitSize == 0) 244 return ~0U; 245 246 unsigned ImmIdx = ~0U; 247 bool ShiftedFree = false, RunFree = false, UnsignedFree = false, 248 ZeroFree = false; 249 switch (Opcode) { 250 default: 251 return TTI::TCC_Free; 252 case Instruction::GetElementPtr: 253 // Always hoist the base address of a GetElementPtr. This prevents the 254 // creation of new constants for every base constant that gets constant 255 // folded with the offset. 256 if (Idx == 0) 257 return 2 * TTI::TCC_Basic; 258 return TTI::TCC_Free; 259 case Instruction::And: 260 RunFree = true; // (for the rotate-and-mask instructions) 261 LLVM_FALLTHROUGH; 262 case Instruction::Add: 263 case Instruction::Or: 264 case Instruction::Xor: 265 ShiftedFree = true; 266 LLVM_FALLTHROUGH; 267 case Instruction::Sub: 268 case Instruction::Mul: 269 case Instruction::Shl: 270 case Instruction::LShr: 271 case Instruction::AShr: 272 ImmIdx = 1; 273 break; 274 case Instruction::ICmp: 275 UnsignedFree = true; 276 ImmIdx = 1; 277 // Zero comparisons can use record-form instructions. 278 LLVM_FALLTHROUGH; 279 case Instruction::Select: 280 ZeroFree = true; 281 break; 282 case Instruction::PHI: 283 case Instruction::Call: 284 case Instruction::Ret: 285 case Instruction::Load: 286 case Instruction::Store: 287 break; 288 } 289 290 if (ZeroFree && Imm == 0) 291 return TTI::TCC_Free; 292 293 if (Idx == ImmIdx && Imm.getBitWidth() <= 64) { 294 if (isInt<16>(Imm.getSExtValue())) 295 return TTI::TCC_Free; 296 297 if (RunFree) { 298 if (Imm.getBitWidth() <= 32 && 299 (isShiftedMask_32(Imm.getZExtValue()) || 300 isShiftedMask_32(~Imm.getZExtValue()))) 301 return TTI::TCC_Free; 302 303 if (ST->isPPC64() && 304 (isShiftedMask_64(Imm.getZExtValue()) || 305 isShiftedMask_64(~Imm.getZExtValue()))) 306 return TTI::TCC_Free; 307 } 308 309 if (UnsignedFree && isUInt<16>(Imm.getZExtValue())) 310 return TTI::TCC_Free; 311 312 if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0) 313 return TTI::TCC_Free; 314 } 315 316 return PPCTTIImpl::getIntImmCost(Imm, Ty, CostKind); 317 } 318 319 unsigned 320 PPCTTIImpl::getUserCost(const User *U, ArrayRef<const Value *> Operands, 321 TTI::TargetCostKind CostKind) { 322 // We already implement getCastInstrCost and getMemoryOpCost where we perform 323 // the vector adjustment there. 324 if (isa<CastInst>(U) || isa<LoadInst>(U) || isa<StoreInst>(U)) 325 return BaseT::getUserCost(U, Operands, CostKind); 326 327 if (U->getType()->isVectorTy()) { 328 // Instructions that need to be split should cost more. 329 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, U->getType()); 330 return LT.first * BaseT::getUserCost(U, Operands, CostKind); 331 } 332 333 return BaseT::getUserCost(U, Operands, CostKind); 334 } 335 336 bool PPCTTIImpl::mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo, 337 SmallPtrSetImpl<const Value *> &Visited) { 338 const PPCTargetMachine &TM = ST->getTargetMachine(); 339 340 // Loop through the inline asm constraints and look for something that 341 // clobbers ctr. 342 auto asmClobbersCTR = [](InlineAsm *IA) { 343 InlineAsm::ConstraintInfoVector CIV = IA->ParseConstraints(); 344 for (unsigned i = 0, ie = CIV.size(); i < ie; ++i) { 345 InlineAsm::ConstraintInfo &C = CIV[i]; 346 if (C.Type != InlineAsm::isInput) 347 for (unsigned j = 0, je = C.Codes.size(); j < je; ++j) 348 if (StringRef(C.Codes[j]).equals_lower("{ctr}")) 349 return true; 350 } 351 return false; 352 }; 353 354 // Determining the address of a TLS variable results in a function call in 355 // certain TLS models. 356 std::function<bool(const Value *)> memAddrUsesCTR = 357 [&memAddrUsesCTR, &TM, &Visited](const Value *MemAddr) -> bool { 358 // No need to traverse again if we already checked this operand. 359 if (!Visited.insert(MemAddr).second) 360 return false; 361 const auto *GV = dyn_cast<GlobalValue>(MemAddr); 362 if (!GV) { 363 // Recurse to check for constants that refer to TLS global variables. 364 if (const auto *CV = dyn_cast<Constant>(MemAddr)) 365 for (const auto &CO : CV->operands()) 366 if (memAddrUsesCTR(CO)) 367 return true; 368 369 return false; 370 } 371 372 if (!GV->isThreadLocal()) 373 return false; 374 TLSModel::Model Model = TM.getTLSModel(GV); 375 return Model == TLSModel::GeneralDynamic || 376 Model == TLSModel::LocalDynamic; 377 }; 378 379 auto isLargeIntegerTy = [](bool Is32Bit, Type *Ty) { 380 if (IntegerType *ITy = dyn_cast<IntegerType>(Ty)) 381 return ITy->getBitWidth() > (Is32Bit ? 32U : 64U); 382 383 return false; 384 }; 385 386 for (BasicBlock::iterator J = BB->begin(), JE = BB->end(); 387 J != JE; ++J) { 388 if (CallInst *CI = dyn_cast<CallInst>(J)) { 389 // Inline ASM is okay, unless it clobbers the ctr register. 390 if (InlineAsm *IA = dyn_cast<InlineAsm>(CI->getCalledOperand())) { 391 if (asmClobbersCTR(IA)) 392 return true; 393 continue; 394 } 395 396 if (Function *F = CI->getCalledFunction()) { 397 // Most intrinsics don't become function calls, but some might. 398 // sin, cos, exp and log are always calls. 399 unsigned Opcode = 0; 400 if (F->getIntrinsicID() != Intrinsic::not_intrinsic) { 401 switch (F->getIntrinsicID()) { 402 default: continue; 403 // If we have a call to loop_decrement or set_loop_iterations, 404 // we're definitely using CTR. 405 case Intrinsic::set_loop_iterations: 406 case Intrinsic::loop_decrement: 407 return true; 408 409 // Exclude eh_sjlj_setjmp; we don't need to exclude eh_sjlj_longjmp 410 // because, although it does clobber the counter register, the 411 // control can't then return to inside the loop unless there is also 412 // an eh_sjlj_setjmp. 413 case Intrinsic::eh_sjlj_setjmp: 414 415 case Intrinsic::memcpy: 416 case Intrinsic::memmove: 417 case Intrinsic::memset: 418 case Intrinsic::powi: 419 case Intrinsic::log: 420 case Intrinsic::log2: 421 case Intrinsic::log10: 422 case Intrinsic::exp: 423 case Intrinsic::exp2: 424 case Intrinsic::pow: 425 case Intrinsic::sin: 426 case Intrinsic::cos: 427 return true; 428 case Intrinsic::copysign: 429 if (CI->getArgOperand(0)->getType()->getScalarType()-> 430 isPPC_FP128Ty()) 431 return true; 432 else 433 continue; // ISD::FCOPYSIGN is never a library call. 434 case Intrinsic::fma: Opcode = ISD::FMA; break; 435 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 436 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 437 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 438 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 439 case Intrinsic::rint: Opcode = ISD::FRINT; break; 440 case Intrinsic::lrint: Opcode = ISD::LRINT; break; 441 case Intrinsic::llrint: Opcode = ISD::LLRINT; break; 442 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; 443 case Intrinsic::round: Opcode = ISD::FROUND; break; 444 case Intrinsic::lround: Opcode = ISD::LROUND; break; 445 case Intrinsic::llround: Opcode = ISD::LLROUND; break; 446 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; 447 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; 448 case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break; 449 case Intrinsic::smul_with_overflow: Opcode = ISD::SMULO; break; 450 } 451 } 452 453 // PowerPC does not use [US]DIVREM or other library calls for 454 // operations on regular types which are not otherwise library calls 455 // (i.e. soft float or atomics). If adapting for targets that do, 456 // additional care is required here. 457 458 LibFunc Func; 459 if (!F->hasLocalLinkage() && F->hasName() && LibInfo && 460 LibInfo->getLibFunc(F->getName(), Func) && 461 LibInfo->hasOptimizedCodeGen(Func)) { 462 // Non-read-only functions are never treated as intrinsics. 463 if (!CI->onlyReadsMemory()) 464 return true; 465 466 // Conversion happens only for FP calls. 467 if (!CI->getArgOperand(0)->getType()->isFloatingPointTy()) 468 return true; 469 470 switch (Func) { 471 default: return true; 472 case LibFunc_copysign: 473 case LibFunc_copysignf: 474 continue; // ISD::FCOPYSIGN is never a library call. 475 case LibFunc_copysignl: 476 return true; 477 case LibFunc_fabs: 478 case LibFunc_fabsf: 479 case LibFunc_fabsl: 480 continue; // ISD::FABS is never a library call. 481 case LibFunc_sqrt: 482 case LibFunc_sqrtf: 483 case LibFunc_sqrtl: 484 Opcode = ISD::FSQRT; break; 485 case LibFunc_floor: 486 case LibFunc_floorf: 487 case LibFunc_floorl: 488 Opcode = ISD::FFLOOR; break; 489 case LibFunc_nearbyint: 490 case LibFunc_nearbyintf: 491 case LibFunc_nearbyintl: 492 Opcode = ISD::FNEARBYINT; break; 493 case LibFunc_ceil: 494 case LibFunc_ceilf: 495 case LibFunc_ceill: 496 Opcode = ISD::FCEIL; break; 497 case LibFunc_rint: 498 case LibFunc_rintf: 499 case LibFunc_rintl: 500 Opcode = ISD::FRINT; break; 501 case LibFunc_round: 502 case LibFunc_roundf: 503 case LibFunc_roundl: 504 Opcode = ISD::FROUND; break; 505 case LibFunc_trunc: 506 case LibFunc_truncf: 507 case LibFunc_truncl: 508 Opcode = ISD::FTRUNC; break; 509 case LibFunc_fmin: 510 case LibFunc_fminf: 511 case LibFunc_fminl: 512 Opcode = ISD::FMINNUM; break; 513 case LibFunc_fmax: 514 case LibFunc_fmaxf: 515 case LibFunc_fmaxl: 516 Opcode = ISD::FMAXNUM; break; 517 } 518 } 519 520 if (Opcode) { 521 EVT EVTy = 522 TLI->getValueType(DL, CI->getArgOperand(0)->getType(), true); 523 524 if (EVTy == MVT::Other) 525 return true; 526 527 if (TLI->isOperationLegalOrCustom(Opcode, EVTy)) 528 continue; 529 else if (EVTy.isVector() && 530 TLI->isOperationLegalOrCustom(Opcode, EVTy.getScalarType())) 531 continue; 532 533 return true; 534 } 535 } 536 537 return true; 538 } else if (isa<BinaryOperator>(J) && 539 (J->getType()->getScalarType()->isFP128Ty() || 540 J->getType()->getScalarType()->isPPC_FP128Ty())) { 541 // Most operations on f128 or ppc_f128 values become calls. 542 return true; 543 } else if (isa<UIToFPInst>(J) || isa<SIToFPInst>(J) || 544 isa<FPToUIInst>(J) || isa<FPToSIInst>(J)) { 545 CastInst *CI = cast<CastInst>(J); 546 if (CI->getSrcTy()->getScalarType()->isPPC_FP128Ty() || 547 CI->getDestTy()->getScalarType()->isPPC_FP128Ty() || 548 isLargeIntegerTy(!TM.isPPC64(), CI->getSrcTy()->getScalarType()) || 549 isLargeIntegerTy(!TM.isPPC64(), CI->getDestTy()->getScalarType())) 550 return true; 551 } else if (isLargeIntegerTy(!TM.isPPC64(), 552 J->getType()->getScalarType()) && 553 (J->getOpcode() == Instruction::UDiv || 554 J->getOpcode() == Instruction::SDiv || 555 J->getOpcode() == Instruction::URem || 556 J->getOpcode() == Instruction::SRem)) { 557 return true; 558 } else if (!TM.isPPC64() && 559 isLargeIntegerTy(false, J->getType()->getScalarType()) && 560 (J->getOpcode() == Instruction::Shl || 561 J->getOpcode() == Instruction::AShr || 562 J->getOpcode() == Instruction::LShr)) { 563 // Only on PPC32, for 128-bit integers (specifically not 64-bit 564 // integers), these might be runtime calls. 565 return true; 566 } else if (isa<IndirectBrInst>(J) || isa<InvokeInst>(J)) { 567 // On PowerPC, indirect jumps use the counter register. 568 return true; 569 } else if (SwitchInst *SI = dyn_cast<SwitchInst>(J)) { 570 if (SI->getNumCases() + 1 >= (unsigned)TLI->getMinimumJumpTableEntries()) 571 return true; 572 } 573 574 // FREM is always a call. 575 if (J->getOpcode() == Instruction::FRem) 576 return true; 577 578 if (ST->useSoftFloat()) { 579 switch(J->getOpcode()) { 580 case Instruction::FAdd: 581 case Instruction::FSub: 582 case Instruction::FMul: 583 case Instruction::FDiv: 584 case Instruction::FPTrunc: 585 case Instruction::FPExt: 586 case Instruction::FPToUI: 587 case Instruction::FPToSI: 588 case Instruction::UIToFP: 589 case Instruction::SIToFP: 590 case Instruction::FCmp: 591 return true; 592 } 593 } 594 595 for (Value *Operand : J->operands()) 596 if (memAddrUsesCTR(Operand)) 597 return true; 598 } 599 600 return false; 601 } 602 603 bool PPCTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, 604 AssumptionCache &AC, 605 TargetLibraryInfo *LibInfo, 606 HardwareLoopInfo &HWLoopInfo) { 607 const PPCTargetMachine &TM = ST->getTargetMachine(); 608 TargetSchedModel SchedModel; 609 SchedModel.init(ST); 610 611 // Do not convert small short loops to CTR loop. 612 unsigned ConstTripCount = SE.getSmallConstantTripCount(L); 613 if (ConstTripCount && ConstTripCount < SmallCTRLoopThreshold) { 614 SmallPtrSet<const Value *, 32> EphValues; 615 CodeMetrics::collectEphemeralValues(L, &AC, EphValues); 616 CodeMetrics Metrics; 617 for (BasicBlock *BB : L->blocks()) 618 Metrics.analyzeBasicBlock(BB, *this, EphValues); 619 // 6 is an approximate latency for the mtctr instruction. 620 if (Metrics.NumInsts <= (6 * SchedModel.getIssueWidth())) 621 return false; 622 } 623 624 // We don't want to spill/restore the counter register, and so we don't 625 // want to use the counter register if the loop contains calls. 626 SmallPtrSet<const Value *, 4> Visited; 627 for (Loop::block_iterator I = L->block_begin(), IE = L->block_end(); 628 I != IE; ++I) 629 if (mightUseCTR(*I, LibInfo, Visited)) 630 return false; 631 632 SmallVector<BasicBlock*, 4> ExitingBlocks; 633 L->getExitingBlocks(ExitingBlocks); 634 635 // If there is an exit edge known to be frequently taken, 636 // we should not transform this loop. 637 for (auto &BB : ExitingBlocks) { 638 Instruction *TI = BB->getTerminator(); 639 if (!TI) continue; 640 641 if (BranchInst *BI = dyn_cast<BranchInst>(TI)) { 642 uint64_t TrueWeight = 0, FalseWeight = 0; 643 if (!BI->isConditional() || 644 !BI->extractProfMetadata(TrueWeight, FalseWeight)) 645 continue; 646 647 // If the exit path is more frequent than the loop path, 648 // we return here without further analysis for this loop. 649 bool TrueIsExit = !L->contains(BI->getSuccessor(0)); 650 if (( TrueIsExit && FalseWeight < TrueWeight) || 651 (!TrueIsExit && FalseWeight > TrueWeight)) 652 return false; 653 } 654 } 655 656 LLVMContext &C = L->getHeader()->getContext(); 657 HWLoopInfo.CountType = TM.isPPC64() ? 658 Type::getInt64Ty(C) : Type::getInt32Ty(C); 659 HWLoopInfo.LoopDecrement = ConstantInt::get(HWLoopInfo.CountType, 1); 660 return true; 661 } 662 663 void PPCTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, 664 TTI::UnrollingPreferences &UP) { 665 if (ST->getCPUDirective() == PPC::DIR_A2) { 666 // The A2 is in-order with a deep pipeline, and concatenation unrolling 667 // helps expose latency-hiding opportunities to the instruction scheduler. 668 UP.Partial = UP.Runtime = true; 669 670 // We unroll a lot on the A2 (hundreds of instructions), and the benefits 671 // often outweigh the cost of a division to compute the trip count. 672 UP.AllowExpensiveTripCount = true; 673 } 674 675 BaseT::getUnrollingPreferences(L, SE, UP); 676 } 677 678 void PPCTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE, 679 TTI::PeelingPreferences &PP) { 680 BaseT::getPeelingPreferences(L, SE, PP); 681 } 682 // This function returns true to allow using coldcc calling convention. 683 // Returning true results in coldcc being used for functions which are cold at 684 // all call sites when the callers of the functions are not calling any other 685 // non coldcc functions. 686 bool PPCTTIImpl::useColdCCForColdCall(Function &F) { 687 return EnablePPCColdCC; 688 } 689 690 bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) { 691 // On the A2, always unroll aggressively. 692 if (ST->getCPUDirective() == PPC::DIR_A2) 693 return true; 694 695 return LoopHasReductions; 696 } 697 698 PPCTTIImpl::TTI::MemCmpExpansionOptions 699 PPCTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 700 TTI::MemCmpExpansionOptions Options; 701 Options.LoadSizes = {8, 4, 2, 1}; 702 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 703 return Options; 704 } 705 706 bool PPCTTIImpl::enableInterleavedAccessVectorization() { 707 return true; 708 } 709 710 unsigned PPCTTIImpl::getNumberOfRegisters(unsigned ClassID) const { 711 assert(ClassID == GPRRC || ClassID == FPRRC || 712 ClassID == VRRC || ClassID == VSXRC); 713 if (ST->hasVSX()) { 714 assert(ClassID == GPRRC || ClassID == VSXRC || ClassID == VRRC); 715 return ClassID == VSXRC ? 64 : 32; 716 } 717 assert(ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC); 718 return 32; 719 } 720 721 unsigned PPCTTIImpl::getRegisterClassForType(bool Vector, Type *Ty) const { 722 if (Vector) 723 return ST->hasVSX() ? VSXRC : VRRC; 724 else if (Ty && (Ty->getScalarType()->isFloatTy() || 725 Ty->getScalarType()->isDoubleTy())) 726 return ST->hasVSX() ? VSXRC : FPRRC; 727 else if (Ty && (Ty->getScalarType()->isFP128Ty() || 728 Ty->getScalarType()->isPPC_FP128Ty())) 729 return VRRC; 730 else if (Ty && Ty->getScalarType()->isHalfTy()) 731 return VSXRC; 732 else 733 return GPRRC; 734 } 735 736 const char* PPCTTIImpl::getRegisterClassName(unsigned ClassID) const { 737 738 switch (ClassID) { 739 default: 740 llvm_unreachable("unknown register class"); 741 return "PPC::unknown register class"; 742 case GPRRC: return "PPC::GPRRC"; 743 case FPRRC: return "PPC::FPRRC"; 744 case VRRC: return "PPC::VRRC"; 745 case VSXRC: return "PPC::VSXRC"; 746 } 747 } 748 749 unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) const { 750 if (Vector) { 751 if (ST->hasAltivec()) return 128; 752 return 0; 753 } 754 755 if (ST->isPPC64()) 756 return 64; 757 return 32; 758 759 } 760 761 unsigned PPCTTIImpl::getCacheLineSize() const { 762 // Check first if the user specified a custom line size. 763 if (CacheLineSize.getNumOccurrences() > 0) 764 return CacheLineSize; 765 766 // Starting with P7 we have a cache line size of 128. 767 unsigned Directive = ST->getCPUDirective(); 768 // Assume that Future CPU has the same cache line size as the others. 769 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 || 770 Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 || 771 Directive == PPC::DIR_PWR_FUTURE) 772 return 128; 773 774 // On other processors return a default of 64 bytes. 775 return 64; 776 } 777 778 unsigned PPCTTIImpl::getPrefetchDistance() const { 779 return 300; 780 } 781 782 unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) { 783 unsigned Directive = ST->getCPUDirective(); 784 // The 440 has no SIMD support, but floating-point instructions 785 // have a 5-cycle latency, so unroll by 5x for latency hiding. 786 if (Directive == PPC::DIR_440) 787 return 5; 788 789 // The A2 has no SIMD support, but floating-point instructions 790 // have a 6-cycle latency, so unroll by 6x for latency hiding. 791 if (Directive == PPC::DIR_A2) 792 return 6; 793 794 // FIXME: For lack of any better information, do no harm... 795 if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) 796 return 1; 797 798 // For P7 and P8, floating-point instructions have a 6-cycle latency and 799 // there are two execution units, so unroll by 12x for latency hiding. 800 // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready 801 // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready 802 // Assume that future is the same as the others. 803 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 || 804 Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 || 805 Directive == PPC::DIR_PWR_FUTURE) 806 return 12; 807 808 // For most things, modern systems have two execution units (and 809 // out-of-order execution). 810 return 2; 811 } 812 813 // Adjust the cost of vector instructions on targets which there is overlap 814 // between the vector and scalar units, thereby reducing the overall throughput 815 // of vector code wrt. scalar code. 816 int PPCTTIImpl::vectorCostAdjustment(int Cost, unsigned Opcode, Type *Ty1, 817 Type *Ty2) { 818 if (!ST->vectorsUseTwoUnits() || !Ty1->isVectorTy()) 819 return Cost; 820 821 std::pair<int, MVT> LT1 = TLI->getTypeLegalizationCost(DL, Ty1); 822 // If type legalization involves splitting the vector, we don't want to 823 // double the cost at every step - only the last step. 824 if (LT1.first != 1 || !LT1.second.isVector()) 825 return Cost; 826 827 int ISD = TLI->InstructionOpcodeToISD(Opcode); 828 if (TLI->isOperationExpand(ISD, LT1.second)) 829 return Cost; 830 831 if (Ty2) { 832 std::pair<int, MVT> LT2 = TLI->getTypeLegalizationCost(DL, Ty2); 833 if (LT2.first != 1 || !LT2.second.isVector()) 834 return Cost; 835 } 836 837 return Cost * 2; 838 } 839 840 int PPCTTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 841 TTI::TargetCostKind CostKind, 842 TTI::OperandValueKind Op1Info, 843 TTI::OperandValueKind Op2Info, 844 TTI::OperandValueProperties Opd1PropInfo, 845 TTI::OperandValueProperties Opd2PropInfo, 846 ArrayRef<const Value *> Args, 847 const Instruction *CxtI) { 848 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); 849 // TODO: Handle more cost kinds. 850 if (CostKind != TTI::TCK_RecipThroughput) 851 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 852 Op2Info, Opd1PropInfo, 853 Opd2PropInfo, Args, CxtI); 854 855 // Fallback to the default implementation. 856 int Cost = BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 857 Op2Info, 858 Opd1PropInfo, Opd2PropInfo); 859 return vectorCostAdjustment(Cost, Opcode, Ty, nullptr); 860 } 861 862 int PPCTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 863 Type *SubTp) { 864 // Legalize the type. 865 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 866 867 // PPC, for both Altivec/VSX, support cheap arbitrary permutations 868 // (at least in the sense that there need only be one non-loop-invariant 869 // instruction). We need one such shuffle instruction for each actual 870 // register (this is not true for arbitrary shuffles, but is true for the 871 // structured types of shuffles covered by TTI::ShuffleKind). 872 return vectorCostAdjustment(LT.first, Instruction::ShuffleVector, Tp, 873 nullptr); 874 } 875 876 int PPCTTIImpl::getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind) { 877 if (CostKind != TTI::TCK_RecipThroughput) 878 return Opcode == Instruction::PHI ? 0 : 1; 879 // Branches are assumed to be predicted. 880 return CostKind == TTI::TCK_RecipThroughput ? 0 : 1; 881 } 882 883 int PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 884 TTI::CastContextHint CCH, 885 TTI::TargetCostKind CostKind, 886 const Instruction *I) { 887 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); 888 889 int Cost = BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); 890 Cost = vectorCostAdjustment(Cost, Opcode, Dst, Src); 891 // TODO: Allow non-throughput costs that aren't binary. 892 if (CostKind != TTI::TCK_RecipThroughput) 893 return Cost == 0 ? 0 : 1; 894 return Cost; 895 } 896 897 int PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 898 TTI::TargetCostKind CostKind, 899 const Instruction *I) { 900 int Cost = BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, CostKind, I); 901 // TODO: Handle other cost kinds. 902 if (CostKind != TTI::TCK_RecipThroughput) 903 return Cost; 904 return vectorCostAdjustment(Cost, Opcode, ValTy, nullptr); 905 } 906 907 int PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 908 assert(Val->isVectorTy() && "This must be a vector type"); 909 910 int ISD = TLI->InstructionOpcodeToISD(Opcode); 911 assert(ISD && "Invalid opcode"); 912 913 int Cost = BaseT::getVectorInstrCost(Opcode, Val, Index); 914 Cost = vectorCostAdjustment(Cost, Opcode, Val, nullptr); 915 916 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) { 917 // Double-precision scalars are already located in index #0 (or #1 if LE). 918 if (ISD == ISD::EXTRACT_VECTOR_ELT && 919 Index == (ST->isLittleEndian() ? 1 : 0)) 920 return 0; 921 922 return Cost; 923 924 } else if (Val->getScalarType()->isIntegerTy() && Index != -1U) { 925 if (ST->hasP9Altivec()) { 926 if (ISD == ISD::INSERT_VECTOR_ELT) 927 // A move-to VSR and a permute/insert. Assume vector operation cost 928 // for both (cost will be 2x on P9). 929 return vectorCostAdjustment(2, Opcode, Val, nullptr); 930 931 // It's an extract. Maybe we can do a cheap move-from VSR. 932 unsigned EltSize = Val->getScalarSizeInBits(); 933 if (EltSize == 64) { 934 unsigned MfvsrdIndex = ST->isLittleEndian() ? 1 : 0; 935 if (Index == MfvsrdIndex) 936 return 1; 937 } else if (EltSize == 32) { 938 unsigned MfvsrwzIndex = ST->isLittleEndian() ? 2 : 1; 939 if (Index == MfvsrwzIndex) 940 return 1; 941 } 942 943 // We need a vector extract (or mfvsrld). Assume vector operation cost. 944 // The cost of the load constant for a vector extract is disregarded 945 // (invariant, easily schedulable). 946 return vectorCostAdjustment(1, Opcode, Val, nullptr); 947 948 } else if (ST->hasDirectMove()) 949 // Assume permute has standard cost. 950 // Assume move-to/move-from VSR have 2x standard cost. 951 return 3; 952 } 953 954 // Estimated cost of a load-hit-store delay. This was obtained 955 // experimentally as a minimum needed to prevent unprofitable 956 // vectorization for the paq8p benchmark. It may need to be 957 // raised further if other unprofitable cases remain. 958 unsigned LHSPenalty = 2; 959 if (ISD == ISD::INSERT_VECTOR_ELT) 960 LHSPenalty += 7; 961 962 // Vector element insert/extract with Altivec is very expensive, 963 // because they require store and reload with the attendant 964 // processor stall for load-hit-store. Until VSX is available, 965 // these need to be estimated as very costly. 966 if (ISD == ISD::EXTRACT_VECTOR_ELT || 967 ISD == ISD::INSERT_VECTOR_ELT) 968 return LHSPenalty + Cost; 969 970 return Cost; 971 } 972 973 int PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 974 MaybeAlign Alignment, unsigned AddressSpace, 975 TTI::TargetCostKind CostKind, 976 const Instruction *I) { 977 if (TLI->getValueType(DL, Src, true) == MVT::Other) 978 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 979 CostKind); 980 // Legalize the type. 981 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 982 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 983 "Invalid Opcode"); 984 985 int Cost = BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 986 CostKind); 987 // TODO: Handle other cost kinds. 988 if (CostKind != TTI::TCK_RecipThroughput) 989 return Cost; 990 991 Cost = vectorCostAdjustment(Cost, Opcode, Src, nullptr); 992 993 bool IsAltivecType = ST->hasAltivec() && 994 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 || 995 LT.second == MVT::v4i32 || LT.second == MVT::v4f32); 996 bool IsVSXType = ST->hasVSX() && 997 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64); 998 999 // VSX has 32b/64b load instructions. Legalization can handle loading of 1000 // 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and 1001 // PPCTargetLowering can't compute the cost appropriately. So here we 1002 // explicitly check this case. 1003 unsigned MemBytes = Src->getPrimitiveSizeInBits(); 1004 if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType && 1005 (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32))) 1006 return 1; 1007 1008 // Aligned loads and stores are easy. 1009 unsigned SrcBytes = LT.second.getStoreSize(); 1010 if (!SrcBytes || !Alignment || *Alignment >= SrcBytes) 1011 return Cost; 1012 1013 // If we can use the permutation-based load sequence, then this is also 1014 // relatively cheap (not counting loop-invariant instructions): one load plus 1015 // one permute (the last load in a series has extra cost, but we're 1016 // neglecting that here). Note that on the P7, we could do unaligned loads 1017 // for Altivec types using the VSX instructions, but that's more expensive 1018 // than using the permutation-based load sequence. On the P8, that's no 1019 // longer true. 1020 if (Opcode == Instruction::Load && (!ST->hasP8Vector() && IsAltivecType) && 1021 *Alignment >= LT.second.getScalarType().getStoreSize()) 1022 return Cost + LT.first; // Add the cost of the permutations. 1023 1024 // For VSX, we can do unaligned loads and stores on Altivec/VSX types. On the 1025 // P7, unaligned vector loads are more expensive than the permutation-based 1026 // load sequence, so that might be used instead, but regardless, the net cost 1027 // is about the same (not counting loop-invariant instructions). 1028 if (IsVSXType || (ST->hasVSX() && IsAltivecType)) 1029 return Cost; 1030 1031 // Newer PPC supports unaligned memory access. 1032 if (TLI->allowsMisalignedMemoryAccesses(LT.second, 0)) 1033 return Cost; 1034 1035 // PPC in general does not support unaligned loads and stores. They'll need 1036 // to be decomposed based on the alignment factor. 1037 1038 // Add the cost of each scalar load or store. 1039 assert(Alignment); 1040 Cost += LT.first * ((SrcBytes / Alignment->value()) - 1); 1041 1042 // For a vector type, there is also scalarization overhead (only for 1043 // stores, loads are expanded using the vector-load + permutation sequence, 1044 // which is much less expensive). 1045 if (Src->isVectorTy() && Opcode == Instruction::Store) 1046 for (int i = 0, e = cast<FixedVectorType>(Src)->getNumElements(); i < e; 1047 ++i) 1048 Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i); 1049 1050 return Cost; 1051 } 1052 1053 int PPCTTIImpl::getInterleavedMemoryOpCost( 1054 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 1055 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 1056 bool UseMaskForCond, bool UseMaskForGaps) { 1057 if (UseMaskForCond || UseMaskForGaps) 1058 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 1059 Alignment, AddressSpace, CostKind, 1060 UseMaskForCond, UseMaskForGaps); 1061 1062 assert(isa<VectorType>(VecTy) && 1063 "Expect a vector type for interleaved memory op"); 1064 1065 // Legalize the type. 1066 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, VecTy); 1067 1068 // Firstly, the cost of load/store operation. 1069 int Cost = 1070 getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, 1071 CostKind); 1072 1073 // PPC, for both Altivec/VSX, support cheap arbitrary permutations 1074 // (at least in the sense that there need only be one non-loop-invariant 1075 // instruction). For each result vector, we need one shuffle per incoming 1076 // vector (except that the first shuffle can take two incoming vectors 1077 // because it does not need to take itself). 1078 Cost += Factor*(LT.first-1); 1079 1080 return Cost; 1081 } 1082 1083 unsigned PPCTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 1084 TTI::TargetCostKind CostKind) { 1085 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 1086 } 1087 1088 bool PPCTTIImpl::canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, 1089 LoopInfo *LI, DominatorTree *DT, 1090 AssumptionCache *AC, TargetLibraryInfo *LibInfo) { 1091 // Process nested loops first. 1092 for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I) 1093 if (canSaveCmp(*I, BI, SE, LI, DT, AC, LibInfo)) 1094 return false; // Stop search. 1095 1096 HardwareLoopInfo HWLoopInfo(L); 1097 1098 if (!HWLoopInfo.canAnalyze(*LI)) 1099 return false; 1100 1101 if (!isHardwareLoopProfitable(L, *SE, *AC, LibInfo, HWLoopInfo)) 1102 return false; 1103 1104 if (!HWLoopInfo.isHardwareLoopCandidate(*SE, *LI, *DT)) 1105 return false; 1106 1107 *BI = HWLoopInfo.ExitBranch; 1108 return true; 1109 } 1110 1111 bool PPCTTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 1112 TargetTransformInfo::LSRCost &C2) { 1113 // PowerPC default behaviour here is "instruction number 1st priority". 1114 // If LsrNoInsnsCost is set, call default implementation. 1115 if (!LsrNoInsnsCost) 1116 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, 1117 C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 1118 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, 1119 C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost); 1120 else 1121 return TargetTransformInfoImplBase::isLSRCostLess(C1, C2); 1122 } 1123