1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "PPCTargetTransformInfo.h" 11 #include "llvm/Analysis/TargetTransformInfo.h" 12 #include "llvm/CodeGen/BasicTTIImpl.h" 13 #include "llvm/Support/CommandLine.h" 14 #include "llvm/Support/Debug.h" 15 #include "llvm/Target/CostTable.h" 16 #include "llvm/Target/TargetLowering.h" 17 using namespace llvm; 18 19 #define DEBUG_TYPE "ppctti" 20 21 static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting", 22 cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden); 23 24 //===----------------------------------------------------------------------===// 25 // 26 // PPC cost model. 27 // 28 //===----------------------------------------------------------------------===// 29 30 TargetTransformInfo::PopcntSupportKind 31 PPCTTIImpl::getPopcntSupport(unsigned TyWidth) { 32 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 33 if (ST->hasPOPCNTD() && TyWidth <= 64) 34 return TTI::PSK_FastHardware; 35 return TTI::PSK_Software; 36 } 37 38 unsigned PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 39 if (DisablePPCConstHoist) 40 return BaseT::getIntImmCost(Imm, Ty); 41 42 assert(Ty->isIntegerTy()); 43 44 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 45 if (BitSize == 0) 46 return ~0U; 47 48 if (Imm == 0) 49 return TTI::TCC_Free; 50 51 if (Imm.getBitWidth() <= 64) { 52 if (isInt<16>(Imm.getSExtValue())) 53 return TTI::TCC_Basic; 54 55 if (isInt<32>(Imm.getSExtValue())) { 56 // A constant that can be materialized using lis. 57 if ((Imm.getZExtValue() & 0xFFFF) == 0) 58 return TTI::TCC_Basic; 59 60 return 2 * TTI::TCC_Basic; 61 } 62 } 63 64 return 4 * TTI::TCC_Basic; 65 } 66 67 unsigned PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, 68 const APInt &Imm, Type *Ty) { 69 if (DisablePPCConstHoist) 70 return BaseT::getIntImmCost(IID, Idx, Imm, Ty); 71 72 assert(Ty->isIntegerTy()); 73 74 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 75 if (BitSize == 0) 76 return ~0U; 77 78 switch (IID) { 79 default: 80 return TTI::TCC_Free; 81 case Intrinsic::sadd_with_overflow: 82 case Intrinsic::uadd_with_overflow: 83 case Intrinsic::ssub_with_overflow: 84 case Intrinsic::usub_with_overflow: 85 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())) 86 return TTI::TCC_Free; 87 break; 88 case Intrinsic::experimental_stackmap: 89 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 90 return TTI::TCC_Free; 91 break; 92 case Intrinsic::experimental_patchpoint_void: 93 case Intrinsic::experimental_patchpoint_i64: 94 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 95 return TTI::TCC_Free; 96 break; 97 } 98 return PPCTTIImpl::getIntImmCost(Imm, Ty); 99 } 100 101 unsigned PPCTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, 102 const APInt &Imm, Type *Ty) { 103 if (DisablePPCConstHoist) 104 return BaseT::getIntImmCost(Opcode, Idx, Imm, Ty); 105 106 assert(Ty->isIntegerTy()); 107 108 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 109 if (BitSize == 0) 110 return ~0U; 111 112 unsigned ImmIdx = ~0U; 113 bool ShiftedFree = false, RunFree = false, UnsignedFree = false, 114 ZeroFree = false; 115 switch (Opcode) { 116 default: 117 return TTI::TCC_Free; 118 case Instruction::GetElementPtr: 119 // Always hoist the base address of a GetElementPtr. This prevents the 120 // creation of new constants for every base constant that gets constant 121 // folded with the offset. 122 if (Idx == 0) 123 return 2 * TTI::TCC_Basic; 124 return TTI::TCC_Free; 125 case Instruction::And: 126 RunFree = true; // (for the rotate-and-mask instructions) 127 // Fallthrough... 128 case Instruction::Add: 129 case Instruction::Or: 130 case Instruction::Xor: 131 ShiftedFree = true; 132 // Fallthrough... 133 case Instruction::Sub: 134 case Instruction::Mul: 135 case Instruction::Shl: 136 case Instruction::LShr: 137 case Instruction::AShr: 138 ImmIdx = 1; 139 break; 140 case Instruction::ICmp: 141 UnsignedFree = true; 142 ImmIdx = 1; 143 // Fallthrough... (zero comparisons can use record-form instructions) 144 case Instruction::Select: 145 ZeroFree = true; 146 break; 147 case Instruction::PHI: 148 case Instruction::Call: 149 case Instruction::Ret: 150 case Instruction::Load: 151 case Instruction::Store: 152 break; 153 } 154 155 if (ZeroFree && Imm == 0) 156 return TTI::TCC_Free; 157 158 if (Idx == ImmIdx && Imm.getBitWidth() <= 64) { 159 if (isInt<16>(Imm.getSExtValue())) 160 return TTI::TCC_Free; 161 162 if (RunFree) { 163 if (Imm.getBitWidth() <= 32 && 164 (isShiftedMask_32(Imm.getZExtValue()) || 165 isShiftedMask_32(~Imm.getZExtValue()))) 166 return TTI::TCC_Free; 167 168 if (ST->isPPC64() && 169 (isShiftedMask_64(Imm.getZExtValue()) || 170 isShiftedMask_64(~Imm.getZExtValue()))) 171 return TTI::TCC_Free; 172 } 173 174 if (UnsignedFree && isUInt<16>(Imm.getZExtValue())) 175 return TTI::TCC_Free; 176 177 if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0) 178 return TTI::TCC_Free; 179 } 180 181 return PPCTTIImpl::getIntImmCost(Imm, Ty); 182 } 183 184 void PPCTTIImpl::getUnrollingPreferences(Loop *L, 185 TTI::UnrollingPreferences &UP) { 186 if (ST->getDarwinDirective() == PPC::DIR_A2) { 187 // The A2 is in-order with a deep pipeline, and concatenation unrolling 188 // helps expose latency-hiding opportunities to the instruction scheduler. 189 UP.Partial = UP.Runtime = true; 190 } 191 192 BaseT::getUnrollingPreferences(L, UP); 193 } 194 195 unsigned PPCTTIImpl::getNumberOfRegisters(bool Vector) { 196 if (Vector && !ST->hasAltivec()) 197 return 0; 198 return ST->hasVSX() ? 64 : 32; 199 } 200 201 unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) { 202 if (Vector) { 203 if (ST->hasAltivec()) return 128; 204 return 0; 205 } 206 207 if (ST->isPPC64()) 208 return 64; 209 return 32; 210 211 } 212 213 unsigned PPCTTIImpl::getMaxInterleaveFactor() { 214 unsigned Directive = ST->getDarwinDirective(); 215 // The 440 has no SIMD support, but floating-point instructions 216 // have a 5-cycle latency, so unroll by 5x for latency hiding. 217 if (Directive == PPC::DIR_440) 218 return 5; 219 220 // The A2 has no SIMD support, but floating-point instructions 221 // have a 6-cycle latency, so unroll by 6x for latency hiding. 222 if (Directive == PPC::DIR_A2) 223 return 6; 224 225 // FIXME: For lack of any better information, do no harm... 226 if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) 227 return 1; 228 229 // For most things, modern systems have two execution units (and 230 // out-of-order execution). 231 return 2; 232 } 233 234 unsigned PPCTTIImpl::getArithmeticInstrCost( 235 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, 236 TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo, 237 TTI::OperandValueProperties Opd2PropInfo) { 238 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); 239 240 // Fallback to the default implementation. 241 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info, 242 Opd1PropInfo, Opd2PropInfo); 243 } 244 245 unsigned PPCTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 246 Type *SubTp) { 247 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 248 } 249 250 unsigned PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { 251 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); 252 253 return BaseT::getCastInstrCost(Opcode, Dst, Src); 254 } 255 256 unsigned PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 257 Type *CondTy) { 258 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy); 259 } 260 261 unsigned PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 262 unsigned Index) { 263 assert(Val->isVectorTy() && "This must be a vector type"); 264 265 int ISD = TLI->InstructionOpcodeToISD(Opcode); 266 assert(ISD && "Invalid opcode"); 267 268 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) { 269 // Double-precision scalars are already located in index #0. 270 if (Index == 0) 271 return 0; 272 273 return BaseT::getVectorInstrCost(Opcode, Val, Index); 274 } 275 276 // Estimated cost of a load-hit-store delay. This was obtained 277 // experimentally as a minimum needed to prevent unprofitable 278 // vectorization for the paq8p benchmark. It may need to be 279 // raised further if other unprofitable cases remain. 280 unsigned LHSPenalty = 2; 281 if (ISD == ISD::INSERT_VECTOR_ELT) 282 LHSPenalty += 7; 283 284 // Vector element insert/extract with Altivec is very expensive, 285 // because they require store and reload with the attendant 286 // processor stall for load-hit-store. Until VSX is available, 287 // these need to be estimated as very costly. 288 if (ISD == ISD::EXTRACT_VECTOR_ELT || 289 ISD == ISD::INSERT_VECTOR_ELT) 290 return LHSPenalty + BaseT::getVectorInstrCost(Opcode, Val, Index); 291 292 return BaseT::getVectorInstrCost(Opcode, Val, Index); 293 } 294 295 unsigned PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 296 unsigned Alignment, 297 unsigned AddressSpace) { 298 // Legalize the type. 299 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src); 300 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 301 "Invalid Opcode"); 302 303 unsigned Cost = BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace); 304 305 // VSX loads/stores support unaligned access. 306 if (ST->hasVSX()) { 307 if (LT.second == MVT::v2f64 || LT.second == MVT::v2i64) 308 return Cost; 309 } 310 311 bool UnalignedAltivec = 312 Src->isVectorTy() && 313 Src->getPrimitiveSizeInBits() >= LT.second.getSizeInBits() && 314 LT.second.getSizeInBits() == 128 && 315 Opcode == Instruction::Load; 316 317 // PPC in general does not support unaligned loads and stores. They'll need 318 // to be decomposed based on the alignment factor. 319 unsigned SrcBytes = LT.second.getStoreSize(); 320 if (SrcBytes && Alignment && Alignment < SrcBytes && !UnalignedAltivec) { 321 Cost += LT.first*(SrcBytes/Alignment-1); 322 323 // For a vector type, there is also scalarization overhead (only for 324 // stores, loads are expanded using the vector-load + permutation sequence, 325 // which is much less expensive). 326 if (Src->isVectorTy() && Opcode == Instruction::Store) 327 for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i) 328 Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i); 329 } 330 331 return Cost; 332 } 333 334