15321dcd6SQingShan Zhang //===- PPCMachineScheduler.h - Custom PowerPC MI scheduler --*- C++ -*-===// 25321dcd6SQingShan Zhang // 35321dcd6SQingShan Zhang // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 45321dcd6SQingShan Zhang // See https://llvm.org/LICENSE.txt for license information. 55321dcd6SQingShan Zhang // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 65321dcd6SQingShan Zhang // 75321dcd6SQingShan Zhang //===----------------------------------------------------------------------===// 85321dcd6SQingShan Zhang // 95321dcd6SQingShan Zhang // Custom PowerPC MI scheduler. 105321dcd6SQingShan Zhang // 115321dcd6SQingShan Zhang //===----------------------------------------------------------------------===// 125321dcd6SQingShan Zhang 135321dcd6SQingShan Zhang #ifndef LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H 145321dcd6SQingShan Zhang #define LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H 155321dcd6SQingShan Zhang 165321dcd6SQingShan Zhang #include "llvm/CodeGen/MachineScheduler.h" 175321dcd6SQingShan Zhang 185321dcd6SQingShan Zhang namespace llvm { 195321dcd6SQingShan Zhang 205321dcd6SQingShan Zhang /// A MachineSchedStrategy implementation for PowerPC pre RA scheduling. 215321dcd6SQingShan Zhang class PPCPreRASchedStrategy : public GenericScheduler { 225321dcd6SQingShan Zhang public: PPCPreRASchedStrategy(const MachineSchedContext * C)235321dcd6SQingShan Zhang PPCPreRASchedStrategy(const MachineSchedContext *C) : 245321dcd6SQingShan Zhang GenericScheduler(C) {} 25449bfdd1SQingShan Zhang protected: 26*07f0faedSQiu Chaofan bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, 27449bfdd1SQingShan Zhang SchedBoundary *Zone) const override; 28*07f0faedSQiu Chaofan 29449bfdd1SQingShan Zhang private: 30449bfdd1SQingShan Zhang bool biasAddiLoadCandidate(SchedCandidate &Cand, 31449bfdd1SQingShan Zhang SchedCandidate &TryCand, 32449bfdd1SQingShan Zhang SchedBoundary &Zone) const; 335321dcd6SQingShan Zhang }; 345321dcd6SQingShan Zhang 355321dcd6SQingShan Zhang /// A MachineSchedStrategy implementation for PowerPC post RA scheduling. 365321dcd6SQingShan Zhang class PPCPostRASchedStrategy : public PostGenericScheduler { 375321dcd6SQingShan Zhang public: PPCPostRASchedStrategy(const MachineSchedContext * C)385321dcd6SQingShan Zhang PPCPostRASchedStrategy(const MachineSchedContext *C) : 395321dcd6SQingShan Zhang PostGenericScheduler(C) {} 405321dcd6SQingShan Zhang 415321dcd6SQingShan Zhang protected: 425321dcd6SQingShan Zhang void initialize(ScheduleDAGMI *Dag) override; 435321dcd6SQingShan Zhang SUnit *pickNode(bool &IsTopNode) override; 445321dcd6SQingShan Zhang void enterMBB(MachineBasicBlock *MBB) override; 455321dcd6SQingShan Zhang void leaveMBB() override; 46f8eabd6dSQingShan Zhang 47*07f0faedSQiu Chaofan bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) override; 48f8eabd6dSQingShan Zhang bool biasAddiCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) const; 495321dcd6SQingShan Zhang }; 505321dcd6SQingShan Zhang 515321dcd6SQingShan Zhang } // end namespace llvm 525321dcd6SQingShan Zhang 535321dcd6SQingShan Zhang #endif // LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H 54