1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements hazard recognizers for scheduling on PowerPC processors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "pre-RA-sched" 15 #include "PPCHazardRecognizers.h" 16 #include "PPC.h" 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/ScheduleDAG.h" 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/raw_ostream.h" 22 using namespace llvm; 23 24 //===----------------------------------------------------------------------===// 25 // PowerPC 970 Hazard Recognizer 26 // 27 // This models the dispatch group formation of the PPC970 processor. Dispatch 28 // groups are bundles of up to five instructions that can contain various mixes 29 // of instructions. The PPC970 can dispatch a peak of 4 non-branch and one 30 // branch instruction per-cycle. 31 // 32 // There are a number of restrictions to dispatch group formation: some 33 // instructions can only be issued in the first slot of a dispatch group, & some 34 // instructions fill an entire dispatch group. Additionally, only branches can 35 // issue in the 5th (last) slot. 36 // 37 // Finally, there are a number of "structural" hazards on the PPC970. These 38 // conditions cause large performance penalties due to misprediction, recovery, 39 // and replay logic that has to happen. These cases include setting a CTR and 40 // branching through it in the same dispatch group, and storing to an address, 41 // then loading from the same address within a dispatch group. To avoid these 42 // conditions, we insert no-op instructions when appropriate. 43 // 44 // FIXME: This is missing some significant cases: 45 // 1. Modeling of microcoded instructions. 46 // 2. Handling of serialized operations. 47 // 3. Handling of the esoteric cases in "Resource-based Instruction Grouping". 48 // 49 50 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetMachine &TM) 51 : TM(TM) { 52 EndDispatchGroup(); 53 } 54 55 void PPCHazardRecognizer970::EndDispatchGroup() { 56 DEBUG(errs() << "=== Start of dispatch group\n"); 57 NumIssued = 0; 58 59 // Structural hazard info. 60 HasCTRSet = false; 61 NumStores = 0; 62 } 63 64 65 PPCII::PPC970_Unit 66 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, 67 bool &isFirst, bool &isSingle, 68 bool &isCracked, 69 bool &isLoad, bool &isStore) { 70 const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode); 71 72 isLoad = MCID.mayLoad(); 73 isStore = MCID.mayStore(); 74 75 uint64_t TSFlags = MCID.TSFlags; 76 77 isFirst = TSFlags & PPCII::PPC970_First; 78 isSingle = TSFlags & PPCII::PPC970_Single; 79 isCracked = TSFlags & PPCII::PPC970_Cracked; 80 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); 81 } 82 83 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer 84 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true. 85 bool PPCHazardRecognizer970:: 86 isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset, 87 const Value *LoadValue) const { 88 for (unsigned i = 0, e = NumStores; i != e; ++i) { 89 // Handle exact and commuted addresses. 90 if (LoadValue == StoreValue[i] && LoadOffset == StoreOffset[i]) 91 return true; 92 93 // Okay, we don't have an exact match, if this is an indexed offset, see if 94 // we have overlap (which happens during fp->int conversion for example). 95 if (StoreValue[i] == LoadValue) { 96 // Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check 97 // to see if the load and store actually overlap. 98 if (StoreOffset[i] < LoadOffset) { 99 if (int64_t(StoreOffset[i]+StoreSize[i]) > LoadOffset) return true; 100 } else { 101 if (int64_t(LoadOffset+LoadSize) > StoreOffset[i]) return true; 102 } 103 } 104 } 105 return false; 106 } 107 108 /// getHazardType - We return hazard for any non-branch instruction that would 109 /// terminate the dispatch group. We turn NoopHazard for any 110 /// instructions that wouldn't terminate the dispatch group that would cause a 111 /// pipeline flush. 112 ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970:: 113 getHazardType(SUnit *SU, int Stalls) { 114 assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead"); 115 116 MachineInstr *MI = SU->getInstr(); 117 118 if (MI->isDebugValue()) 119 return NoHazard; 120 121 unsigned Opcode = MI->getOpcode(); 122 bool isFirst, isSingle, isCracked, isLoad, isStore; 123 PPCII::PPC970_Unit InstrType = 124 GetInstrType(Opcode, isFirst, isSingle, isCracked, 125 isLoad, isStore); 126 if (InstrType == PPCII::PPC970_Pseudo) return NoHazard; 127 128 // We can only issue a PPC970_First/PPC970_Single instruction (such as 129 // crand/mtspr/etc) if this is the first cycle of the dispatch group. 130 if (NumIssued != 0 && (isFirst || isSingle)) 131 return Hazard; 132 133 // If this instruction is cracked into two ops by the decoder, we know that 134 // it is not a branch and that it cannot issue if 3 other instructions are 135 // already in the dispatch group. 136 if (isCracked && NumIssued > 2) 137 return Hazard; 138 139 switch (InstrType) { 140 default: llvm_unreachable("Unknown instruction type!"); 141 case PPCII::PPC970_FXU: 142 case PPCII::PPC970_LSU: 143 case PPCII::PPC970_FPU: 144 case PPCII::PPC970_VALU: 145 case PPCII::PPC970_VPERM: 146 // We can only issue a branch as the last instruction in a group. 147 if (NumIssued == 4) return Hazard; 148 break; 149 case PPCII::PPC970_CRU: 150 // We can only issue a CR instruction in the first two slots. 151 if (NumIssued >= 2) return Hazard; 152 break; 153 case PPCII::PPC970_BRU: 154 break; 155 } 156 157 // Do not allow MTCTR and BCTRL to be in the same dispatch group. 158 if (HasCTRSet && Opcode == PPC::BCTRL) 159 return NoopHazard; 160 161 // If this is a load following a store, make sure it's not to the same or 162 // overlapping address. 163 if (isLoad && NumStores && !MI->memoperands_empty()) { 164 MachineMemOperand *MO = *MI->memoperands_begin(); 165 if (isLoadOfStoredAddress(MO->getSize(), 166 MO->getOffset(), MO->getValue())) 167 return NoopHazard; 168 } 169 170 return NoHazard; 171 } 172 173 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { 174 MachineInstr *MI = SU->getInstr(); 175 176 if (MI->isDebugValue()) 177 return; 178 179 unsigned Opcode = MI->getOpcode(); 180 bool isFirst, isSingle, isCracked, isLoad, isStore; 181 PPCII::PPC970_Unit InstrType = 182 GetInstrType(Opcode, isFirst, isSingle, isCracked, 183 isLoad, isStore); 184 if (InstrType == PPCII::PPC970_Pseudo) return; 185 186 // Update structural hazard information. 187 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true; 188 189 // Track the address stored to. 190 if (isStore && NumStores < 4 && !MI->memoperands_empty()) { 191 MachineMemOperand *MO = *MI->memoperands_begin(); 192 StoreSize[NumStores] = MO->getSize(); 193 StoreOffset[NumStores] = MO->getOffset(); 194 StoreValue[NumStores] = MO->getValue(); 195 ++NumStores; 196 } 197 198 if (InstrType == PPCII::PPC970_BRU || isSingle) 199 NumIssued = 4; // Terminate a d-group. 200 ++NumIssued; 201 202 // If this instruction is cracked into two ops by the decoder, remember that 203 // we issued two pieces. 204 if (isCracked) 205 ++NumIssued; 206 207 if (NumIssued == 5) 208 EndDispatchGroup(); 209 } 210 211 void PPCHazardRecognizer970::AdvanceCycle() { 212 assert(NumIssued < 5 && "Illegal dispatch group!"); 213 ++NumIssued; 214 if (NumIssued == 5) 215 EndDispatchGroup(); 216 } 217 218 void PPCHazardRecognizer970::Reset() { 219 EndDispatchGroup(); 220 } 221 222