1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PPC implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCFrameLowering.h" 15 #include "PPCInstrBuilder.h" 16 #include "PPCInstrInfo.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineModuleInfo.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/RegisterScavenging.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Target/TargetOptions.h" 26 27 using namespace llvm; 28 29 // FIXME This disables some code that aligns the stack to a boundary bigger than 30 // the default (16 bytes on Darwin) when there is a stack local of greater 31 // alignment. This does not currently work, because the delta between old and 32 // new stack pointers is added to offsets that reference incoming parameters 33 // after the prolog is generated, and the code that does that doesn't handle a 34 // variable delta. You don't want to do that anyway; a better approach is to 35 // reserve another register that retains to the incoming stack pointer, and 36 // reference parameters relative to that. 37 #define ALIGN_STACK 0 38 39 40 /// VRRegNo - Map from a numbered VR register to its enum value. 41 /// 42 static const uint16_t VRRegNo[] = { 43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 47 }; 48 49 /// RemoveVRSaveCode - We have found that this function does not need any code 50 /// to manipulate the VRSAVE register, even though it uses vector registers. 51 /// This can happen when the only registers used are known to be live in or out 52 /// of the function. Remove all of the VRSAVE related code from the function. 53 /// FIXME: The removal of the code results in a compile failure at -O0 when the 54 /// function contains a function call, as the GPR containing original VRSAVE 55 /// contents is spilled and reloaded around the call. Without the prolog code, 56 /// the spill instruction refers to an undefined register. This code needs 57 /// to account for all uses of that GPR. 58 static void RemoveVRSaveCode(MachineInstr *MI) { 59 MachineBasicBlock *Entry = MI->getParent(); 60 MachineFunction *MF = Entry->getParent(); 61 62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 63 MachineBasicBlock::iterator MBBI = MI; 64 ++MBBI; 65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 66 MBBI->eraseFromParent(); 67 68 bool RemovedAllMTVRSAVEs = true; 69 // See if we can find and remove the MTVRSAVE instruction from all of the 70 // epilog blocks. 71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 72 // If last instruction is a return instruction, add an epilogue 73 if (!I->empty() && I->back().isReturn()) { 74 bool FoundIt = false; 75 for (MBBI = I->end(); MBBI != I->begin(); ) { 76 --MBBI; 77 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 78 MBBI->eraseFromParent(); // remove it. 79 FoundIt = true; 80 break; 81 } 82 } 83 RemovedAllMTVRSAVEs &= FoundIt; 84 } 85 } 86 87 // If we found and removed all MTVRSAVE instructions, remove the read of 88 // VRSAVE as well. 89 if (RemovedAllMTVRSAVEs) { 90 MBBI = MI; 91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 92 --MBBI; 93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 94 MBBI->eraseFromParent(); 95 } 96 97 // Finally, nuke the UPDATE_VRSAVE. 98 MI->eraseFromParent(); 99 } 100 101 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 102 // instruction selector. Based on the vector registers that have been used, 103 // transform this into the appropriate ORI instruction. 104 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 105 MachineFunction *MF = MI->getParent()->getParent(); 106 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 107 DebugLoc dl = MI->getDebugLoc(); 108 109 unsigned UsedRegMask = 0; 110 for (unsigned i = 0; i != 32; ++i) 111 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 112 UsedRegMask |= 1 << (31-i); 113 114 // Live in and live out values already must be in the mask, so don't bother 115 // marking them. 116 for (MachineRegisterInfo::livein_iterator 117 I = MF->getRegInfo().livein_begin(), 118 E = MF->getRegInfo().livein_end(); I != E; ++I) { 119 unsigned RegNo = TRI->getEncodingValue(I->first); 120 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 121 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 122 } 123 124 // Live out registers appear as use operands on return instructions. 125 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 126 UsedRegMask != 0 && BI != BE; ++BI) { 127 const MachineBasicBlock &MBB = *BI; 128 if (MBB.empty() || !MBB.back().isReturn()) 129 continue; 130 const MachineInstr &Ret = MBB.back(); 131 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 132 const MachineOperand &MO = Ret.getOperand(I); 133 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 134 continue; 135 unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 136 UsedRegMask &= ~(1 << (31-RegNo)); 137 } 138 } 139 140 // If no registers are used, turn this into a copy. 141 if (UsedRegMask == 0) { 142 // Remove all VRSAVE code. 143 RemoveVRSaveCode(MI); 144 return; 145 } 146 147 unsigned SrcReg = MI->getOperand(1).getReg(); 148 unsigned DstReg = MI->getOperand(0).getReg(); 149 150 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 151 if (DstReg != SrcReg) 152 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 153 .addReg(SrcReg) 154 .addImm(UsedRegMask); 155 else 156 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 157 .addReg(SrcReg, RegState::Kill) 158 .addImm(UsedRegMask); 159 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 160 if (DstReg != SrcReg) 161 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 162 .addReg(SrcReg) 163 .addImm(UsedRegMask >> 16); 164 else 165 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 166 .addReg(SrcReg, RegState::Kill) 167 .addImm(UsedRegMask >> 16); 168 } else { 169 if (DstReg != SrcReg) 170 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 171 .addReg(SrcReg) 172 .addImm(UsedRegMask >> 16); 173 else 174 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 175 .addReg(SrcReg, RegState::Kill) 176 .addImm(UsedRegMask >> 16); 177 178 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 179 .addReg(DstReg, RegState::Kill) 180 .addImm(UsedRegMask & 0xFFFF); 181 } 182 183 // Remove the old UPDATE_VRSAVE instruction. 184 MI->eraseFromParent(); 185 } 186 187 static bool spillsCR(const MachineFunction &MF) { 188 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 189 return FuncInfo->isCRSpilled(); 190 } 191 192 static bool spillsVRSAVE(const MachineFunction &MF) { 193 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 194 return FuncInfo->isVRSAVESpilled(); 195 } 196 197 static bool hasSpills(const MachineFunction &MF) { 198 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 199 return FuncInfo->hasSpills(); 200 } 201 202 static bool hasNonRISpills(const MachineFunction &MF) { 203 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 204 return FuncInfo->hasNonRISpills(); 205 } 206 207 /// determineFrameLayout - Determine the size of the frame and maximum call 208 /// frame size. 209 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 210 bool UpdateMF, 211 bool UseEstimate) const { 212 MachineFrameInfo *MFI = MF.getFrameInfo(); 213 214 // Get the number of bytes to allocate from the FrameInfo 215 unsigned FrameSize = 216 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 217 218 // Get the alignments provided by the target, and the maximum alignment 219 // (if any) of the fixed frame objects. 220 unsigned MaxAlign = MFI->getMaxAlignment(); 221 unsigned TargetAlign = getStackAlignment(); 222 unsigned AlignMask = TargetAlign - 1; // 223 224 // If we are a leaf function, and use up to 224 bytes of stack space, 225 // don't have a frame pointer, calls, or dynamic alloca then we do not need 226 // to adjust the stack pointer (we fit in the Red Zone). For 64-bit 227 // SVR4, we also require a stack frame if we need to spill the CR, 228 // since this spill area is addressed relative to the stack pointer. 229 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 230 // stackless code if all local vars are reg-allocated. 231 bool DisableRedZone = MF.getFunction()->getAttributes(). 232 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone); 233 if (!DisableRedZone && 234 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 235 !Subtarget.isSVR4ABI() || // allocated locals. 236 FrameSize == 0) && 237 FrameSize <= 224 && // Fits in red zone. 238 !MFI->hasVarSizedObjects() && // No dynamic alloca. 239 !MFI->adjustsStack() && // No calls. 240 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave. 241 Subtarget.isSVR4ABI() 242 && spillsCR(MF)) && 243 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 244 // No need for frame 245 if (UpdateMF) 246 MFI->setStackSize(0); 247 return 0; 248 } 249 250 // Get the maximum call frame size of all the calls. 251 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 252 253 // Maximum call frame needs to be at least big enough for linkage and 8 args. 254 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 255 Subtarget.isDarwinABI()); 256 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 257 258 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 259 // that allocations will be aligned. 260 if (MFI->hasVarSizedObjects()) 261 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 262 263 // Update maximum call frame size. 264 if (UpdateMF) 265 MFI->setMaxCallFrameSize(maxCallFrameSize); 266 267 // Include call frame size in total. 268 FrameSize += maxCallFrameSize; 269 270 // Make sure the frame is aligned. 271 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 272 273 // Update frame info. 274 if (UpdateMF) 275 MFI->setStackSize(FrameSize); 276 277 return FrameSize; 278 } 279 280 // hasFP - Return true if the specified function actually has a dedicated frame 281 // pointer register. 282 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 283 const MachineFrameInfo *MFI = MF.getFrameInfo(); 284 // FIXME: This is pretty much broken by design: hasFP() might be called really 285 // early, before the stack layout was calculated and thus hasFP() might return 286 // true or false here depending on the time of call. 287 return (MFI->getStackSize()) && needsFP(MF); 288 } 289 290 // needsFP - Return true if the specified function should have a dedicated frame 291 // pointer register. This is true if the function has variable sized allocas or 292 // if frame pointer elimination is disabled. 293 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 294 const MachineFrameInfo *MFI = MF.getFrameInfo(); 295 296 // Naked functions have no stack frame pushed, so we don't have a frame 297 // pointer. 298 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 299 Attribute::Naked)) 300 return false; 301 302 return MF.getTarget().Options.DisableFramePointerElim(MF) || 303 MFI->hasVarSizedObjects() || 304 (MF.getTarget().Options.GuaranteedTailCallOpt && 305 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 306 } 307 308 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 309 bool is31 = needsFP(MF); 310 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 311 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 312 313 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 314 BI != BE; ++BI) 315 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 316 --MBBI; 317 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 318 MachineOperand &MO = MBBI->getOperand(I); 319 if (!MO.isReg()) 320 continue; 321 322 switch (MO.getReg()) { 323 case PPC::FP: 324 MO.setReg(FPReg); 325 break; 326 case PPC::FP8: 327 MO.setReg(FP8Reg); 328 break; 329 } 330 } 331 } 332 } 333 334 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 335 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 336 MachineBasicBlock::iterator MBBI = MBB.begin(); 337 MachineFrameInfo *MFI = MF.getFrameInfo(); 338 const PPCInstrInfo &TII = 339 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 340 341 MachineModuleInfo &MMI = MF.getMMI(); 342 DebugLoc dl; 343 bool needsFrameMoves = MMI.hasDebugInfo() || 344 MF.getFunction()->needsUnwindTableEntry(); 345 346 // Prepare for frame info. 347 MCSymbol *FrameLabel = 0; 348 349 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 350 // process it. 351 if (!Subtarget.isSVR4ABI()) 352 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 353 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 354 HandleVRSaveUpdate(MBBI, TII); 355 break; 356 } 357 } 358 359 // Move MBBI back to the beginning of the function. 360 MBBI = MBB.begin(); 361 362 // Work out frame sizes. 363 unsigned FrameSize = determineFrameLayout(MF); 364 int NegFrameSize = -FrameSize; 365 366 if (MFI->isFrameAddressTaken()) 367 replaceFPWithRealFP(MF); 368 369 // Get processor type. 370 bool isPPC64 = Subtarget.isPPC64(); 371 // Get operating system 372 bool isDarwinABI = Subtarget.isDarwinABI(); 373 // Check if the link register (LR) must be saved. 374 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 375 bool MustSaveLR = FI->mustSaveLR(); 376 // Do we have a frame pointer for this function? 377 bool HasFP = hasFP(MF); 378 379 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 380 381 int FPOffset = 0; 382 if (HasFP) { 383 if (Subtarget.isSVR4ABI()) { 384 MachineFrameInfo *FFI = MF.getFrameInfo(); 385 int FPIndex = FI->getFramePointerSaveIndex(); 386 assert(FPIndex && "No Frame Pointer Save Slot!"); 387 FPOffset = FFI->getObjectOffset(FPIndex); 388 } else { 389 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 390 } 391 } 392 393 if (isPPC64) { 394 if (MustSaveLR) 395 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 396 397 if (HasFP) 398 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 399 .addReg(PPC::X31) 400 .addImm(FPOffset/4) 401 .addReg(PPC::X1); 402 403 if (MustSaveLR) 404 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 405 .addReg(PPC::X0) 406 .addImm(LROffset / 4) 407 .addReg(PPC::X1); 408 } else { 409 if (MustSaveLR) 410 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 411 412 if (HasFP) 413 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative 414 // offsets of R1 is not allowed. 415 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 416 .addReg(PPC::R31) 417 .addImm(FPOffset) 418 .addReg(PPC::R1); 419 420 if (MustSaveLR) 421 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 422 .addReg(PPC::R0) 423 .addImm(LROffset) 424 .addReg(PPC::R1); 425 } 426 427 // Skip if a leaf routine. 428 if (!FrameSize) return; 429 430 // Get stack alignments. 431 unsigned TargetAlign = getStackAlignment(); 432 unsigned MaxAlign = MFI->getMaxAlignment(); 433 434 // Adjust stack pointer: r1 += NegFrameSize. 435 // If there is a preferred stack alignment, align R1 now 436 if (!isPPC64) { 437 // PPC32. 438 if (ALIGN_STACK && MaxAlign > TargetAlign) { 439 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 440 "Invalid alignment!"); 441 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 442 443 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 444 .addReg(PPC::R1) 445 .addImm(0) 446 .addImm(32 - Log2_32(MaxAlign)) 447 .addImm(31); 448 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 449 .addReg(PPC::R0, RegState::Kill) 450 .addImm(NegFrameSize); 451 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 452 .addReg(PPC::R1, RegState::Kill) 453 .addReg(PPC::R1) 454 .addReg(PPC::R0); 455 } else if (isInt<16>(NegFrameSize)) { 456 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 457 .addReg(PPC::R1) 458 .addImm(NegFrameSize) 459 .addReg(PPC::R1); 460 } else { 461 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 462 .addImm(NegFrameSize >> 16); 463 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 464 .addReg(PPC::R0, RegState::Kill) 465 .addImm(NegFrameSize & 0xFFFF); 466 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 467 .addReg(PPC::R1, RegState::Kill) 468 .addReg(PPC::R1) 469 .addReg(PPC::R0); 470 } 471 } else { // PPC64. 472 if (ALIGN_STACK && MaxAlign > TargetAlign) { 473 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 474 "Invalid alignment!"); 475 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 476 477 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 478 .addReg(PPC::X1) 479 .addImm(0) 480 .addImm(64 - Log2_32(MaxAlign)); 481 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 482 .addReg(PPC::X0) 483 .addImm(NegFrameSize); 484 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 485 .addReg(PPC::X1, RegState::Kill) 486 .addReg(PPC::X1) 487 .addReg(PPC::X0); 488 } else if (isInt<16>(NegFrameSize)) { 489 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 490 .addReg(PPC::X1) 491 .addImm(NegFrameSize / 4) 492 .addReg(PPC::X1); 493 } else { 494 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 495 .addImm(NegFrameSize >> 16); 496 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 497 .addReg(PPC::X0, RegState::Kill) 498 .addImm(NegFrameSize & 0xFFFF); 499 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 500 .addReg(PPC::X1, RegState::Kill) 501 .addReg(PPC::X1) 502 .addReg(PPC::X0); 503 } 504 } 505 506 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 507 508 // Add the "machine moves" for the instructions we generated above, but in 509 // reverse order. 510 if (needsFrameMoves) { 511 // Mark effective beginning of when frame pointer becomes valid. 512 FrameLabel = MMI.getContext().CreateTempSymbol(); 513 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 514 515 // Show update of SP. 516 if (NegFrameSize) { 517 MachineLocation SPDst(MachineLocation::VirtualFP); 518 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 519 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 520 } else { 521 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 522 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 523 } 524 525 if (HasFP) { 526 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 527 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 528 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 529 } 530 531 if (MustSaveLR) { 532 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 533 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 534 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 535 } 536 } 537 538 MCSymbol *ReadyLabel = 0; 539 540 // If there is a frame pointer, copy R1 into R31 541 if (HasFP) { 542 if (!isPPC64) { 543 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 544 .addReg(PPC::R1) 545 .addReg(PPC::R1); 546 } else { 547 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 548 .addReg(PPC::X1) 549 .addReg(PPC::X1); 550 } 551 552 if (needsFrameMoves) { 553 ReadyLabel = MMI.getContext().CreateTempSymbol(); 554 555 // Mark effective beginning of when frame pointer is ready. 556 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 557 558 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 559 (isPPC64 ? PPC::X1 : PPC::R1)); 560 MachineLocation FPSrc(MachineLocation::VirtualFP); 561 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 562 } 563 } 564 565 if (needsFrameMoves) { 566 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 567 568 // Add callee saved registers to move list. 569 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 570 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 571 unsigned Reg = CSI[I].getReg(); 572 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 573 574 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 575 // subregisters of CR2. We just need to emit a move of CR2. 576 if (PPC::CRBITRCRegClass.contains(Reg)) 577 continue; 578 579 // For SVR4, don't emit a move for the CR spill slot if we haven't 580 // spilled CRs. 581 if (Subtarget.isSVR4ABI() 582 && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 583 && !spillsCR(MF)) 584 continue; 585 586 // For 64-bit SVR4 when we have spilled CRs, the spill location 587 // is SP+8, not a frame-relative slot. 588 if (Subtarget.isSVR4ABI() 589 && Subtarget.isPPC64() 590 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 591 MachineLocation CSDst(PPC::X1, 8); 592 MachineLocation CSSrc(PPC::CR2); 593 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 594 continue; 595 } 596 597 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 598 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 599 MachineLocation CSSrc(Reg); 600 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 601 } 602 } 603 } 604 605 void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 606 MachineBasicBlock &MBB) const { 607 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 608 assert(MBBI != MBB.end() && "Returning block has no terminator"); 609 const PPCInstrInfo &TII = 610 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 611 612 unsigned RetOpcode = MBBI->getOpcode(); 613 DebugLoc dl; 614 615 assert((RetOpcode == PPC::BLR || 616 RetOpcode == PPC::TCRETURNri || 617 RetOpcode == PPC::TCRETURNdi || 618 RetOpcode == PPC::TCRETURNai || 619 RetOpcode == PPC::TCRETURNri8 || 620 RetOpcode == PPC::TCRETURNdi8 || 621 RetOpcode == PPC::TCRETURNai8) && 622 "Can only insert epilog into returning blocks"); 623 624 // Get alignment info so we know how to restore r1 625 const MachineFrameInfo *MFI = MF.getFrameInfo(); 626 unsigned TargetAlign = getStackAlignment(); 627 unsigned MaxAlign = MFI->getMaxAlignment(); 628 629 // Get the number of bytes allocated from the FrameInfo. 630 int FrameSize = MFI->getStackSize(); 631 632 // Get processor type. 633 bool isPPC64 = Subtarget.isPPC64(); 634 // Get operating system 635 bool isDarwinABI = Subtarget.isDarwinABI(); 636 // Check if the link register (LR) has been saved. 637 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 638 bool MustSaveLR = FI->mustSaveLR(); 639 // Do we have a frame pointer for this function? 640 bool HasFP = hasFP(MF); 641 642 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 643 644 int FPOffset = 0; 645 if (HasFP) { 646 if (Subtarget.isSVR4ABI()) { 647 MachineFrameInfo *FFI = MF.getFrameInfo(); 648 int FPIndex = FI->getFramePointerSaveIndex(); 649 assert(FPIndex && "No Frame Pointer Save Slot!"); 650 FPOffset = FFI->getObjectOffset(FPIndex); 651 } else { 652 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 653 } 654 } 655 656 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 657 RetOpcode == PPC::TCRETURNdi || 658 RetOpcode == PPC::TCRETURNai || 659 RetOpcode == PPC::TCRETURNri8 || 660 RetOpcode == PPC::TCRETURNdi8 || 661 RetOpcode == PPC::TCRETURNai8; 662 663 if (UsesTCRet) { 664 int MaxTCRetDelta = FI->getTailCallSPDelta(); 665 MachineOperand &StackAdjust = MBBI->getOperand(1); 666 assert(StackAdjust.isImm() && "Expecting immediate value."); 667 // Adjust stack pointer. 668 int StackAdj = StackAdjust.getImm(); 669 int Delta = StackAdj - MaxTCRetDelta; 670 assert((Delta >= 0) && "Delta must be positive"); 671 if (MaxTCRetDelta>0) 672 FrameSize += (StackAdj +Delta); 673 else 674 FrameSize += StackAdj; 675 } 676 677 if (FrameSize) { 678 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 679 // on entry to the function. Add this offset back now. 680 if (!isPPC64) { 681 // If this function contained a fastcc call and GuaranteedTailCallOpt is 682 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 683 // call which invalidates the stack pointer value in SP(0). So we use the 684 // value of R31 in this case. 685 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 686 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 687 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 688 .addReg(PPC::R31).addImm(FrameSize); 689 } else if(FI->hasFastCall()) { 690 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 691 .addImm(FrameSize >> 16); 692 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 693 .addReg(PPC::R0, RegState::Kill) 694 .addImm(FrameSize & 0xFFFF); 695 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 696 .addReg(PPC::R1) 697 .addReg(PPC::R31) 698 .addReg(PPC::R0); 699 } else if (isInt<16>(FrameSize) && 700 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 701 !MFI->hasVarSizedObjects()) { 702 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 703 .addReg(PPC::R1).addImm(FrameSize); 704 } else { 705 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 706 .addImm(0).addReg(PPC::R1); 707 } 708 } else { 709 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 710 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 711 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 712 .addReg(PPC::X31).addImm(FrameSize); 713 } else if(FI->hasFastCall()) { 714 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 715 .addImm(FrameSize >> 16); 716 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 717 .addReg(PPC::X0, RegState::Kill) 718 .addImm(FrameSize & 0xFFFF); 719 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 720 .addReg(PPC::X1) 721 .addReg(PPC::X31) 722 .addReg(PPC::X0); 723 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 724 !MFI->hasVarSizedObjects()) { 725 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 726 .addReg(PPC::X1).addImm(FrameSize); 727 } else { 728 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 729 .addImm(0).addReg(PPC::X1); 730 } 731 } 732 } 733 734 if (isPPC64) { 735 if (MustSaveLR) 736 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 737 .addImm(LROffset/4).addReg(PPC::X1); 738 739 if (HasFP) 740 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 741 .addImm(FPOffset/4).addReg(PPC::X1); 742 743 if (MustSaveLR) 744 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 745 } else { 746 if (MustSaveLR) 747 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 748 .addImm(LROffset).addReg(PPC::R1); 749 750 if (HasFP) 751 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 752 .addImm(FPOffset).addReg(PPC::R1); 753 754 if (MustSaveLR) 755 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 756 } 757 758 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 759 // call optimization 760 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 761 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 762 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 763 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 764 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 765 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 766 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 767 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 768 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 769 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 770 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 771 772 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 773 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 774 .addReg(StackReg).addImm(CallerAllocatedAmt); 775 } else { 776 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 777 .addImm(CallerAllocatedAmt >> 16); 778 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 779 .addReg(TmpReg, RegState::Kill) 780 .addImm(CallerAllocatedAmt & 0xFFFF); 781 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 782 .addReg(StackReg) 783 .addReg(FPReg) 784 .addReg(TmpReg); 785 } 786 } else if (RetOpcode == PPC::TCRETURNdi) { 787 MBBI = MBB.getLastNonDebugInstr(); 788 MachineOperand &JumpTarget = MBBI->getOperand(0); 789 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 790 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 791 } else if (RetOpcode == PPC::TCRETURNri) { 792 MBBI = MBB.getLastNonDebugInstr(); 793 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 794 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 795 } else if (RetOpcode == PPC::TCRETURNai) { 796 MBBI = MBB.getLastNonDebugInstr(); 797 MachineOperand &JumpTarget = MBBI->getOperand(0); 798 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 799 } else if (RetOpcode == PPC::TCRETURNdi8) { 800 MBBI = MBB.getLastNonDebugInstr(); 801 MachineOperand &JumpTarget = MBBI->getOperand(0); 802 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 803 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 804 } else if (RetOpcode == PPC::TCRETURNri8) { 805 MBBI = MBB.getLastNonDebugInstr(); 806 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 807 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 808 } else if (RetOpcode == PPC::TCRETURNai8) { 809 MBBI = MBB.getLastNonDebugInstr(); 810 MachineOperand &JumpTarget = MBBI->getOperand(0); 811 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 812 } 813 } 814 815 /// MustSaveLR - Return true if this function requires that we save the LR 816 /// register onto the stack in the prolog and restore it in the epilog of the 817 /// function. 818 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 819 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 820 821 // We need a save/restore of LR if there is any def of LR (which is 822 // defined by calls, including the PIC setup sequence), or if there is 823 // some use of the LR stack slot (e.g. for builtin_return_address). 824 // (LR comes in 32 and 64 bit versions.) 825 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 826 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 827 } 828 829 void 830 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 831 RegScavenger *) const { 832 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 833 834 // Save and clear the LR state. 835 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 836 unsigned LR = RegInfo->getRARegister(); 837 FI->setMustSaveLR(MustSaveLR(MF, LR)); 838 MachineRegisterInfo &MRI = MF.getRegInfo(); 839 MRI.setPhysRegUnused(LR); 840 841 // Save R31 if necessary 842 int FPSI = FI->getFramePointerSaveIndex(); 843 bool isPPC64 = Subtarget.isPPC64(); 844 bool isDarwinABI = Subtarget.isDarwinABI(); 845 MachineFrameInfo *MFI = MF.getFrameInfo(); 846 847 // If the frame pointer save index hasn't been defined yet. 848 if (!FPSI && needsFP(MF)) { 849 // Find out what the fix offset of the frame pointer save area. 850 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 851 // Allocate the frame index for frame pointer save area. 852 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 853 // Save the result. 854 FI->setFramePointerSaveIndex(FPSI); 855 } 856 857 // Reserve stack space to move the linkage area to in case of a tail call. 858 int TCSPDelta = 0; 859 if (MF.getTarget().Options.GuaranteedTailCallOpt && 860 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 861 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 862 } 863 864 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 865 // function uses CR 2, 3, or 4. 866 if (!isPPC64 && !isDarwinABI && 867 (MRI.isPhysRegUsed(PPC::CR2) || 868 MRI.isPhysRegUsed(PPC::CR3) || 869 MRI.isPhysRegUsed(PPC::CR4))) { 870 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 871 FI->setCRSpillFrameIndex(FrameIdx); 872 } 873 } 874 875 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 876 RegScavenger *RS) const { 877 // Early exit if not using the SVR4 ABI. 878 if (!Subtarget.isSVR4ABI()) { 879 addScavengingSpillSlot(MF, RS); 880 return; 881 } 882 883 // Get callee saved register information. 884 MachineFrameInfo *FFI = MF.getFrameInfo(); 885 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 886 887 // Early exit if no callee saved registers are modified! 888 if (CSI.empty() && !needsFP(MF)) { 889 addScavengingSpillSlot(MF, RS); 890 return; 891 } 892 893 unsigned MinGPR = PPC::R31; 894 unsigned MinG8R = PPC::X31; 895 unsigned MinFPR = PPC::F31; 896 unsigned MinVR = PPC::V31; 897 898 bool HasGPSaveArea = false; 899 bool HasG8SaveArea = false; 900 bool HasFPSaveArea = false; 901 bool HasVRSAVESaveArea = false; 902 bool HasVRSaveArea = false; 903 904 SmallVector<CalleeSavedInfo, 18> GPRegs; 905 SmallVector<CalleeSavedInfo, 18> G8Regs; 906 SmallVector<CalleeSavedInfo, 18> FPRegs; 907 SmallVector<CalleeSavedInfo, 18> VRegs; 908 909 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 910 unsigned Reg = CSI[i].getReg(); 911 if (PPC::GPRCRegClass.contains(Reg)) { 912 HasGPSaveArea = true; 913 914 GPRegs.push_back(CSI[i]); 915 916 if (Reg < MinGPR) { 917 MinGPR = Reg; 918 } 919 } else if (PPC::G8RCRegClass.contains(Reg)) { 920 HasG8SaveArea = true; 921 922 G8Regs.push_back(CSI[i]); 923 924 if (Reg < MinG8R) { 925 MinG8R = Reg; 926 } 927 } else if (PPC::F8RCRegClass.contains(Reg)) { 928 HasFPSaveArea = true; 929 930 FPRegs.push_back(CSI[i]); 931 932 if (Reg < MinFPR) { 933 MinFPR = Reg; 934 } 935 } else if (PPC::CRBITRCRegClass.contains(Reg) || 936 PPC::CRRCRegClass.contains(Reg)) { 937 ; // do nothing, as we already know whether CRs are spilled 938 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 939 HasVRSAVESaveArea = true; 940 } else if (PPC::VRRCRegClass.contains(Reg)) { 941 HasVRSaveArea = true; 942 943 VRegs.push_back(CSI[i]); 944 945 if (Reg < MinVR) { 946 MinVR = Reg; 947 } 948 } else { 949 llvm_unreachable("Unknown RegisterClass!"); 950 } 951 } 952 953 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 954 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 955 956 int64_t LowerBound = 0; 957 958 // Take into account stack space reserved for tail calls. 959 int TCSPDelta = 0; 960 if (MF.getTarget().Options.GuaranteedTailCallOpt && 961 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 962 LowerBound = TCSPDelta; 963 } 964 965 // The Floating-point register save area is right below the back chain word 966 // of the previous stack frame. 967 if (HasFPSaveArea) { 968 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 969 int FI = FPRegs[i].getFrameIdx(); 970 971 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 972 } 973 974 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 975 } 976 977 // Check whether the frame pointer register is allocated. If so, make sure it 978 // is spilled to the correct offset. 979 if (needsFP(MF)) { 980 HasGPSaveArea = true; 981 982 int FI = PFI->getFramePointerSaveIndex(); 983 assert(FI && "No Frame Pointer Save Slot!"); 984 985 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 986 } 987 988 // General register save area starts right below the Floating-point 989 // register save area. 990 if (HasGPSaveArea || HasG8SaveArea) { 991 // Move general register save area spill slots down, taking into account 992 // the size of the Floating-point register save area. 993 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 994 int FI = GPRegs[i].getFrameIdx(); 995 996 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 997 } 998 999 // Move general register save area spill slots down, taking into account 1000 // the size of the Floating-point register save area. 1001 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1002 int FI = G8Regs[i].getFrameIdx(); 1003 1004 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1005 } 1006 1007 unsigned MinReg = 1008 std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1009 TRI->getEncodingValue(MinG8R)); 1010 1011 if (Subtarget.isPPC64()) { 1012 LowerBound -= (31 - MinReg + 1) * 8; 1013 } else { 1014 LowerBound -= (31 - MinReg + 1) * 4; 1015 } 1016 } 1017 1018 // For 32-bit only, the CR save area is below the general register 1019 // save area. For 64-bit SVR4, the CR save area is addressed relative 1020 // to the stack pointer and hence does not need an adjustment here. 1021 // Only CR2 (the first nonvolatile spilled) has an associated frame 1022 // index so that we have a single uniform save area. 1023 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1024 // Adjust the frame index of the CR spill slot. 1025 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1026 unsigned Reg = CSI[i].getReg(); 1027 1028 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1029 // Leave Darwin logic as-is. 1030 || (!Subtarget.isSVR4ABI() && 1031 (PPC::CRBITRCRegClass.contains(Reg) || 1032 PPC::CRRCRegClass.contains(Reg)))) { 1033 int FI = CSI[i].getFrameIdx(); 1034 1035 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1036 } 1037 } 1038 1039 LowerBound -= 4; // The CR save area is always 4 bytes long. 1040 } 1041 1042 if (HasVRSAVESaveArea) { 1043 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1044 // which have the VRSAVE register class? 1045 // Adjust the frame index of the VRSAVE spill slot. 1046 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1047 unsigned Reg = CSI[i].getReg(); 1048 1049 if (PPC::VRSAVERCRegClass.contains(Reg)) { 1050 int FI = CSI[i].getFrameIdx(); 1051 1052 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1053 } 1054 } 1055 1056 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1057 } 1058 1059 if (HasVRSaveArea) { 1060 // Insert alignment padding, we need 16-byte alignment. 1061 LowerBound = (LowerBound - 15) & ~(15); 1062 1063 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1064 int FI = VRegs[i].getFrameIdx(); 1065 1066 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1067 } 1068 } 1069 1070 addScavengingSpillSlot(MF, RS); 1071 } 1072 1073 void 1074 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1075 RegScavenger *RS) const { 1076 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1077 // a large stack, which will require scavenging a register to materialize a 1078 // large offset. 1079 1080 // We need to have a scavenger spill slot for spills if the frame size is 1081 // large. In case there is no free register for large-offset addressing, 1082 // this slot is used for the necessary emergency spill. Also, we need the 1083 // slot for dynamic stack allocations. 1084 1085 // The scavenger might be invoked if the frame offset does not fit into 1086 // the 16-bit immediate. We don't know the complete frame size here 1087 // because we've not yet computed callee-saved register spills or the 1088 // needed alignment padding. 1089 unsigned StackSize = determineFrameLayout(MF, false, true); 1090 MachineFrameInfo *MFI = MF.getFrameInfo(); 1091 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1092 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1093 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1094 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1095 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1096 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1097 RC->getAlignment(), 1098 false)); 1099 1100 // These kinds of spills might need two registers. 1101 if (spillsCR(MF) || spillsVRSAVE(MF)) 1102 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1103 RC->getAlignment(), 1104 false)); 1105 1106 } 1107 } 1108 1109 bool 1110 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1111 MachineBasicBlock::iterator MI, 1112 const std::vector<CalleeSavedInfo> &CSI, 1113 const TargetRegisterInfo *TRI) const { 1114 1115 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1116 // Return false otherwise to maintain pre-existing behavior. 1117 if (!Subtarget.isSVR4ABI()) 1118 return false; 1119 1120 MachineFunction *MF = MBB.getParent(); 1121 const PPCInstrInfo &TII = 1122 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1123 DebugLoc DL; 1124 bool CRSpilled = false; 1125 1126 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1127 unsigned Reg = CSI[i].getReg(); 1128 // CR2 through CR4 are the nonvolatile CR fields. 1129 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1130 1131 if (CRSpilled && IsCRField) 1132 continue; 1133 1134 // Add the callee-saved register as live-in; it's killed at the spill. 1135 MBB.addLiveIn(Reg); 1136 1137 // Insert the spill to the stack frame. 1138 if (IsCRField) { 1139 CRSpilled = true; 1140 // The first time we see a CR field, store the whole CR into the 1141 // save slot via GPR12 (available in the prolog for 32- and 64-bit). 1142 if (Subtarget.isPPC64()) { 1143 // 64-bit: SP+8 1144 bool is31 = needsFP(*MF); 1145 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 1146 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR8), PPC::X12)); 1147 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW8)) 1148 .addReg(PPC::X12, 1149 getKillRegState(true)) 1150 .addImm(8) 1151 .addReg(FP8Reg)); 1152 } else { 1153 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1154 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1155 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)); 1156 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1157 .addReg(PPC::R12, 1158 getKillRegState(true)), 1159 CSI[i].getFrameIdx())); 1160 } 1161 1162 // Record that we spill the CR in this function. 1163 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1164 FuncInfo->setSpillsCR(); 1165 } else { 1166 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1167 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1168 CSI[i].getFrameIdx(), RC, TRI); 1169 } 1170 } 1171 return true; 1172 } 1173 1174 static void 1175 restoreCRs(bool isPPC64, bool is31, 1176 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1177 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1178 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1179 1180 MachineFunction *MF = MBB.getParent(); 1181 const PPCInstrInfo &TII = 1182 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1183 DebugLoc DL; 1184 unsigned RestoreOp, MoveReg; 1185 1186 if (isPPC64) { 1187 // 64-bit: SP+8 1188 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 1189 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ8), PPC::X12) 1190 .addImm(8) 1191 .addReg(FP8Reg)); 1192 RestoreOp = PPC::MTCRF8; 1193 MoveReg = PPC::X12; 1194 } else { 1195 // 32-bit: FP-relative 1196 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1197 PPC::R12), 1198 CSI[CSIIndex].getFrameIdx())); 1199 RestoreOp = PPC::MTCRF; 1200 MoveReg = PPC::R12; 1201 } 1202 1203 if (CR2Spilled) 1204 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1205 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1206 1207 if (CR3Spilled) 1208 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1209 .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1210 1211 if (CR4Spilled) 1212 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1213 .addReg(MoveReg, getKillRegState(true))); 1214 } 1215 1216 void PPCFrameLowering:: 1217 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1218 MachineBasicBlock::iterator I) const { 1219 const PPCInstrInfo &TII = 1220 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 1221 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1222 I->getOpcode() == PPC::ADJCALLSTACKUP) { 1223 // Add (actually subtract) back the amount the callee popped on return. 1224 if (int CalleeAmt = I->getOperand(1).getImm()) { 1225 bool is64Bit = Subtarget.isPPC64(); 1226 CalleeAmt *= -1; 1227 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1228 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1229 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1230 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1231 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1232 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1233 MachineInstr *MI = I; 1234 DebugLoc dl = MI->getDebugLoc(); 1235 1236 if (isInt<16>(CalleeAmt)) { 1237 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1238 .addReg(StackReg, RegState::Kill) 1239 .addImm(CalleeAmt); 1240 } else { 1241 MachineBasicBlock::iterator MBBI = I; 1242 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1243 .addImm(CalleeAmt >> 16); 1244 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1245 .addReg(TmpReg, RegState::Kill) 1246 .addImm(CalleeAmt & 0xFFFF); 1247 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1248 .addReg(StackReg, RegState::Kill) 1249 .addReg(TmpReg); 1250 } 1251 } 1252 } 1253 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1254 MBB.erase(I); 1255 } 1256 1257 bool 1258 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1259 MachineBasicBlock::iterator MI, 1260 const std::vector<CalleeSavedInfo> &CSI, 1261 const TargetRegisterInfo *TRI) const { 1262 1263 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1264 // Return false otherwise to maintain pre-existing behavior. 1265 if (!Subtarget.isSVR4ABI()) 1266 return false; 1267 1268 MachineFunction *MF = MBB.getParent(); 1269 const PPCInstrInfo &TII = 1270 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1271 bool CR2Spilled = false; 1272 bool CR3Spilled = false; 1273 bool CR4Spilled = false; 1274 unsigned CSIIndex = 0; 1275 1276 // Initialize insertion-point logic; we will be restoring in reverse 1277 // order of spill. 1278 MachineBasicBlock::iterator I = MI, BeforeI = I; 1279 bool AtStart = I == MBB.begin(); 1280 1281 if (!AtStart) 1282 --BeforeI; 1283 1284 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1285 unsigned Reg = CSI[i].getReg(); 1286 1287 if (Reg == PPC::CR2) { 1288 CR2Spilled = true; 1289 // The spill slot is associated only with CR2, which is the 1290 // first nonvolatile spilled. Save it here. 1291 CSIIndex = i; 1292 continue; 1293 } else if (Reg == PPC::CR3) { 1294 CR3Spilled = true; 1295 continue; 1296 } else if (Reg == PPC::CR4) { 1297 CR4Spilled = true; 1298 continue; 1299 } else { 1300 // When we first encounter a non-CR register after seeing at 1301 // least one CR register, restore all spilled CRs together. 1302 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1303 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1304 bool is31 = needsFP(*MF); 1305 restoreCRs(Subtarget.isPPC64(), is31, 1306 CR2Spilled, CR3Spilled, CR4Spilled, 1307 MBB, I, CSI, CSIIndex); 1308 CR2Spilled = CR3Spilled = CR4Spilled = false; 1309 } 1310 1311 // Default behavior for non-CR saves. 1312 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1313 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1314 RC, TRI); 1315 assert(I != MBB.begin() && 1316 "loadRegFromStackSlot didn't insert any code!"); 1317 } 1318 1319 // Insert in reverse order. 1320 if (AtStart) 1321 I = MBB.begin(); 1322 else { 1323 I = BeforeI; 1324 ++I; 1325 } 1326 } 1327 1328 // If we haven't yet spilled the CRs, do so now. 1329 if (CR2Spilled || CR3Spilled || CR4Spilled) { 1330 bool is31 = needsFP(*MF); 1331 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1332 MBB, I, CSI, CSIIndex); 1333 } 1334 1335 return true; 1336 } 1337 1338