1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PPC implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCFrameLowering.h" 15 #include "PPCInstrBuilder.h" 16 #include "PPCInstrInfo.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCSubtarget.h" 19 #include "PPCTargetMachine.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/RegisterScavenging.h" 26 #include "llvm/IR/Function.h" 27 #include "llvm/Target/TargetOptions.h" 28 29 using namespace llvm; 30 31 /// VRRegNo - Map from a numbered VR register to its enum value. 32 /// 33 static const MCPhysReg VRRegNo[] = { 34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 38 }; 39 40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) { 41 if (STI.isDarwinABI()) 42 return STI.isPPC64() ? 16 : 8; 43 // SVR4 ABI: 44 return STI.isPPC64() ? 16 : 4; 45 } 46 47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) { 48 return STI.isELFv2ABI() ? 24 : 40; 49 } 50 51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) { 52 // For the Darwin ABI: 53 // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area 54 // for saving the frame pointer (if needed.) While the published ABI has 55 // not used this slot since at least MacOSX 10.2, there is older code 56 // around that does use it, and that needs to continue to work. 57 if (STI.isDarwinABI()) 58 return STI.isPPC64() ? -8U : -4U; 59 60 // SVR4 ABI: First slot in the general register save area. 61 return STI.isPPC64() ? -8U : -4U; 62 } 63 64 static unsigned computeLinkageSize(const PPCSubtarget &STI) { 65 if (STI.isDarwinABI() || STI.isPPC64()) 66 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4); 67 68 // SVR4 ABI: 69 return 8; 70 } 71 72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) { 73 if (STI.isDarwinABI()) 74 return STI.isPPC64() ? -16U : -8U; 75 76 // SVR4 ABI: First slot in the general register save area. 77 return STI.isPPC64() 78 ? -16U 79 : (STI.getTargetMachine().getRelocationModel() == Reloc::PIC_) 80 ? -12U 81 : -8U; 82 } 83 84 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI) 85 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 86 STI.getPlatformStackAlignment(), 0), 87 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), 88 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), 89 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), 90 LinkageSize(computeLinkageSize(Subtarget)), 91 BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {} 92 93 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. 94 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots( 95 unsigned &NumEntries) const { 96 if (Subtarget.isDarwinABI()) { 97 NumEntries = 1; 98 if (Subtarget.isPPC64()) { 99 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; 100 return &darwin64Offsets; 101 } else { 102 static const SpillSlot darwinOffsets = {PPC::R31, -4}; 103 return &darwinOffsets; 104 } 105 } 106 107 // Early exit if not using the SVR4 ABI. 108 if (!Subtarget.isSVR4ABI()) { 109 NumEntries = 0; 110 return nullptr; 111 } 112 113 // Note that the offsets here overlap, but this is fixed up in 114 // processFunctionBeforeFrameFinalized. 115 116 static const SpillSlot Offsets[] = { 117 // Floating-point register save area offsets. 118 {PPC::F31, -8}, 119 {PPC::F30, -16}, 120 {PPC::F29, -24}, 121 {PPC::F28, -32}, 122 {PPC::F27, -40}, 123 {PPC::F26, -48}, 124 {PPC::F25, -56}, 125 {PPC::F24, -64}, 126 {PPC::F23, -72}, 127 {PPC::F22, -80}, 128 {PPC::F21, -88}, 129 {PPC::F20, -96}, 130 {PPC::F19, -104}, 131 {PPC::F18, -112}, 132 {PPC::F17, -120}, 133 {PPC::F16, -128}, 134 {PPC::F15, -136}, 135 {PPC::F14, -144}, 136 137 // General register save area offsets. 138 {PPC::R31, -4}, 139 {PPC::R30, -8}, 140 {PPC::R29, -12}, 141 {PPC::R28, -16}, 142 {PPC::R27, -20}, 143 {PPC::R26, -24}, 144 {PPC::R25, -28}, 145 {PPC::R24, -32}, 146 {PPC::R23, -36}, 147 {PPC::R22, -40}, 148 {PPC::R21, -44}, 149 {PPC::R20, -48}, 150 {PPC::R19, -52}, 151 {PPC::R18, -56}, 152 {PPC::R17, -60}, 153 {PPC::R16, -64}, 154 {PPC::R15, -68}, 155 {PPC::R14, -72}, 156 157 // CR save area offset. We map each of the nonvolatile CR fields 158 // to the slot for CR2, which is the first of the nonvolatile CR 159 // fields to be assigned, so that we only allocate one save slot. 160 // See PPCRegisterInfo::hasReservedSpillSlot() for more information. 161 {PPC::CR2, -4}, 162 163 // VRSAVE save area offset. 164 {PPC::VRSAVE, -4}, 165 166 // Vector register save area 167 {PPC::V31, -16}, 168 {PPC::V30, -32}, 169 {PPC::V29, -48}, 170 {PPC::V28, -64}, 171 {PPC::V27, -80}, 172 {PPC::V26, -96}, 173 {PPC::V25, -112}, 174 {PPC::V24, -128}, 175 {PPC::V23, -144}, 176 {PPC::V22, -160}, 177 {PPC::V21, -176}, 178 {PPC::V20, -192}}; 179 180 static const SpillSlot Offsets64[] = { 181 // Floating-point register save area offsets. 182 {PPC::F31, -8}, 183 {PPC::F30, -16}, 184 {PPC::F29, -24}, 185 {PPC::F28, -32}, 186 {PPC::F27, -40}, 187 {PPC::F26, -48}, 188 {PPC::F25, -56}, 189 {PPC::F24, -64}, 190 {PPC::F23, -72}, 191 {PPC::F22, -80}, 192 {PPC::F21, -88}, 193 {PPC::F20, -96}, 194 {PPC::F19, -104}, 195 {PPC::F18, -112}, 196 {PPC::F17, -120}, 197 {PPC::F16, -128}, 198 {PPC::F15, -136}, 199 {PPC::F14, -144}, 200 201 // General register save area offsets. 202 {PPC::X31, -8}, 203 {PPC::X30, -16}, 204 {PPC::X29, -24}, 205 {PPC::X28, -32}, 206 {PPC::X27, -40}, 207 {PPC::X26, -48}, 208 {PPC::X25, -56}, 209 {PPC::X24, -64}, 210 {PPC::X23, -72}, 211 {PPC::X22, -80}, 212 {PPC::X21, -88}, 213 {PPC::X20, -96}, 214 {PPC::X19, -104}, 215 {PPC::X18, -112}, 216 {PPC::X17, -120}, 217 {PPC::X16, -128}, 218 {PPC::X15, -136}, 219 {PPC::X14, -144}, 220 221 // VRSAVE save area offset. 222 {PPC::VRSAVE, -4}, 223 224 // Vector register save area 225 {PPC::V31, -16}, 226 {PPC::V30, -32}, 227 {PPC::V29, -48}, 228 {PPC::V28, -64}, 229 {PPC::V27, -80}, 230 {PPC::V26, -96}, 231 {PPC::V25, -112}, 232 {PPC::V24, -128}, 233 {PPC::V23, -144}, 234 {PPC::V22, -160}, 235 {PPC::V21, -176}, 236 {PPC::V20, -192}}; 237 238 if (Subtarget.isPPC64()) { 239 NumEntries = array_lengthof(Offsets64); 240 241 return Offsets64; 242 } else { 243 NumEntries = array_lengthof(Offsets); 244 245 return Offsets; 246 } 247 } 248 249 /// RemoveVRSaveCode - We have found that this function does not need any code 250 /// to manipulate the VRSAVE register, even though it uses vector registers. 251 /// This can happen when the only registers used are known to be live in or out 252 /// of the function. Remove all of the VRSAVE related code from the function. 253 /// FIXME: The removal of the code results in a compile failure at -O0 when the 254 /// function contains a function call, as the GPR containing original VRSAVE 255 /// contents is spilled and reloaded around the call. Without the prolog code, 256 /// the spill instruction refers to an undefined register. This code needs 257 /// to account for all uses of that GPR. 258 static void RemoveVRSaveCode(MachineInstr *MI) { 259 MachineBasicBlock *Entry = MI->getParent(); 260 MachineFunction *MF = Entry->getParent(); 261 262 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 263 MachineBasicBlock::iterator MBBI = MI; 264 ++MBBI; 265 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 266 MBBI->eraseFromParent(); 267 268 bool RemovedAllMTVRSAVEs = true; 269 // See if we can find and remove the MTVRSAVE instruction from all of the 270 // epilog blocks. 271 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 272 // If last instruction is a return instruction, add an epilogue 273 if (I->isReturnBlock()) { 274 bool FoundIt = false; 275 for (MBBI = I->end(); MBBI != I->begin(); ) { 276 --MBBI; 277 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 278 MBBI->eraseFromParent(); // remove it. 279 FoundIt = true; 280 break; 281 } 282 } 283 RemovedAllMTVRSAVEs &= FoundIt; 284 } 285 } 286 287 // If we found and removed all MTVRSAVE instructions, remove the read of 288 // VRSAVE as well. 289 if (RemovedAllMTVRSAVEs) { 290 MBBI = MI; 291 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 292 --MBBI; 293 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 294 MBBI->eraseFromParent(); 295 } 296 297 // Finally, nuke the UPDATE_VRSAVE. 298 MI->eraseFromParent(); 299 } 300 301 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 302 // instruction selector. Based on the vector registers that have been used, 303 // transform this into the appropriate ORI instruction. 304 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 305 MachineFunction *MF = MI->getParent()->getParent(); 306 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 307 DebugLoc dl = MI->getDebugLoc(); 308 309 const MachineRegisterInfo &MRI = MF->getRegInfo(); 310 unsigned UsedRegMask = 0; 311 for (unsigned i = 0; i != 32; ++i) 312 if (MRI.isPhysRegModified(VRRegNo[i])) 313 UsedRegMask |= 1 << (31-i); 314 315 // Live in and live out values already must be in the mask, so don't bother 316 // marking them. 317 for (MachineRegisterInfo::livein_iterator 318 I = MF->getRegInfo().livein_begin(), 319 E = MF->getRegInfo().livein_end(); I != E; ++I) { 320 unsigned RegNo = TRI->getEncodingValue(I->first); 321 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 322 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 323 } 324 325 // Live out registers appear as use operands on return instructions. 326 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 327 UsedRegMask != 0 && BI != BE; ++BI) { 328 const MachineBasicBlock &MBB = *BI; 329 if (!MBB.isReturnBlock()) 330 continue; 331 const MachineInstr &Ret = MBB.back(); 332 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 333 const MachineOperand &MO = Ret.getOperand(I); 334 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 335 continue; 336 unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 337 UsedRegMask &= ~(1 << (31-RegNo)); 338 } 339 } 340 341 // If no registers are used, turn this into a copy. 342 if (UsedRegMask == 0) { 343 // Remove all VRSAVE code. 344 RemoveVRSaveCode(MI); 345 return; 346 } 347 348 unsigned SrcReg = MI->getOperand(1).getReg(); 349 unsigned DstReg = MI->getOperand(0).getReg(); 350 351 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 352 if (DstReg != SrcReg) 353 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 354 .addReg(SrcReg) 355 .addImm(UsedRegMask); 356 else 357 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 358 .addReg(SrcReg, RegState::Kill) 359 .addImm(UsedRegMask); 360 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 361 if (DstReg != SrcReg) 362 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 363 .addReg(SrcReg) 364 .addImm(UsedRegMask >> 16); 365 else 366 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 367 .addReg(SrcReg, RegState::Kill) 368 .addImm(UsedRegMask >> 16); 369 } else { 370 if (DstReg != SrcReg) 371 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 372 .addReg(SrcReg) 373 .addImm(UsedRegMask >> 16); 374 else 375 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 376 .addReg(SrcReg, RegState::Kill) 377 .addImm(UsedRegMask >> 16); 378 379 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 380 .addReg(DstReg, RegState::Kill) 381 .addImm(UsedRegMask & 0xFFFF); 382 } 383 384 // Remove the old UPDATE_VRSAVE instruction. 385 MI->eraseFromParent(); 386 } 387 388 static bool spillsCR(const MachineFunction &MF) { 389 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 390 return FuncInfo->isCRSpilled(); 391 } 392 393 static bool spillsVRSAVE(const MachineFunction &MF) { 394 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 395 return FuncInfo->isVRSAVESpilled(); 396 } 397 398 static bool hasSpills(const MachineFunction &MF) { 399 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 400 return FuncInfo->hasSpills(); 401 } 402 403 static bool hasNonRISpills(const MachineFunction &MF) { 404 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 405 return FuncInfo->hasNonRISpills(); 406 } 407 408 /// MustSaveLR - Return true if this function requires that we save the LR 409 /// register onto the stack in the prolog and restore it in the epilog of the 410 /// function. 411 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 412 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 413 414 // We need a save/restore of LR if there is any def of LR (which is 415 // defined by calls, including the PIC setup sequence), or if there is 416 // some use of the LR stack slot (e.g. for builtin_return_address). 417 // (LR comes in 32 and 64 bit versions.) 418 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 419 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 420 } 421 422 /// determineFrameLayout - Determine the size of the frame and maximum call 423 /// frame size. 424 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 425 bool UpdateMF, 426 bool UseEstimate) const { 427 MachineFrameInfo *MFI = MF.getFrameInfo(); 428 429 // Get the number of bytes to allocate from the FrameInfo 430 unsigned FrameSize = 431 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 432 433 // Get stack alignments. The frame must be aligned to the greatest of these: 434 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI 435 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame 436 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1; 437 438 const PPCRegisterInfo *RegInfo = 439 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 440 441 // If we are a leaf function, and use up to 224 bytes of stack space, 442 // don't have a frame pointer, calls, or dynamic alloca then we do not need 443 // to adjust the stack pointer (we fit in the Red Zone). 444 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 445 // stackless code if all local vars are reg-allocated. 446 bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone); 447 unsigned LR = RegInfo->getRARegister(); 448 if (!DisableRedZone && 449 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 450 !Subtarget.isSVR4ABI() || // allocated locals. 451 FrameSize == 0) && 452 FrameSize <= 224 && // Fits in red zone. 453 !MFI->hasVarSizedObjects() && // No dynamic alloca. 454 !MFI->adjustsStack() && // No calls. 455 !MustSaveLR(MF, LR) && 456 !RegInfo->hasBasePointer(MF)) { // No special alignment. 457 // No need for frame 458 if (UpdateMF) 459 MFI->setStackSize(0); 460 return 0; 461 } 462 463 // Get the maximum call frame size of all the calls. 464 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 465 466 // Maximum call frame needs to be at least big enough for linkage area. 467 unsigned minCallFrameSize = getLinkageSize(); 468 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 469 470 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 471 // that allocations will be aligned. 472 if (MFI->hasVarSizedObjects()) 473 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 474 475 // Update maximum call frame size. 476 if (UpdateMF) 477 MFI->setMaxCallFrameSize(maxCallFrameSize); 478 479 // Include call frame size in total. 480 FrameSize += maxCallFrameSize; 481 482 // Make sure the frame is aligned. 483 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 484 485 // Update frame info. 486 if (UpdateMF) 487 MFI->setStackSize(FrameSize); 488 489 return FrameSize; 490 } 491 492 // hasFP - Return true if the specified function actually has a dedicated frame 493 // pointer register. 494 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 495 const MachineFrameInfo *MFI = MF.getFrameInfo(); 496 // FIXME: This is pretty much broken by design: hasFP() might be called really 497 // early, before the stack layout was calculated and thus hasFP() might return 498 // true or false here depending on the time of call. 499 return (MFI->getStackSize()) && needsFP(MF); 500 } 501 502 // needsFP - Return true if the specified function should have a dedicated frame 503 // pointer register. This is true if the function has variable sized allocas or 504 // if frame pointer elimination is disabled. 505 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 506 const MachineFrameInfo *MFI = MF.getFrameInfo(); 507 508 // Naked functions have no stack frame pushed, so we don't have a frame 509 // pointer. 510 if (MF.getFunction()->hasFnAttribute(Attribute::Naked)) 511 return false; 512 513 return MF.getTarget().Options.DisableFramePointerElim(MF) || 514 MFI->hasVarSizedObjects() || 515 MFI->hasStackMap() || MFI->hasPatchPoint() || 516 (MF.getTarget().Options.GuaranteedTailCallOpt && 517 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 518 } 519 520 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 521 bool is31 = needsFP(MF); 522 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 523 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 524 525 const PPCRegisterInfo *RegInfo = 526 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 527 bool HasBP = RegInfo->hasBasePointer(MF); 528 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; 529 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg; 530 531 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 532 BI != BE; ++BI) 533 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 534 --MBBI; 535 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 536 MachineOperand &MO = MBBI->getOperand(I); 537 if (!MO.isReg()) 538 continue; 539 540 switch (MO.getReg()) { 541 case PPC::FP: 542 MO.setReg(FPReg); 543 break; 544 case PPC::FP8: 545 MO.setReg(FP8Reg); 546 break; 547 case PPC::BP: 548 MO.setReg(BPReg); 549 break; 550 case PPC::BP8: 551 MO.setReg(BP8Reg); 552 break; 553 554 } 555 } 556 } 557 } 558 559 /* This function will do the following: 560 - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12 561 respectively (defaults recommended by the ABI) and return true 562 - If MBB is not an entry block, initialize the register scavenger and look 563 for available registers. 564 - If the defaults (R0/R12) are available, return true 565 - If TwoUniqueRegsRequired is set to true, it looks for two unique 566 registers. Otherwise, look for a single available register. 567 - If the required registers are found, set SR1 and SR2 and return true. 568 - If the required registers are not found, set SR2 or both SR1 and SR2 to 569 PPC::NoRegister and return false. 570 571 Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired 572 is not set, this function will attempt to find two different registers, but 573 still return true if only one register is available (and set SR1 == SR2). 574 */ 575 bool 576 PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, 577 bool UseAtEnd, 578 bool TwoUniqueRegsRequired, 579 unsigned *SR1, 580 unsigned *SR2) const { 581 RegScavenger RS; 582 unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0; 583 unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; 584 585 // Set the defaults for the two scratch registers. 586 if (SR1) 587 *SR1 = R0; 588 589 if (SR2) { 590 assert (SR1 && "Asking for the second scratch register but not the first?"); 591 *SR2 = R12; 592 } 593 594 // If MBB is an entry or exit block, use R0 and R12 as the scratch registers. 595 if ((UseAtEnd && MBB->isReturnBlock()) || 596 (!UseAtEnd && (&MBB->getParent()->front() == MBB))) 597 return true; 598 599 RS.enterBasicBlock(*MBB); 600 601 if (UseAtEnd && !MBB->empty()) { 602 // The scratch register will be used at the end of the block, so must 603 // consider all registers used within the block 604 605 MachineBasicBlock::iterator MBBI = MBB->getFirstTerminator(); 606 // If no terminator, back iterator up to previous instruction. 607 if (MBBI == MBB->end()) 608 MBBI = std::prev(MBBI); 609 610 if (MBBI != MBB->begin()) 611 RS.forward(MBBI); 612 } 613 614 // If the two registers are available, we're all good. 615 // Note that we only return here if both R0 and R12 are available because 616 // although the function may not require two unique registers, it may benefit 617 // from having two so we should try to provide them. 618 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) 619 return true; 620 621 // Get the list of callee-saved registers for the target. 622 const PPCRegisterInfo *RegInfo = 623 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 624 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); 625 626 // Get all the available registers in the block. 627 BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass : 628 &PPC::GPRCRegClass); 629 630 // We shouldn't use callee-saved registers as scratch registers as they may be 631 // available when looking for a candidate block for shrink wrapping but not 632 // available when the actual prologue/epilogue is being emitted because they 633 // were added as live-in to the prologue block by PrologueEpilogueInserter. 634 for (int i = 0; CSRegs[i]; ++i) 635 BV.reset(CSRegs[i]); 636 637 // Set the first scratch register to the first available one. 638 if (SR1) { 639 int FirstScratchReg = BV.find_first(); 640 *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg; 641 } 642 643 // If there is another one available, set the second scratch register to that. 644 // Otherwise, set it to either PPC::NoRegister if this function requires two 645 // or to whatever SR1 is set to if this function doesn't require two. 646 if (SR2) { 647 int SecondScratchReg = BV.find_next(*SR1); 648 if (SecondScratchReg != -1) 649 *SR2 = SecondScratchReg; 650 else 651 *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1; 652 } 653 654 // Now that we've done our best to provide both registers, double check 655 // whether we were unable to provide enough. 656 if (BV.count() < (TwoUniqueRegsRequired ? 2U : 1U)) 657 return false; 658 659 return true; 660 } 661 662 // We need a scratch register for spilling LR and for spilling CR. By default, 663 // we use two scratch registers to hide latency. However, if only one scratch 664 // register is available, we can adjust for that by not overlapping the spill 665 // code. However, if we need to realign the stack (i.e. have a base pointer) 666 // and the stack frame is large, we need two scratch registers. 667 bool 668 PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const { 669 const PPCRegisterInfo *RegInfo = 670 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 671 MachineFunction &MF = *(MBB->getParent()); 672 bool HasBP = RegInfo->hasBasePointer(MF); 673 unsigned FrameSize = determineFrameLayout(MF, false); 674 int NegFrameSize = -FrameSize; 675 bool IsLargeFrame = !isInt<16>(NegFrameSize); 676 MachineFrameInfo *MFI = MF.getFrameInfo(); 677 unsigned MaxAlign = MFI->getMaxAlignment(); 678 679 return IsLargeFrame && HasBP && MaxAlign > 1; 680 } 681 682 bool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { 683 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 684 685 return findScratchRegister(TmpMBB, false, 686 twoUniqueScratchRegsRequired(TmpMBB)); 687 } 688 689 bool PPCFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { 690 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 691 692 return findScratchRegister(TmpMBB, true); 693 } 694 695 void PPCFrameLowering::emitPrologue(MachineFunction &MF, 696 MachineBasicBlock &MBB) const { 697 MachineBasicBlock::iterator MBBI = MBB.begin(); 698 MachineFrameInfo *MFI = MF.getFrameInfo(); 699 const PPCInstrInfo &TII = 700 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 701 const PPCRegisterInfo *RegInfo = 702 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 703 704 MachineModuleInfo &MMI = MF.getMMI(); 705 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 706 DebugLoc dl; 707 bool needsCFI = MMI.hasDebugInfo() || 708 MF.getFunction()->needsUnwindTableEntry(); 709 710 // Get processor type. 711 bool isPPC64 = Subtarget.isPPC64(); 712 // Get the ABI. 713 bool isSVR4ABI = Subtarget.isSVR4ABI(); 714 bool isELFv2ABI = Subtarget.isELFv2ABI(); 715 assert((Subtarget.isDarwinABI() || isSVR4ABI) && 716 "Currently only Darwin and SVR4 ABIs are supported for PowerPC."); 717 718 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 719 // process it. 720 if (!isSVR4ABI) 721 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 722 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 723 HandleVRSaveUpdate(MBBI, TII); 724 break; 725 } 726 } 727 728 // Move MBBI back to the beginning of the prologue block. 729 MBBI = MBB.begin(); 730 731 // Work out frame sizes. 732 unsigned FrameSize = determineFrameLayout(MF); 733 int NegFrameSize = -FrameSize; 734 if (!isInt<32>(NegFrameSize)) 735 llvm_unreachable("Unhandled stack size!"); 736 737 if (MFI->isFrameAddressTaken()) 738 replaceFPWithRealFP(MF); 739 740 // Check if the link register (LR) must be saved. 741 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 742 bool MustSaveLR = FI->mustSaveLR(); 743 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 744 bool MustSaveCR = !MustSaveCRs.empty(); 745 // Do we have a frame pointer and/or base pointer for this function? 746 bool HasFP = hasFP(MF); 747 bool HasBP = RegInfo->hasBasePointer(MF); 748 749 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 750 unsigned BPReg = RegInfo->getBaseRegister(MF); 751 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 752 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR; 753 unsigned ScratchReg = 0; 754 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 755 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.) 756 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 757 : PPC::MFLR ); 758 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD 759 : PPC::STW ); 760 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU 761 : PPC::STWU ); 762 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX 763 : PPC::STWUX); 764 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8 765 : PPC::LIS ); 766 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 767 : PPC::ORI ); 768 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 769 : PPC::OR ); 770 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8 771 : PPC::SUBFC); 772 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8 773 : PPC::SUBFIC); 774 775 // Regarding this assert: Even though LR is saved in the caller's frame (i.e., 776 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no 777 // Red Zone, an asynchronous event (a form of "callee") could claim a frame & 778 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR. 779 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && 780 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); 781 782 // Using the same bool variable as below to supress compiler warnings. 783 bool SingleScratchReg = 784 findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB), 785 &ScratchReg, &TempReg); 786 assert(SingleScratchReg && 787 "Required number of registers not available in this block"); 788 789 SingleScratchReg = ScratchReg == TempReg; 790 791 int LROffset = getReturnSaveOffset(); 792 793 int FPOffset = 0; 794 if (HasFP) { 795 if (isSVR4ABI) { 796 MachineFrameInfo *FFI = MF.getFrameInfo(); 797 int FPIndex = FI->getFramePointerSaveIndex(); 798 assert(FPIndex && "No Frame Pointer Save Slot!"); 799 FPOffset = FFI->getObjectOffset(FPIndex); 800 } else { 801 FPOffset = getFramePointerSaveOffset(); 802 } 803 } 804 805 int BPOffset = 0; 806 if (HasBP) { 807 if (isSVR4ABI) { 808 MachineFrameInfo *FFI = MF.getFrameInfo(); 809 int BPIndex = FI->getBasePointerSaveIndex(); 810 assert(BPIndex && "No Base Pointer Save Slot!"); 811 BPOffset = FFI->getObjectOffset(BPIndex); 812 } else { 813 BPOffset = getBasePointerSaveOffset(); 814 } 815 } 816 817 int PBPOffset = 0; 818 if (FI->usesPICBase()) { 819 MachineFrameInfo *FFI = MF.getFrameInfo(); 820 int PBPIndex = FI->getPICBasePointerSaveIndex(); 821 assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 822 PBPOffset = FFI->getObjectOffset(PBPIndex); 823 } 824 825 // Get stack alignments. 826 unsigned MaxAlign = MFI->getMaxAlignment(); 827 if (HasBP && MaxAlign > 1) 828 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 829 "Invalid alignment!"); 830 831 // Frames of 32KB & larger require special handling because they cannot be 832 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand. 833 bool isLargeFrame = !isInt<16>(NegFrameSize); 834 835 assert((isPPC64 || !MustSaveCR) && 836 "Prologue CR saving supported only in 64-bit mode"); 837 838 // If we need to spill the CR and the LR but we don't have two separate 839 // registers available, we must spill them one at a time 840 if (MustSaveCR && SingleScratchReg && MustSaveLR) { 841 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. 842 // If only one or two CR fields are clobbered, it could be more 843 // efficient to use mfocrf to selectively save just those fields. 844 MachineInstrBuilder MIB = 845 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); 846 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 847 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 848 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 849 .addReg(TempReg, getKillRegState(true)) 850 .addImm(8) 851 .addReg(SPReg); 852 } 853 854 if (MustSaveLR) 855 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); 856 857 if (MustSaveCR && 858 !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64 859 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. 860 // If only one or two CR fields are clobbered, it could be more 861 // efficient to use mfocrf to selectively save just those fields. 862 MachineInstrBuilder MIB = 863 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); 864 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 865 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 866 } 867 868 if (HasFP) 869 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 870 BuildMI(MBB, MBBI, dl, StoreInst) 871 .addReg(FPReg) 872 .addImm(FPOffset) 873 .addReg(SPReg); 874 875 if (FI->usesPICBase()) 876 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 877 BuildMI(MBB, MBBI, dl, StoreInst) 878 .addReg(PPC::R30) 879 .addImm(PBPOffset) 880 .addReg(SPReg); 881 882 if (HasBP) 883 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 884 BuildMI(MBB, MBBI, dl, StoreInst) 885 .addReg(BPReg) 886 .addImm(BPOffset) 887 .addReg(SPReg); 888 889 if (MustSaveLR) 890 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 891 BuildMI(MBB, MBBI, dl, StoreInst) 892 .addReg(ScratchReg) 893 .addImm(LROffset) 894 .addReg(SPReg); 895 896 if (MustSaveCR && 897 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 898 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 899 .addReg(TempReg, getKillRegState(true)) 900 .addImm(8) 901 .addReg(SPReg); 902 903 // Skip the rest if this is a leaf function & all spills fit in the Red Zone. 904 if (!FrameSize) return; 905 906 // Adjust stack pointer: r1 += NegFrameSize. 907 // If there is a preferred stack alignment, align R1 now 908 909 if (HasBP) { 910 // Save a copy of r1 as the base pointer. 911 BuildMI(MBB, MBBI, dl, OrInst, BPReg) 912 .addReg(SPReg) 913 .addReg(SPReg); 914 } 915 916 // This condition must be kept in sync with canUseAsPrologue. 917 if (HasBP && MaxAlign > 1) { 918 if (isPPC64) 919 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) 920 .addReg(SPReg) 921 .addImm(0) 922 .addImm(64 - Log2_32(MaxAlign)); 923 else // PPC32... 924 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg) 925 .addReg(SPReg) 926 .addImm(0) 927 .addImm(32 - Log2_32(MaxAlign)) 928 .addImm(31); 929 if (!isLargeFrame) { 930 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg) 931 .addReg(ScratchReg, RegState::Kill) 932 .addImm(NegFrameSize); 933 } else { 934 assert(!SingleScratchReg && "Only a single scratch reg available"); 935 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) 936 .addImm(NegFrameSize >> 16); 937 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg) 938 .addReg(TempReg, RegState::Kill) 939 .addImm(NegFrameSize & 0xFFFF); 940 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg) 941 .addReg(ScratchReg, RegState::Kill) 942 .addReg(TempReg, RegState::Kill); 943 } 944 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 945 .addReg(SPReg, RegState::Kill) 946 .addReg(SPReg) 947 .addReg(ScratchReg); 948 949 } else if (!isLargeFrame) { 950 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg) 951 .addReg(SPReg) 952 .addImm(NegFrameSize) 953 .addReg(SPReg); 954 955 } else { 956 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 957 .addImm(NegFrameSize >> 16); 958 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 959 .addReg(ScratchReg, RegState::Kill) 960 .addImm(NegFrameSize & 0xFFFF); 961 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 962 .addReg(SPReg, RegState::Kill) 963 .addReg(SPReg) 964 .addReg(ScratchReg); 965 } 966 967 // Add Call Frame Information for the instructions we generated above. 968 if (needsCFI) { 969 unsigned CFIIndex; 970 971 if (HasBP) { 972 // Define CFA in terms of BP. Do this in preference to using FP/SP, 973 // because if the stack needed aligning then CFA won't be at a fixed 974 // offset from FP/SP. 975 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 976 CFIIndex = MMI.addFrameInst( 977 MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 978 } else { 979 // Adjust the definition of CFA to account for the change in SP. 980 assert(NegFrameSize); 981 CFIIndex = MMI.addFrameInst( 982 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize)); 983 } 984 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 985 .addCFIIndex(CFIIndex); 986 987 if (HasFP) { 988 // Describe where FP was saved, at a fixed offset from CFA. 989 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 990 CFIIndex = MMI.addFrameInst( 991 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset)); 992 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 993 .addCFIIndex(CFIIndex); 994 } 995 996 if (FI->usesPICBase()) { 997 // Describe where FP was saved, at a fixed offset from CFA. 998 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true); 999 CFIIndex = MMI.addFrameInst( 1000 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset)); 1001 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1002 .addCFIIndex(CFIIndex); 1003 } 1004 1005 if (HasBP) { 1006 // Describe where BP was saved, at a fixed offset from CFA. 1007 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 1008 CFIIndex = MMI.addFrameInst( 1009 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset)); 1010 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1011 .addCFIIndex(CFIIndex); 1012 } 1013 1014 if (MustSaveLR) { 1015 // Describe where LR was saved, at a fixed offset from CFA. 1016 unsigned Reg = MRI->getDwarfRegNum(LRReg, true); 1017 CFIIndex = MMI.addFrameInst( 1018 MCCFIInstruction::createOffset(nullptr, Reg, LROffset)); 1019 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1020 .addCFIIndex(CFIIndex); 1021 } 1022 } 1023 1024 // If there is a frame pointer, copy R1 into R31 1025 if (HasFP) { 1026 BuildMI(MBB, MBBI, dl, OrInst, FPReg) 1027 .addReg(SPReg) 1028 .addReg(SPReg); 1029 1030 if (!HasBP && needsCFI) { 1031 // Change the definition of CFA from SP+offset to FP+offset, because SP 1032 // will change at every alloca. 1033 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 1034 unsigned CFIIndex = MMI.addFrameInst( 1035 MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 1036 1037 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1038 .addCFIIndex(CFIIndex); 1039 } 1040 } 1041 1042 if (needsCFI) { 1043 // Describe where callee saved registers were saved, at fixed offsets from 1044 // CFA. 1045 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1046 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1047 unsigned Reg = CSI[I].getReg(); 1048 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 1049 1050 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 1051 // subregisters of CR2. We just need to emit a move of CR2. 1052 if (PPC::CRBITRCRegClass.contains(Reg)) 1053 continue; 1054 1055 // For SVR4, don't emit a move for the CR spill slot if we haven't 1056 // spilled CRs. 1057 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 1058 && !MustSaveCR) 1059 continue; 1060 1061 // For 64-bit SVR4 when we have spilled CRs, the spill location 1062 // is SP+8, not a frame-relative slot. 1063 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1064 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for 1065 // the whole CR word. In the ELFv2 ABI, every CR that was 1066 // actually saved gets its own CFI record. 1067 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2; 1068 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1069 nullptr, MRI->getDwarfRegNum(CRReg, true), 8)); 1070 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1071 .addCFIIndex(CFIIndex); 1072 continue; 1073 } 1074 1075 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1076 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1077 nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); 1078 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1079 .addCFIIndex(CFIIndex); 1080 } 1081 } 1082 } 1083 1084 void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 1085 MachineBasicBlock &MBB) const { 1086 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 1087 DebugLoc dl; 1088 1089 if (MBBI != MBB.end()) 1090 dl = MBBI->getDebugLoc(); 1091 1092 const PPCInstrInfo &TII = 1093 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1094 const PPCRegisterInfo *RegInfo = 1095 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1096 1097 // Get alignment info so we know how to restore the SP. 1098 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1099 1100 // Get the number of bytes allocated from the FrameInfo. 1101 int FrameSize = MFI->getStackSize(); 1102 1103 // Get processor type. 1104 bool isPPC64 = Subtarget.isPPC64(); 1105 // Get the ABI. 1106 bool isSVR4ABI = Subtarget.isSVR4ABI(); 1107 1108 // Check if the link register (LR) has been saved. 1109 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1110 bool MustSaveLR = FI->mustSaveLR(); 1111 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 1112 bool MustSaveCR = !MustSaveCRs.empty(); 1113 // Do we have a frame pointer and/or base pointer for this function? 1114 bool HasFP = hasFP(MF); 1115 bool HasBP = RegInfo->hasBasePointer(MF); 1116 1117 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 1118 unsigned BPReg = RegInfo->getBaseRegister(MF); 1119 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 1120 unsigned ScratchReg = 0; 1121 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 1122 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 1123 : PPC::MTLR ); 1124 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD 1125 : PPC::LWZ ); 1126 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8 1127 : PPC::LIS ); 1128 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 1129 : PPC::ORI ); 1130 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8 1131 : PPC::ADDI ); 1132 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 1133 : PPC::ADD4 ); 1134 1135 int LROffset = getReturnSaveOffset(); 1136 1137 int FPOffset = 0; 1138 1139 // Using the same bool variable as below to supress compiler warnings. 1140 bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg, 1141 &TempReg); 1142 assert(SingleScratchReg && 1143 "Could not find an available scratch register"); 1144 1145 SingleScratchReg = ScratchReg == TempReg; 1146 1147 if (HasFP) { 1148 if (isSVR4ABI) { 1149 MachineFrameInfo *FFI = MF.getFrameInfo(); 1150 int FPIndex = FI->getFramePointerSaveIndex(); 1151 assert(FPIndex && "No Frame Pointer Save Slot!"); 1152 FPOffset = FFI->getObjectOffset(FPIndex); 1153 } else { 1154 FPOffset = getFramePointerSaveOffset(); 1155 } 1156 } 1157 1158 int BPOffset = 0; 1159 if (HasBP) { 1160 if (isSVR4ABI) { 1161 MachineFrameInfo *FFI = MF.getFrameInfo(); 1162 int BPIndex = FI->getBasePointerSaveIndex(); 1163 assert(BPIndex && "No Base Pointer Save Slot!"); 1164 BPOffset = FFI->getObjectOffset(BPIndex); 1165 } else { 1166 BPOffset = getBasePointerSaveOffset(); 1167 } 1168 } 1169 1170 int PBPOffset = 0; 1171 if (FI->usesPICBase()) { 1172 MachineFrameInfo *FFI = MF.getFrameInfo(); 1173 int PBPIndex = FI->getPICBasePointerSaveIndex(); 1174 assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 1175 PBPOffset = FFI->getObjectOffset(PBPIndex); 1176 } 1177 1178 bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn()); 1179 1180 if (IsReturnBlock) { 1181 unsigned RetOpcode = MBBI->getOpcode(); 1182 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1183 RetOpcode == PPC::TCRETURNdi || 1184 RetOpcode == PPC::TCRETURNai || 1185 RetOpcode == PPC::TCRETURNri8 || 1186 RetOpcode == PPC::TCRETURNdi8 || 1187 RetOpcode == PPC::TCRETURNai8; 1188 1189 if (UsesTCRet) { 1190 int MaxTCRetDelta = FI->getTailCallSPDelta(); 1191 MachineOperand &StackAdjust = MBBI->getOperand(1); 1192 assert(StackAdjust.isImm() && "Expecting immediate value."); 1193 // Adjust stack pointer. 1194 int StackAdj = StackAdjust.getImm(); 1195 int Delta = StackAdj - MaxTCRetDelta; 1196 assert((Delta >= 0) && "Delta must be positive"); 1197 if (MaxTCRetDelta>0) 1198 FrameSize += (StackAdj +Delta); 1199 else 1200 FrameSize += StackAdj; 1201 } 1202 } 1203 1204 // Frames of 32KB & larger require special handling because they cannot be 1205 // indexed into with a simple LD/LWZ immediate offset operand. 1206 bool isLargeFrame = !isInt<16>(FrameSize); 1207 1208 if (FrameSize) { 1209 // In the prologue, the loaded (or persistent) stack pointer value is offset 1210 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now. 1211 1212 // If this function contained a fastcc call and GuaranteedTailCallOpt is 1213 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1214 // call which invalidates the stack pointer value in SP(0). So we use the 1215 // value of R31 in this case. 1216 if (FI->hasFastCall()) { 1217 assert(HasFP && "Expecting a valid frame pointer."); 1218 if (!isLargeFrame) { 1219 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1220 .addReg(FPReg).addImm(FrameSize); 1221 } else { 1222 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1223 .addImm(FrameSize >> 16); 1224 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1225 .addReg(ScratchReg, RegState::Kill) 1226 .addImm(FrameSize & 0xFFFF); 1227 BuildMI(MBB, MBBI, dl, AddInst) 1228 .addReg(SPReg) 1229 .addReg(FPReg) 1230 .addReg(ScratchReg); 1231 } 1232 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) { 1233 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1234 .addReg(SPReg) 1235 .addImm(FrameSize); 1236 } else { 1237 BuildMI(MBB, MBBI, dl, LoadInst, SPReg) 1238 .addImm(0) 1239 .addReg(SPReg); 1240 } 1241 } 1242 1243 assert((isPPC64 || !MustSaveCR) && 1244 "Epilogue CR restoring supported only in 64-bit mode"); 1245 1246 // If we need to save both the LR and the CR and we only have one available 1247 // scratch register, we must do them one at a time. 1248 if (MustSaveCR && SingleScratchReg && MustSaveLR) { 1249 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 1250 .addImm(8) 1251 .addReg(SPReg); 1252 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1253 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1254 .addReg(TempReg, getKillRegState(i == e-1)); 1255 } 1256 1257 if (MustSaveLR) 1258 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) 1259 .addImm(LROffset) 1260 .addReg(SPReg); 1261 1262 if (MustSaveCR && 1263 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 1264 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 1265 .addImm(8) 1266 .addReg(SPReg); 1267 1268 if (HasFP) 1269 BuildMI(MBB, MBBI, dl, LoadInst, FPReg) 1270 .addImm(FPOffset) 1271 .addReg(SPReg); 1272 1273 if (FI->usesPICBase()) 1274 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 1275 BuildMI(MBB, MBBI, dl, LoadInst) 1276 .addReg(PPC::R30) 1277 .addImm(PBPOffset) 1278 .addReg(SPReg); 1279 1280 if (HasBP) 1281 BuildMI(MBB, MBBI, dl, LoadInst, BPReg) 1282 .addImm(BPOffset) 1283 .addReg(SPReg); 1284 1285 if (MustSaveCR && 1286 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 1287 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1288 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1289 .addReg(TempReg, getKillRegState(i == e-1)); 1290 1291 if (MustSaveLR) 1292 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg); 1293 1294 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1295 // call optimization 1296 if (IsReturnBlock) { 1297 unsigned RetOpcode = MBBI->getOpcode(); 1298 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1299 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) && 1300 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1301 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1302 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1303 1304 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 1305 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1306 .addReg(SPReg).addImm(CallerAllocatedAmt); 1307 } else { 1308 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1309 .addImm(CallerAllocatedAmt >> 16); 1310 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1311 .addReg(ScratchReg, RegState::Kill) 1312 .addImm(CallerAllocatedAmt & 0xFFFF); 1313 BuildMI(MBB, MBBI, dl, AddInst) 1314 .addReg(SPReg) 1315 .addReg(FPReg) 1316 .addReg(ScratchReg); 1317 } 1318 } else { 1319 createTailCallBranchInstr(MBB); 1320 } 1321 } 1322 } 1323 1324 void PPCFrameLowering::createTailCallBranchInstr(MachineBasicBlock &MBB) const { 1325 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 1326 DebugLoc dl; 1327 1328 if (MBBI != MBB.end()) 1329 dl = MBBI->getDebugLoc(); 1330 1331 const PPCInstrInfo &TII = 1332 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1333 1334 // Create branch instruction for pseudo tail call return instruction 1335 unsigned RetOpcode = MBBI->getOpcode(); 1336 if (RetOpcode == PPC::TCRETURNdi) { 1337 MBBI = MBB.getLastNonDebugInstr(); 1338 MachineOperand &JumpTarget = MBBI->getOperand(0); 1339 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1340 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1341 } else if (RetOpcode == PPC::TCRETURNri) { 1342 MBBI = MBB.getLastNonDebugInstr(); 1343 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1344 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1345 } else if (RetOpcode == PPC::TCRETURNai) { 1346 MBBI = MBB.getLastNonDebugInstr(); 1347 MachineOperand &JumpTarget = MBBI->getOperand(0); 1348 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1349 } else if (RetOpcode == PPC::TCRETURNdi8) { 1350 MBBI = MBB.getLastNonDebugInstr(); 1351 MachineOperand &JumpTarget = MBBI->getOperand(0); 1352 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1353 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1354 } else if (RetOpcode == PPC::TCRETURNri8) { 1355 MBBI = MBB.getLastNonDebugInstr(); 1356 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1357 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1358 } else if (RetOpcode == PPC::TCRETURNai8) { 1359 MBBI = MBB.getLastNonDebugInstr(); 1360 MachineOperand &JumpTarget = MBBI->getOperand(0); 1361 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1362 } 1363 } 1364 1365 void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF, 1366 BitVector &SavedRegs, 1367 RegScavenger *RS) const { 1368 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 1369 1370 const PPCRegisterInfo *RegInfo = 1371 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1372 1373 // Save and clear the LR state. 1374 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1375 unsigned LR = RegInfo->getRARegister(); 1376 FI->setMustSaveLR(MustSaveLR(MF, LR)); 1377 SavedRegs.reset(LR); 1378 1379 // Save R31 if necessary 1380 int FPSI = FI->getFramePointerSaveIndex(); 1381 bool isPPC64 = Subtarget.isPPC64(); 1382 bool isDarwinABI = Subtarget.isDarwinABI(); 1383 MachineFrameInfo *MFI = MF.getFrameInfo(); 1384 1385 // If the frame pointer save index hasn't been defined yet. 1386 if (!FPSI && needsFP(MF)) { 1387 // Find out what the fix offset of the frame pointer save area. 1388 int FPOffset = getFramePointerSaveOffset(); 1389 // Allocate the frame index for frame pointer save area. 1390 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 1391 // Save the result. 1392 FI->setFramePointerSaveIndex(FPSI); 1393 } 1394 1395 int BPSI = FI->getBasePointerSaveIndex(); 1396 if (!BPSI && RegInfo->hasBasePointer(MF)) { 1397 int BPOffset = getBasePointerSaveOffset(); 1398 // Allocate the frame index for the base pointer save area. 1399 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true); 1400 // Save the result. 1401 FI->setBasePointerSaveIndex(BPSI); 1402 } 1403 1404 // Reserve stack space for the PIC Base register (R30). 1405 // Only used in SVR4 32-bit. 1406 if (FI->usesPICBase()) { 1407 int PBPSI = MFI->CreateFixedObject(4, -8, true); 1408 FI->setPICBasePointerSaveIndex(PBPSI); 1409 } 1410 1411 // Reserve stack space to move the linkage area to in case of a tail call. 1412 int TCSPDelta = 0; 1413 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1414 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 1415 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 1416 } 1417 1418 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 1419 // function uses CR 2, 3, or 4. 1420 if (!isPPC64 && !isDarwinABI && 1421 (SavedRegs.test(PPC::CR2) || 1422 SavedRegs.test(PPC::CR3) || 1423 SavedRegs.test(PPC::CR4))) { 1424 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 1425 FI->setCRSpillFrameIndex(FrameIdx); 1426 } 1427 } 1428 1429 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 1430 RegScavenger *RS) const { 1431 // Early exit if not using the SVR4 ABI. 1432 if (!Subtarget.isSVR4ABI()) { 1433 addScavengingSpillSlot(MF, RS); 1434 return; 1435 } 1436 1437 // Get callee saved register information. 1438 MachineFrameInfo *FFI = MF.getFrameInfo(); 1439 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 1440 1441 // If the function is shrink-wrapped, and if the function has a tail call, the 1442 // tail call might not be in the new RestoreBlock, so real branch instruction 1443 // won't be generated by emitEpilogue(), because shrink-wrap has chosen new 1444 // RestoreBlock. So we handle this case here. 1445 if (FFI->getSavePoint() && FFI->hasTailCall()) { 1446 MachineBasicBlock *RestoreBlock = FFI->getRestorePoint(); 1447 for (MachineBasicBlock &MBB : MF) { 1448 if (MBB.isReturnBlock() && (&MBB) != RestoreBlock) 1449 createTailCallBranchInstr(MBB); 1450 } 1451 } 1452 1453 // Early exit if no callee saved registers are modified! 1454 if (CSI.empty() && !needsFP(MF)) { 1455 addScavengingSpillSlot(MF, RS); 1456 return; 1457 } 1458 1459 unsigned MinGPR = PPC::R31; 1460 unsigned MinG8R = PPC::X31; 1461 unsigned MinFPR = PPC::F31; 1462 unsigned MinVR = PPC::V31; 1463 1464 bool HasGPSaveArea = false; 1465 bool HasG8SaveArea = false; 1466 bool HasFPSaveArea = false; 1467 bool HasVRSAVESaveArea = false; 1468 bool HasVRSaveArea = false; 1469 1470 SmallVector<CalleeSavedInfo, 18> GPRegs; 1471 SmallVector<CalleeSavedInfo, 18> G8Regs; 1472 SmallVector<CalleeSavedInfo, 18> FPRegs; 1473 SmallVector<CalleeSavedInfo, 18> VRegs; 1474 1475 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1476 unsigned Reg = CSI[i].getReg(); 1477 if (PPC::GPRCRegClass.contains(Reg)) { 1478 HasGPSaveArea = true; 1479 1480 GPRegs.push_back(CSI[i]); 1481 1482 if (Reg < MinGPR) { 1483 MinGPR = Reg; 1484 } 1485 } else if (PPC::G8RCRegClass.contains(Reg)) { 1486 HasG8SaveArea = true; 1487 1488 G8Regs.push_back(CSI[i]); 1489 1490 if (Reg < MinG8R) { 1491 MinG8R = Reg; 1492 } 1493 } else if (PPC::F8RCRegClass.contains(Reg)) { 1494 HasFPSaveArea = true; 1495 1496 FPRegs.push_back(CSI[i]); 1497 1498 if (Reg < MinFPR) { 1499 MinFPR = Reg; 1500 } 1501 } else if (PPC::CRBITRCRegClass.contains(Reg) || 1502 PPC::CRRCRegClass.contains(Reg)) { 1503 ; // do nothing, as we already know whether CRs are spilled 1504 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 1505 HasVRSAVESaveArea = true; 1506 } else if (PPC::VRRCRegClass.contains(Reg)) { 1507 HasVRSaveArea = true; 1508 1509 VRegs.push_back(CSI[i]); 1510 1511 if (Reg < MinVR) { 1512 MinVR = Reg; 1513 } 1514 } else { 1515 llvm_unreachable("Unknown RegisterClass!"); 1516 } 1517 } 1518 1519 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1520 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1521 1522 int64_t LowerBound = 0; 1523 1524 // Take into account stack space reserved for tail calls. 1525 int TCSPDelta = 0; 1526 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1527 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1528 LowerBound = TCSPDelta; 1529 } 1530 1531 // The Floating-point register save area is right below the back chain word 1532 // of the previous stack frame. 1533 if (HasFPSaveArea) { 1534 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1535 int FI = FPRegs[i].getFrameIdx(); 1536 1537 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1538 } 1539 1540 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 1541 } 1542 1543 // Check whether the frame pointer register is allocated. If so, make sure it 1544 // is spilled to the correct offset. 1545 if (needsFP(MF)) { 1546 HasGPSaveArea = true; 1547 1548 int FI = PFI->getFramePointerSaveIndex(); 1549 assert(FI && "No Frame Pointer Save Slot!"); 1550 1551 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1552 } 1553 1554 if (PFI->usesPICBase()) { 1555 HasGPSaveArea = true; 1556 1557 int FI = PFI->getPICBasePointerSaveIndex(); 1558 assert(FI && "No PIC Base Pointer Save Slot!"); 1559 1560 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1561 } 1562 1563 const PPCRegisterInfo *RegInfo = 1564 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1565 if (RegInfo->hasBasePointer(MF)) { 1566 HasGPSaveArea = true; 1567 1568 int FI = PFI->getBasePointerSaveIndex(); 1569 assert(FI && "No Base Pointer Save Slot!"); 1570 1571 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1572 } 1573 1574 // General register save area starts right below the Floating-point 1575 // register save area. 1576 if (HasGPSaveArea || HasG8SaveArea) { 1577 // Move general register save area spill slots down, taking into account 1578 // the size of the Floating-point register save area. 1579 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1580 int FI = GPRegs[i].getFrameIdx(); 1581 1582 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1583 } 1584 1585 // Move general register save area spill slots down, taking into account 1586 // the size of the Floating-point register save area. 1587 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1588 int FI = G8Regs[i].getFrameIdx(); 1589 1590 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1591 } 1592 1593 unsigned MinReg = 1594 std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1595 TRI->getEncodingValue(MinG8R)); 1596 1597 if (Subtarget.isPPC64()) { 1598 LowerBound -= (31 - MinReg + 1) * 8; 1599 } else { 1600 LowerBound -= (31 - MinReg + 1) * 4; 1601 } 1602 } 1603 1604 // For 32-bit only, the CR save area is below the general register 1605 // save area. For 64-bit SVR4, the CR save area is addressed relative 1606 // to the stack pointer and hence does not need an adjustment here. 1607 // Only CR2 (the first nonvolatile spilled) has an associated frame 1608 // index so that we have a single uniform save area. 1609 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1610 // Adjust the frame index of the CR spill slot. 1611 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1612 unsigned Reg = CSI[i].getReg(); 1613 1614 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1615 // Leave Darwin logic as-is. 1616 || (!Subtarget.isSVR4ABI() && 1617 (PPC::CRBITRCRegClass.contains(Reg) || 1618 PPC::CRRCRegClass.contains(Reg)))) { 1619 int FI = CSI[i].getFrameIdx(); 1620 1621 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1622 } 1623 } 1624 1625 LowerBound -= 4; // The CR save area is always 4 bytes long. 1626 } 1627 1628 if (HasVRSAVESaveArea) { 1629 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1630 // which have the VRSAVE register class? 1631 // Adjust the frame index of the VRSAVE spill slot. 1632 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1633 unsigned Reg = CSI[i].getReg(); 1634 1635 if (PPC::VRSAVERCRegClass.contains(Reg)) { 1636 int FI = CSI[i].getFrameIdx(); 1637 1638 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1639 } 1640 } 1641 1642 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1643 } 1644 1645 if (HasVRSaveArea) { 1646 // Insert alignment padding, we need 16-byte alignment. 1647 LowerBound = (LowerBound - 15) & ~(15); 1648 1649 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1650 int FI = VRegs[i].getFrameIdx(); 1651 1652 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1653 } 1654 } 1655 1656 addScavengingSpillSlot(MF, RS); 1657 } 1658 1659 void 1660 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1661 RegScavenger *RS) const { 1662 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1663 // a large stack, which will require scavenging a register to materialize a 1664 // large offset. 1665 1666 // We need to have a scavenger spill slot for spills if the frame size is 1667 // large. In case there is no free register for large-offset addressing, 1668 // this slot is used for the necessary emergency spill. Also, we need the 1669 // slot for dynamic stack allocations. 1670 1671 // The scavenger might be invoked if the frame offset does not fit into 1672 // the 16-bit immediate. We don't know the complete frame size here 1673 // because we've not yet computed callee-saved register spills or the 1674 // needed alignment padding. 1675 unsigned StackSize = determineFrameLayout(MF, false, true); 1676 MachineFrameInfo *MFI = MF.getFrameInfo(); 1677 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1678 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1679 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1680 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1681 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1682 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1683 RC->getAlignment(), 1684 false)); 1685 1686 // Might we have over-aligned allocas? 1687 bool HasAlVars = MFI->hasVarSizedObjects() && 1688 MFI->getMaxAlignment() > getStackAlignment(); 1689 1690 // These kinds of spills might need two registers. 1691 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars) 1692 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1693 RC->getAlignment(), 1694 false)); 1695 1696 } 1697 } 1698 1699 bool 1700 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1701 MachineBasicBlock::iterator MI, 1702 const std::vector<CalleeSavedInfo> &CSI, 1703 const TargetRegisterInfo *TRI) const { 1704 1705 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1706 // Return false otherwise to maintain pre-existing behavior. 1707 if (!Subtarget.isSVR4ABI()) 1708 return false; 1709 1710 MachineFunction *MF = MBB.getParent(); 1711 const PPCInstrInfo &TII = 1712 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1713 DebugLoc DL; 1714 bool CRSpilled = false; 1715 MachineInstrBuilder CRMIB; 1716 1717 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1718 unsigned Reg = CSI[i].getReg(); 1719 // Only Darwin actually uses the VRSAVE register, but it can still appear 1720 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1721 // Darwin, ignore it. 1722 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1723 continue; 1724 1725 // CR2 through CR4 are the nonvolatile CR fields. 1726 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1727 1728 // Add the callee-saved register as live-in; it's killed at the spill. 1729 MBB.addLiveIn(Reg); 1730 1731 if (CRSpilled && IsCRField) { 1732 CRMIB.addReg(Reg, RegState::ImplicitKill); 1733 continue; 1734 } 1735 1736 // Insert the spill to the stack frame. 1737 if (IsCRField) { 1738 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1739 if (Subtarget.isPPC64()) { 1740 // The actual spill will happen at the start of the prologue. 1741 FuncInfo->addMustSaveCR(Reg); 1742 } else { 1743 CRSpilled = true; 1744 FuncInfo->setSpillsCR(); 1745 1746 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1747 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1748 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) 1749 .addReg(Reg, RegState::ImplicitKill); 1750 1751 MBB.insert(MI, CRMIB); 1752 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1753 .addReg(PPC::R12, 1754 getKillRegState(true)), 1755 CSI[i].getFrameIdx())); 1756 } 1757 } else { 1758 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1759 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1760 CSI[i].getFrameIdx(), RC, TRI); 1761 } 1762 } 1763 return true; 1764 } 1765 1766 static void 1767 restoreCRs(bool isPPC64, bool is31, 1768 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1769 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1770 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1771 1772 MachineFunction *MF = MBB.getParent(); 1773 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 1774 DebugLoc DL; 1775 unsigned RestoreOp, MoveReg; 1776 1777 if (isPPC64) 1778 // This is handled during epilogue generation. 1779 return; 1780 else { 1781 // 32-bit: FP-relative 1782 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1783 PPC::R12), 1784 CSI[CSIIndex].getFrameIdx())); 1785 RestoreOp = PPC::MTOCRF; 1786 MoveReg = PPC::R12; 1787 } 1788 1789 if (CR2Spilled) 1790 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1791 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1792 1793 if (CR3Spilled) 1794 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1795 .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1796 1797 if (CR4Spilled) 1798 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1799 .addReg(MoveReg, getKillRegState(true))); 1800 } 1801 1802 MachineBasicBlock::iterator PPCFrameLowering:: 1803 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1804 MachineBasicBlock::iterator I) const { 1805 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1806 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1807 I->getOpcode() == PPC::ADJCALLSTACKUP) { 1808 // Add (actually subtract) back the amount the callee popped on return. 1809 if (int CalleeAmt = I->getOperand(1).getImm()) { 1810 bool is64Bit = Subtarget.isPPC64(); 1811 CalleeAmt *= -1; 1812 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1813 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1814 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1815 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1816 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1817 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1818 MachineInstr *MI = I; 1819 DebugLoc dl = MI->getDebugLoc(); 1820 1821 if (isInt<16>(CalleeAmt)) { 1822 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1823 .addReg(StackReg, RegState::Kill) 1824 .addImm(CalleeAmt); 1825 } else { 1826 MachineBasicBlock::iterator MBBI = I; 1827 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1828 .addImm(CalleeAmt >> 16); 1829 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1830 .addReg(TmpReg, RegState::Kill) 1831 .addImm(CalleeAmt & 0xFFFF); 1832 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1833 .addReg(StackReg, RegState::Kill) 1834 .addReg(TmpReg); 1835 } 1836 } 1837 } 1838 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1839 return MBB.erase(I); 1840 } 1841 1842 bool 1843 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1844 MachineBasicBlock::iterator MI, 1845 const std::vector<CalleeSavedInfo> &CSI, 1846 const TargetRegisterInfo *TRI) const { 1847 1848 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1849 // Return false otherwise to maintain pre-existing behavior. 1850 if (!Subtarget.isSVR4ABI()) 1851 return false; 1852 1853 MachineFunction *MF = MBB.getParent(); 1854 const PPCInstrInfo &TII = 1855 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1856 bool CR2Spilled = false; 1857 bool CR3Spilled = false; 1858 bool CR4Spilled = false; 1859 unsigned CSIIndex = 0; 1860 1861 // Initialize insertion-point logic; we will be restoring in reverse 1862 // order of spill. 1863 MachineBasicBlock::iterator I = MI, BeforeI = I; 1864 bool AtStart = I == MBB.begin(); 1865 1866 if (!AtStart) 1867 --BeforeI; 1868 1869 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1870 unsigned Reg = CSI[i].getReg(); 1871 1872 // Only Darwin actually uses the VRSAVE register, but it can still appear 1873 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1874 // Darwin, ignore it. 1875 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1876 continue; 1877 1878 if (Reg == PPC::CR2) { 1879 CR2Spilled = true; 1880 // The spill slot is associated only with CR2, which is the 1881 // first nonvolatile spilled. Save it here. 1882 CSIIndex = i; 1883 continue; 1884 } else if (Reg == PPC::CR3) { 1885 CR3Spilled = true; 1886 continue; 1887 } else if (Reg == PPC::CR4) { 1888 CR4Spilled = true; 1889 continue; 1890 } else { 1891 // When we first encounter a non-CR register after seeing at 1892 // least one CR register, restore all spilled CRs together. 1893 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1894 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1895 bool is31 = needsFP(*MF); 1896 restoreCRs(Subtarget.isPPC64(), is31, 1897 CR2Spilled, CR3Spilled, CR4Spilled, 1898 MBB, I, CSI, CSIIndex); 1899 CR2Spilled = CR3Spilled = CR4Spilled = false; 1900 } 1901 1902 // Default behavior for non-CR saves. 1903 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1904 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1905 RC, TRI); 1906 assert(I != MBB.begin() && 1907 "loadRegFromStackSlot didn't insert any code!"); 1908 } 1909 1910 // Insert in reverse order. 1911 if (AtStart) 1912 I = MBB.begin(); 1913 else { 1914 I = BeforeI; 1915 ++I; 1916 } 1917 } 1918 1919 // If we haven't yet spilled the CRs, do so now. 1920 if (CR2Spilled || CR3Spilled || CR4Spilled) { 1921 bool is31 = needsFP(*MF); 1922 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1923 MBB, I, CSI, CSIIndex); 1924 } 1925 1926 return true; 1927 } 1928 1929 bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const { 1930 return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() && 1931 MF.getSubtarget<PPCSubtarget>().isPPC64()); 1932 } 1933