1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PPC implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCFrameLowering.h" 15 #include "PPCInstrBuilder.h" 16 #include "PPCInstrInfo.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCSubtarget.h" 19 #include "PPCTargetMachine.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/RegisterScavenging.h" 26 #include "llvm/IR/Function.h" 27 #include "llvm/Target/TargetOptions.h" 28 29 using namespace llvm; 30 31 /// VRRegNo - Map from a numbered VR register to its enum value. 32 /// 33 static const MCPhysReg VRRegNo[] = { 34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 38 }; 39 40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) { 41 if (STI.isDarwinABI()) 42 return STI.isPPC64() ? 16 : 8; 43 // SVR4 ABI: 44 return STI.isPPC64() ? 16 : 4; 45 } 46 47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) { 48 return STI.isELFv2ABI() ? 24 : 40; 49 } 50 51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) { 52 // For the Darwin ABI: 53 // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area 54 // for saving the frame pointer (if needed.) While the published ABI has 55 // not used this slot since at least MacOSX 10.2, there is older code 56 // around that does use it, and that needs to continue to work. 57 if (STI.isDarwinABI()) 58 return STI.isPPC64() ? -8U : -4U; 59 60 // SVR4 ABI: First slot in the general register save area. 61 return STI.isPPC64() ? -8U : -4U; 62 } 63 64 static unsigned computeLinkageSize(const PPCSubtarget &STI) { 65 if (STI.isDarwinABI() || STI.isPPC64()) 66 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4); 67 68 // SVR4 ABI: 69 return 8; 70 } 71 72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) { 73 if (STI.isDarwinABI()) 74 return STI.isPPC64() ? -16U : -8U; 75 76 // SVR4 ABI: First slot in the general register save area. 77 return STI.isPPC64() 78 ? -16U 79 : (STI.getTargetMachine().getRelocationModel() == Reloc::PIC_) 80 ? -12U 81 : -8U; 82 } 83 84 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI) 85 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 86 STI.getPlatformStackAlignment(), 0), 87 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), 88 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), 89 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), 90 LinkageSize(computeLinkageSize(Subtarget)), 91 BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {} 92 93 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. 94 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots( 95 unsigned &NumEntries) const { 96 if (Subtarget.isDarwinABI()) { 97 NumEntries = 1; 98 if (Subtarget.isPPC64()) { 99 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; 100 return &darwin64Offsets; 101 } else { 102 static const SpillSlot darwinOffsets = {PPC::R31, -4}; 103 return &darwinOffsets; 104 } 105 } 106 107 // Early exit if not using the SVR4 ABI. 108 if (!Subtarget.isSVR4ABI()) { 109 NumEntries = 0; 110 return nullptr; 111 } 112 113 // Note that the offsets here overlap, but this is fixed up in 114 // processFunctionBeforeFrameFinalized. 115 116 static const SpillSlot Offsets[] = { 117 // Floating-point register save area offsets. 118 {PPC::F31, -8}, 119 {PPC::F30, -16}, 120 {PPC::F29, -24}, 121 {PPC::F28, -32}, 122 {PPC::F27, -40}, 123 {PPC::F26, -48}, 124 {PPC::F25, -56}, 125 {PPC::F24, -64}, 126 {PPC::F23, -72}, 127 {PPC::F22, -80}, 128 {PPC::F21, -88}, 129 {PPC::F20, -96}, 130 {PPC::F19, -104}, 131 {PPC::F18, -112}, 132 {PPC::F17, -120}, 133 {PPC::F16, -128}, 134 {PPC::F15, -136}, 135 {PPC::F14, -144}, 136 137 // General register save area offsets. 138 {PPC::R31, -4}, 139 {PPC::R30, -8}, 140 {PPC::R29, -12}, 141 {PPC::R28, -16}, 142 {PPC::R27, -20}, 143 {PPC::R26, -24}, 144 {PPC::R25, -28}, 145 {PPC::R24, -32}, 146 {PPC::R23, -36}, 147 {PPC::R22, -40}, 148 {PPC::R21, -44}, 149 {PPC::R20, -48}, 150 {PPC::R19, -52}, 151 {PPC::R18, -56}, 152 {PPC::R17, -60}, 153 {PPC::R16, -64}, 154 {PPC::R15, -68}, 155 {PPC::R14, -72}, 156 157 // CR save area offset. We map each of the nonvolatile CR fields 158 // to the slot for CR2, which is the first of the nonvolatile CR 159 // fields to be assigned, so that we only allocate one save slot. 160 // See PPCRegisterInfo::hasReservedSpillSlot() for more information. 161 {PPC::CR2, -4}, 162 163 // VRSAVE save area offset. 164 {PPC::VRSAVE, -4}, 165 166 // Vector register save area 167 {PPC::V31, -16}, 168 {PPC::V30, -32}, 169 {PPC::V29, -48}, 170 {PPC::V28, -64}, 171 {PPC::V27, -80}, 172 {PPC::V26, -96}, 173 {PPC::V25, -112}, 174 {PPC::V24, -128}, 175 {PPC::V23, -144}, 176 {PPC::V22, -160}, 177 {PPC::V21, -176}, 178 {PPC::V20, -192}}; 179 180 static const SpillSlot Offsets64[] = { 181 // Floating-point register save area offsets. 182 {PPC::F31, -8}, 183 {PPC::F30, -16}, 184 {PPC::F29, -24}, 185 {PPC::F28, -32}, 186 {PPC::F27, -40}, 187 {PPC::F26, -48}, 188 {PPC::F25, -56}, 189 {PPC::F24, -64}, 190 {PPC::F23, -72}, 191 {PPC::F22, -80}, 192 {PPC::F21, -88}, 193 {PPC::F20, -96}, 194 {PPC::F19, -104}, 195 {PPC::F18, -112}, 196 {PPC::F17, -120}, 197 {PPC::F16, -128}, 198 {PPC::F15, -136}, 199 {PPC::F14, -144}, 200 201 // General register save area offsets. 202 {PPC::X31, -8}, 203 {PPC::X30, -16}, 204 {PPC::X29, -24}, 205 {PPC::X28, -32}, 206 {PPC::X27, -40}, 207 {PPC::X26, -48}, 208 {PPC::X25, -56}, 209 {PPC::X24, -64}, 210 {PPC::X23, -72}, 211 {PPC::X22, -80}, 212 {PPC::X21, -88}, 213 {PPC::X20, -96}, 214 {PPC::X19, -104}, 215 {PPC::X18, -112}, 216 {PPC::X17, -120}, 217 {PPC::X16, -128}, 218 {PPC::X15, -136}, 219 {PPC::X14, -144}, 220 221 // VRSAVE save area offset. 222 {PPC::VRSAVE, -4}, 223 224 // Vector register save area 225 {PPC::V31, -16}, 226 {PPC::V30, -32}, 227 {PPC::V29, -48}, 228 {PPC::V28, -64}, 229 {PPC::V27, -80}, 230 {PPC::V26, -96}, 231 {PPC::V25, -112}, 232 {PPC::V24, -128}, 233 {PPC::V23, -144}, 234 {PPC::V22, -160}, 235 {PPC::V21, -176}, 236 {PPC::V20, -192}}; 237 238 if (Subtarget.isPPC64()) { 239 NumEntries = array_lengthof(Offsets64); 240 241 return Offsets64; 242 } else { 243 NumEntries = array_lengthof(Offsets); 244 245 return Offsets; 246 } 247 } 248 249 /// RemoveVRSaveCode - We have found that this function does not need any code 250 /// to manipulate the VRSAVE register, even though it uses vector registers. 251 /// This can happen when the only registers used are known to be live in or out 252 /// of the function. Remove all of the VRSAVE related code from the function. 253 /// FIXME: The removal of the code results in a compile failure at -O0 when the 254 /// function contains a function call, as the GPR containing original VRSAVE 255 /// contents is spilled and reloaded around the call. Without the prolog code, 256 /// the spill instruction refers to an undefined register. This code needs 257 /// to account for all uses of that GPR. 258 static void RemoveVRSaveCode(MachineInstr *MI) { 259 MachineBasicBlock *Entry = MI->getParent(); 260 MachineFunction *MF = Entry->getParent(); 261 262 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 263 MachineBasicBlock::iterator MBBI = MI; 264 ++MBBI; 265 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 266 MBBI->eraseFromParent(); 267 268 bool RemovedAllMTVRSAVEs = true; 269 // See if we can find and remove the MTVRSAVE instruction from all of the 270 // epilog blocks. 271 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 272 // If last instruction is a return instruction, add an epilogue 273 if (I->isReturnBlock()) { 274 bool FoundIt = false; 275 for (MBBI = I->end(); MBBI != I->begin(); ) { 276 --MBBI; 277 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 278 MBBI->eraseFromParent(); // remove it. 279 FoundIt = true; 280 break; 281 } 282 } 283 RemovedAllMTVRSAVEs &= FoundIt; 284 } 285 } 286 287 // If we found and removed all MTVRSAVE instructions, remove the read of 288 // VRSAVE as well. 289 if (RemovedAllMTVRSAVEs) { 290 MBBI = MI; 291 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 292 --MBBI; 293 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 294 MBBI->eraseFromParent(); 295 } 296 297 // Finally, nuke the UPDATE_VRSAVE. 298 MI->eraseFromParent(); 299 } 300 301 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 302 // instruction selector. Based on the vector registers that have been used, 303 // transform this into the appropriate ORI instruction. 304 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 305 MachineFunction *MF = MI->getParent()->getParent(); 306 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 307 DebugLoc dl = MI->getDebugLoc(); 308 309 const MachineRegisterInfo &MRI = MF->getRegInfo(); 310 unsigned UsedRegMask = 0; 311 for (unsigned i = 0; i != 32; ++i) 312 if (MRI.isPhysRegModified(VRRegNo[i])) 313 UsedRegMask |= 1 << (31-i); 314 315 // Live in and live out values already must be in the mask, so don't bother 316 // marking them. 317 for (MachineRegisterInfo::livein_iterator 318 I = MF->getRegInfo().livein_begin(), 319 E = MF->getRegInfo().livein_end(); I != E; ++I) { 320 unsigned RegNo = TRI->getEncodingValue(I->first); 321 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 322 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 323 } 324 325 // Live out registers appear as use operands on return instructions. 326 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 327 UsedRegMask != 0 && BI != BE; ++BI) { 328 const MachineBasicBlock &MBB = *BI; 329 if (!MBB.isReturnBlock()) 330 continue; 331 const MachineInstr &Ret = MBB.back(); 332 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 333 const MachineOperand &MO = Ret.getOperand(I); 334 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 335 continue; 336 unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 337 UsedRegMask &= ~(1 << (31-RegNo)); 338 } 339 } 340 341 // If no registers are used, turn this into a copy. 342 if (UsedRegMask == 0) { 343 // Remove all VRSAVE code. 344 RemoveVRSaveCode(MI); 345 return; 346 } 347 348 unsigned SrcReg = MI->getOperand(1).getReg(); 349 unsigned DstReg = MI->getOperand(0).getReg(); 350 351 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 352 if (DstReg != SrcReg) 353 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 354 .addReg(SrcReg) 355 .addImm(UsedRegMask); 356 else 357 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 358 .addReg(SrcReg, RegState::Kill) 359 .addImm(UsedRegMask); 360 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 361 if (DstReg != SrcReg) 362 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 363 .addReg(SrcReg) 364 .addImm(UsedRegMask >> 16); 365 else 366 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 367 .addReg(SrcReg, RegState::Kill) 368 .addImm(UsedRegMask >> 16); 369 } else { 370 if (DstReg != SrcReg) 371 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 372 .addReg(SrcReg) 373 .addImm(UsedRegMask >> 16); 374 else 375 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 376 .addReg(SrcReg, RegState::Kill) 377 .addImm(UsedRegMask >> 16); 378 379 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 380 .addReg(DstReg, RegState::Kill) 381 .addImm(UsedRegMask & 0xFFFF); 382 } 383 384 // Remove the old UPDATE_VRSAVE instruction. 385 MI->eraseFromParent(); 386 } 387 388 static bool spillsCR(const MachineFunction &MF) { 389 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 390 return FuncInfo->isCRSpilled(); 391 } 392 393 static bool spillsVRSAVE(const MachineFunction &MF) { 394 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 395 return FuncInfo->isVRSAVESpilled(); 396 } 397 398 static bool hasSpills(const MachineFunction &MF) { 399 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 400 return FuncInfo->hasSpills(); 401 } 402 403 static bool hasNonRISpills(const MachineFunction &MF) { 404 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 405 return FuncInfo->hasNonRISpills(); 406 } 407 408 /// MustSaveLR - Return true if this function requires that we save the LR 409 /// register onto the stack in the prolog and restore it in the epilog of the 410 /// function. 411 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 412 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 413 414 // We need a save/restore of LR if there is any def of LR (which is 415 // defined by calls, including the PIC setup sequence), or if there is 416 // some use of the LR stack slot (e.g. for builtin_return_address). 417 // (LR comes in 32 and 64 bit versions.) 418 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 419 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 420 } 421 422 /// determineFrameLayout - Determine the size of the frame and maximum call 423 /// frame size. 424 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 425 bool UpdateMF, 426 bool UseEstimate) const { 427 MachineFrameInfo *MFI = MF.getFrameInfo(); 428 429 // Get the number of bytes to allocate from the FrameInfo 430 unsigned FrameSize = 431 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 432 433 // Get stack alignments. The frame must be aligned to the greatest of these: 434 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI 435 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame 436 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1; 437 438 const PPCRegisterInfo *RegInfo = 439 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 440 441 // If we are a leaf function, and use up to 224 bytes of stack space, 442 // don't have a frame pointer, calls, or dynamic alloca then we do not need 443 // to adjust the stack pointer (we fit in the Red Zone). 444 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 445 // stackless code if all local vars are reg-allocated. 446 bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone); 447 unsigned LR = RegInfo->getRARegister(); 448 if (!DisableRedZone && 449 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 450 !Subtarget.isSVR4ABI() || // allocated locals. 451 FrameSize == 0) && 452 FrameSize <= 224 && // Fits in red zone. 453 !MFI->hasVarSizedObjects() && // No dynamic alloca. 454 !MFI->adjustsStack() && // No calls. 455 !MustSaveLR(MF, LR) && 456 !RegInfo->hasBasePointer(MF)) { // No special alignment. 457 // No need for frame 458 if (UpdateMF) 459 MFI->setStackSize(0); 460 return 0; 461 } 462 463 // Get the maximum call frame size of all the calls. 464 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 465 466 // Maximum call frame needs to be at least big enough for linkage area. 467 unsigned minCallFrameSize = getLinkageSize(); 468 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 469 470 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 471 // that allocations will be aligned. 472 if (MFI->hasVarSizedObjects()) 473 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 474 475 // Update maximum call frame size. 476 if (UpdateMF) 477 MFI->setMaxCallFrameSize(maxCallFrameSize); 478 479 // Include call frame size in total. 480 FrameSize += maxCallFrameSize; 481 482 // Make sure the frame is aligned. 483 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 484 485 // Update frame info. 486 if (UpdateMF) 487 MFI->setStackSize(FrameSize); 488 489 return FrameSize; 490 } 491 492 // hasFP - Return true if the specified function actually has a dedicated frame 493 // pointer register. 494 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 495 const MachineFrameInfo *MFI = MF.getFrameInfo(); 496 // FIXME: This is pretty much broken by design: hasFP() might be called really 497 // early, before the stack layout was calculated and thus hasFP() might return 498 // true or false here depending on the time of call. 499 return (MFI->getStackSize()) && needsFP(MF); 500 } 501 502 // needsFP - Return true if the specified function should have a dedicated frame 503 // pointer register. This is true if the function has variable sized allocas or 504 // if frame pointer elimination is disabled. 505 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 506 const MachineFrameInfo *MFI = MF.getFrameInfo(); 507 508 // Naked functions have no stack frame pushed, so we don't have a frame 509 // pointer. 510 if (MF.getFunction()->hasFnAttribute(Attribute::Naked)) 511 return false; 512 513 return MF.getTarget().Options.DisableFramePointerElim(MF) || 514 MFI->hasVarSizedObjects() || 515 MFI->hasStackMap() || MFI->hasPatchPoint() || 516 (MF.getTarget().Options.GuaranteedTailCallOpt && 517 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 518 } 519 520 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 521 bool is31 = needsFP(MF); 522 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 523 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 524 525 const PPCRegisterInfo *RegInfo = 526 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 527 bool HasBP = RegInfo->hasBasePointer(MF); 528 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; 529 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg; 530 531 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 532 BI != BE; ++BI) 533 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 534 --MBBI; 535 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 536 MachineOperand &MO = MBBI->getOperand(I); 537 if (!MO.isReg()) 538 continue; 539 540 switch (MO.getReg()) { 541 case PPC::FP: 542 MO.setReg(FPReg); 543 break; 544 case PPC::FP8: 545 MO.setReg(FP8Reg); 546 break; 547 case PPC::BP: 548 MO.setReg(BPReg); 549 break; 550 case PPC::BP8: 551 MO.setReg(BP8Reg); 552 break; 553 554 } 555 } 556 } 557 } 558 559 /* This function will do the following: 560 - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12 561 respectively (defaults recommended by the ABI) and return true 562 - If MBB is not an entry block, initialize the register scavenger and look 563 for available registers. 564 - If the defaults (R0/R12) are available, return true 565 - If TwoUniqueRegsRequired is set to true, it looks for two unique 566 registers. Otherwise, look for a single available register. 567 - If the required registers are found, set SR1 and SR2 and return true. 568 - If the required registers are not found, set SR2 or both SR1 and SR2 to 569 PPC::NoRegister and return false. 570 571 Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired 572 is not set, this function will attempt to find two different registers, but 573 still return true if only one register is available (and set SR1 == SR2). 574 */ 575 bool 576 PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, 577 bool UseAtEnd, 578 bool TwoUniqueRegsRequired, 579 unsigned *SR1, 580 unsigned *SR2) const { 581 RegScavenger RS; 582 unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0; 583 unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; 584 585 // Set the defaults for the two scratch registers. 586 if (SR1) 587 *SR1 = R0; 588 589 if (SR2) { 590 assert (SR1 && "Asking for the second scratch register but not the first?"); 591 *SR2 = R12; 592 } 593 594 // If MBB is an entry or exit block, use R0 and R12 as the scratch registers. 595 if ((UseAtEnd && MBB->isReturnBlock()) || 596 (!UseAtEnd && (&MBB->getParent()->front() == MBB))) 597 return true; 598 599 RS.enterBasicBlock(*MBB); 600 601 if (UseAtEnd && !MBB->empty()) { 602 // The scratch register will be used at the end of the block, so must 603 // consider all registers used within the block 604 605 MachineBasicBlock::iterator MBBI = MBB->getFirstTerminator(); 606 // If no terminator, back iterator up to previous instruction. 607 if (MBBI == MBB->end()) 608 MBBI = std::prev(MBBI); 609 610 if (MBBI != MBB->begin()) 611 RS.forward(MBBI); 612 } 613 614 // If the two registers are available, we're all good. 615 // Note that we only return here if both R0 and R12 are available because 616 // although the function may not require two unique registers, it may benefit 617 // from having two so we should try to provide them. 618 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) 619 return true; 620 621 // Get the list of callee-saved registers for the target. 622 const PPCRegisterInfo *RegInfo = 623 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 624 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); 625 626 // Get all the available registers in the block. 627 BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass : 628 &PPC::GPRCRegClass); 629 630 // We shouldn't use callee-saved registers as scratch registers as they may be 631 // available when looking for a candidate block for shrink wrapping but not 632 // available when the actual prologue/epilogue is being emitted because they 633 // were added as live-in to the prologue block by PrologueEpilogueInserter. 634 for (int i = 0; CSRegs[i]; ++i) 635 BV.reset(CSRegs[i]); 636 637 // Set the first scratch register to the first available one. 638 if (SR1) { 639 int FirstScratchReg = BV.find_first(); 640 *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg; 641 } 642 643 // If there is another one available, set the second scratch register to that. 644 // Otherwise, set it to either PPC::NoRegister if this function requires two 645 // or to whatever SR1 is set to if this function doesn't require two. 646 if (SR2) { 647 int SecondScratchReg = BV.find_next(*SR1); 648 if (SecondScratchReg != -1) 649 *SR2 = SecondScratchReg; 650 else 651 *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1; 652 } 653 654 // Now that we've done our best to provide both registers, double check 655 // whether we were unable to provide enough. 656 if (BV.count() < (TwoUniqueRegsRequired ? 2U : 1U)) 657 return false; 658 659 return true; 660 } 661 662 // We need a scratch register for spilling LR and for spilling CR. By default, 663 // we use two scratch registers to hide latency. However, if only one scratch 664 // register is available, we can adjust for that by not overlapping the spill 665 // code. However, if we need to realign the stack (i.e. have a base pointer) 666 // and the stack frame is large, we need two scratch registers. 667 bool 668 PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const { 669 const PPCRegisterInfo *RegInfo = 670 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 671 MachineFunction &MF = *(MBB->getParent()); 672 bool HasBP = RegInfo->hasBasePointer(MF); 673 unsigned FrameSize = determineFrameLayout(MF, false); 674 int NegFrameSize = -FrameSize; 675 bool IsLargeFrame = !isInt<16>(NegFrameSize); 676 MachineFrameInfo *MFI = MF.getFrameInfo(); 677 unsigned MaxAlign = MFI->getMaxAlignment(); 678 679 return IsLargeFrame && HasBP && MaxAlign > 1; 680 } 681 682 bool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { 683 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 684 685 return findScratchRegister(TmpMBB, false, 686 twoUniqueScratchRegsRequired(TmpMBB)); 687 } 688 689 bool PPCFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { 690 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 691 692 return findScratchRegister(TmpMBB, true); 693 } 694 695 void PPCFrameLowering::emitPrologue(MachineFunction &MF, 696 MachineBasicBlock &MBB) const { 697 MachineBasicBlock::iterator MBBI = MBB.begin(); 698 MachineFrameInfo *MFI = MF.getFrameInfo(); 699 const PPCInstrInfo &TII = 700 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 701 const PPCRegisterInfo *RegInfo = 702 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 703 704 MachineModuleInfo &MMI = MF.getMMI(); 705 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 706 DebugLoc dl; 707 bool needsCFI = MMI.hasDebugInfo() || 708 MF.getFunction()->needsUnwindTableEntry(); 709 710 // Get processor type. 711 bool isPPC64 = Subtarget.isPPC64(); 712 // Get the ABI. 713 bool isSVR4ABI = Subtarget.isSVR4ABI(); 714 bool isELFv2ABI = Subtarget.isELFv2ABI(); 715 assert((Subtarget.isDarwinABI() || isSVR4ABI) && 716 "Currently only Darwin and SVR4 ABIs are supported for PowerPC."); 717 718 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 719 // process it. 720 if (!isSVR4ABI) 721 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 722 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 723 HandleVRSaveUpdate(MBBI, TII); 724 break; 725 } 726 } 727 728 // Move MBBI back to the beginning of the prologue block. 729 MBBI = MBB.begin(); 730 731 // Work out frame sizes. 732 unsigned FrameSize = determineFrameLayout(MF); 733 int NegFrameSize = -FrameSize; 734 if (!isInt<32>(NegFrameSize)) 735 llvm_unreachable("Unhandled stack size!"); 736 737 if (MFI->isFrameAddressTaken()) 738 replaceFPWithRealFP(MF); 739 740 // Check if the link register (LR) must be saved. 741 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 742 bool MustSaveLR = FI->mustSaveLR(); 743 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 744 bool MustSaveCR = !MustSaveCRs.empty(); 745 // Do we have a frame pointer and/or base pointer for this function? 746 bool HasFP = hasFP(MF); 747 bool HasBP = RegInfo->hasBasePointer(MF); 748 749 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 750 unsigned BPReg = RegInfo->getBaseRegister(MF); 751 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 752 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR; 753 unsigned ScratchReg = 0; 754 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 755 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.) 756 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 757 : PPC::MFLR ); 758 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD 759 : PPC::STW ); 760 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU 761 : PPC::STWU ); 762 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX 763 : PPC::STWUX); 764 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8 765 : PPC::LIS ); 766 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 767 : PPC::ORI ); 768 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 769 : PPC::OR ); 770 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8 771 : PPC::SUBFC); 772 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8 773 : PPC::SUBFIC); 774 775 // Regarding this assert: Even though LR is saved in the caller's frame (i.e., 776 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no 777 // Red Zone, an asynchronous event (a form of "callee") could claim a frame & 778 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR. 779 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && 780 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); 781 782 // Using the same bool variable as below to supress compiler warnings. 783 bool SingleScratchReg = 784 findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB), 785 &ScratchReg, &TempReg); 786 assert(SingleScratchReg && 787 "Required number of registers not available in this block"); 788 789 SingleScratchReg = ScratchReg == TempReg; 790 791 int LROffset = getReturnSaveOffset(); 792 793 int FPOffset = 0; 794 if (HasFP) { 795 if (isSVR4ABI) { 796 MachineFrameInfo *FFI = MF.getFrameInfo(); 797 int FPIndex = FI->getFramePointerSaveIndex(); 798 assert(FPIndex && "No Frame Pointer Save Slot!"); 799 FPOffset = FFI->getObjectOffset(FPIndex); 800 } else { 801 FPOffset = getFramePointerSaveOffset(); 802 } 803 } 804 805 int BPOffset = 0; 806 if (HasBP) { 807 if (isSVR4ABI) { 808 MachineFrameInfo *FFI = MF.getFrameInfo(); 809 int BPIndex = FI->getBasePointerSaveIndex(); 810 assert(BPIndex && "No Base Pointer Save Slot!"); 811 BPOffset = FFI->getObjectOffset(BPIndex); 812 } else { 813 BPOffset = getBasePointerSaveOffset(); 814 } 815 } 816 817 int PBPOffset = 0; 818 if (FI->usesPICBase()) { 819 MachineFrameInfo *FFI = MF.getFrameInfo(); 820 int PBPIndex = FI->getPICBasePointerSaveIndex(); 821 assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 822 PBPOffset = FFI->getObjectOffset(PBPIndex); 823 } 824 825 // Get stack alignments. 826 unsigned MaxAlign = MFI->getMaxAlignment(); 827 if (HasBP && MaxAlign > 1) 828 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 829 "Invalid alignment!"); 830 831 // Frames of 32KB & larger require special handling because they cannot be 832 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand. 833 bool isLargeFrame = !isInt<16>(NegFrameSize); 834 835 assert((isPPC64 || !MustSaveCR) && 836 "Prologue CR saving supported only in 64-bit mode"); 837 838 // If we need to spill the CR and the LR but we don't have two separate 839 // registers available, we must spill them one at a time 840 if (MustSaveCR && SingleScratchReg && MustSaveLR) { 841 // In the ELFv2 ABI, we are not required to save all CR fields. 842 // If only one or two CR fields are clobbered, it is more efficient to use 843 // mfocrf to selectively save just those fields, because mfocrf has short 844 // latency compares to mfcr. 845 unsigned MfcrOpcode = PPC::MFCR8; 846 if (isELFv2ABI && MustSaveCRs.size() == 1) 847 MfcrOpcode = PPC::MFOCRF8; 848 MachineInstrBuilder MIB = 849 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg); 850 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 851 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 852 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 853 .addReg(TempReg, getKillRegState(true)) 854 .addImm(8) 855 .addReg(SPReg); 856 } 857 858 if (MustSaveLR) 859 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); 860 861 if (MustSaveCR && 862 !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64 863 // In the ELFv2 ABI, we are not required to save all CR fields. 864 // If only one or two CR fields are clobbered, it is more efficient to use 865 // mfocrf to selectively save just those fields, because mfocrf has short 866 // latency compares to mfcr. 867 unsigned MfcrOpcode = PPC::MFCR8; 868 if (isELFv2ABI && MustSaveCRs.size() == 1) 869 MfcrOpcode = PPC::MFOCRF8; 870 MachineInstrBuilder MIB = 871 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg); 872 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 873 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 874 } 875 876 if (HasFP) 877 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 878 BuildMI(MBB, MBBI, dl, StoreInst) 879 .addReg(FPReg) 880 .addImm(FPOffset) 881 .addReg(SPReg); 882 883 if (FI->usesPICBase()) 884 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 885 BuildMI(MBB, MBBI, dl, StoreInst) 886 .addReg(PPC::R30) 887 .addImm(PBPOffset) 888 .addReg(SPReg); 889 890 if (HasBP) 891 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 892 BuildMI(MBB, MBBI, dl, StoreInst) 893 .addReg(BPReg) 894 .addImm(BPOffset) 895 .addReg(SPReg); 896 897 if (MustSaveLR) 898 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 899 BuildMI(MBB, MBBI, dl, StoreInst) 900 .addReg(ScratchReg) 901 .addImm(LROffset) 902 .addReg(SPReg); 903 904 if (MustSaveCR && 905 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 906 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 907 .addReg(TempReg, getKillRegState(true)) 908 .addImm(8) 909 .addReg(SPReg); 910 911 // Skip the rest if this is a leaf function & all spills fit in the Red Zone. 912 if (!FrameSize) return; 913 914 // Adjust stack pointer: r1 += NegFrameSize. 915 // If there is a preferred stack alignment, align R1 now 916 917 if (HasBP) { 918 // Save a copy of r1 as the base pointer. 919 BuildMI(MBB, MBBI, dl, OrInst, BPReg) 920 .addReg(SPReg) 921 .addReg(SPReg); 922 } 923 924 // This condition must be kept in sync with canUseAsPrologue. 925 if (HasBP && MaxAlign > 1) { 926 if (isPPC64) 927 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) 928 .addReg(SPReg) 929 .addImm(0) 930 .addImm(64 - Log2_32(MaxAlign)); 931 else // PPC32... 932 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg) 933 .addReg(SPReg) 934 .addImm(0) 935 .addImm(32 - Log2_32(MaxAlign)) 936 .addImm(31); 937 if (!isLargeFrame) { 938 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg) 939 .addReg(ScratchReg, RegState::Kill) 940 .addImm(NegFrameSize); 941 } else { 942 assert(!SingleScratchReg && "Only a single scratch reg available"); 943 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) 944 .addImm(NegFrameSize >> 16); 945 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg) 946 .addReg(TempReg, RegState::Kill) 947 .addImm(NegFrameSize & 0xFFFF); 948 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg) 949 .addReg(ScratchReg, RegState::Kill) 950 .addReg(TempReg, RegState::Kill); 951 } 952 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 953 .addReg(SPReg, RegState::Kill) 954 .addReg(SPReg) 955 .addReg(ScratchReg); 956 957 } else if (!isLargeFrame) { 958 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg) 959 .addReg(SPReg) 960 .addImm(NegFrameSize) 961 .addReg(SPReg); 962 963 } else { 964 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 965 .addImm(NegFrameSize >> 16); 966 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 967 .addReg(ScratchReg, RegState::Kill) 968 .addImm(NegFrameSize & 0xFFFF); 969 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 970 .addReg(SPReg, RegState::Kill) 971 .addReg(SPReg) 972 .addReg(ScratchReg); 973 } 974 975 // Add Call Frame Information for the instructions we generated above. 976 if (needsCFI) { 977 unsigned CFIIndex; 978 979 if (HasBP) { 980 // Define CFA in terms of BP. Do this in preference to using FP/SP, 981 // because if the stack needed aligning then CFA won't be at a fixed 982 // offset from FP/SP. 983 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 984 CFIIndex = MMI.addFrameInst( 985 MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 986 } else { 987 // Adjust the definition of CFA to account for the change in SP. 988 assert(NegFrameSize); 989 CFIIndex = MMI.addFrameInst( 990 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize)); 991 } 992 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 993 .addCFIIndex(CFIIndex); 994 995 if (HasFP) { 996 // Describe where FP was saved, at a fixed offset from CFA. 997 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 998 CFIIndex = MMI.addFrameInst( 999 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset)); 1000 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1001 .addCFIIndex(CFIIndex); 1002 } 1003 1004 if (FI->usesPICBase()) { 1005 // Describe where FP was saved, at a fixed offset from CFA. 1006 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true); 1007 CFIIndex = MMI.addFrameInst( 1008 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset)); 1009 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1010 .addCFIIndex(CFIIndex); 1011 } 1012 1013 if (HasBP) { 1014 // Describe where BP was saved, at a fixed offset from CFA. 1015 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 1016 CFIIndex = MMI.addFrameInst( 1017 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset)); 1018 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1019 .addCFIIndex(CFIIndex); 1020 } 1021 1022 if (MustSaveLR) { 1023 // Describe where LR was saved, at a fixed offset from CFA. 1024 unsigned Reg = MRI->getDwarfRegNum(LRReg, true); 1025 CFIIndex = MMI.addFrameInst( 1026 MCCFIInstruction::createOffset(nullptr, Reg, LROffset)); 1027 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1028 .addCFIIndex(CFIIndex); 1029 } 1030 } 1031 1032 // If there is a frame pointer, copy R1 into R31 1033 if (HasFP) { 1034 BuildMI(MBB, MBBI, dl, OrInst, FPReg) 1035 .addReg(SPReg) 1036 .addReg(SPReg); 1037 1038 if (!HasBP && needsCFI) { 1039 // Change the definition of CFA from SP+offset to FP+offset, because SP 1040 // will change at every alloca. 1041 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 1042 unsigned CFIIndex = MMI.addFrameInst( 1043 MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 1044 1045 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1046 .addCFIIndex(CFIIndex); 1047 } 1048 } 1049 1050 if (needsCFI) { 1051 // Describe where callee saved registers were saved, at fixed offsets from 1052 // CFA. 1053 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1054 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1055 unsigned Reg = CSI[I].getReg(); 1056 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 1057 1058 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 1059 // subregisters of CR2. We just need to emit a move of CR2. 1060 if (PPC::CRBITRCRegClass.contains(Reg)) 1061 continue; 1062 1063 // For SVR4, don't emit a move for the CR spill slot if we haven't 1064 // spilled CRs. 1065 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 1066 && !MustSaveCR) 1067 continue; 1068 1069 // For 64-bit SVR4 when we have spilled CRs, the spill location 1070 // is SP+8, not a frame-relative slot. 1071 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1072 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for 1073 // the whole CR word. In the ELFv2 ABI, every CR that was 1074 // actually saved gets its own CFI record. 1075 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2; 1076 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1077 nullptr, MRI->getDwarfRegNum(CRReg, true), 8)); 1078 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1079 .addCFIIndex(CFIIndex); 1080 continue; 1081 } 1082 1083 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1084 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1085 nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); 1086 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1087 .addCFIIndex(CFIIndex); 1088 } 1089 } 1090 } 1091 1092 void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 1093 MachineBasicBlock &MBB) const { 1094 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 1095 DebugLoc dl; 1096 1097 if (MBBI != MBB.end()) 1098 dl = MBBI->getDebugLoc(); 1099 1100 const PPCInstrInfo &TII = 1101 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1102 const PPCRegisterInfo *RegInfo = 1103 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1104 1105 // Get alignment info so we know how to restore the SP. 1106 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1107 1108 // Get the number of bytes allocated from the FrameInfo. 1109 int FrameSize = MFI->getStackSize(); 1110 1111 // Get processor type. 1112 bool isPPC64 = Subtarget.isPPC64(); 1113 // Get the ABI. 1114 bool isSVR4ABI = Subtarget.isSVR4ABI(); 1115 1116 // Check if the link register (LR) has been saved. 1117 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1118 bool MustSaveLR = FI->mustSaveLR(); 1119 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 1120 bool MustSaveCR = !MustSaveCRs.empty(); 1121 // Do we have a frame pointer and/or base pointer for this function? 1122 bool HasFP = hasFP(MF); 1123 bool HasBP = RegInfo->hasBasePointer(MF); 1124 1125 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 1126 unsigned BPReg = RegInfo->getBaseRegister(MF); 1127 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 1128 unsigned ScratchReg = 0; 1129 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 1130 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 1131 : PPC::MTLR ); 1132 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD 1133 : PPC::LWZ ); 1134 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8 1135 : PPC::LIS ); 1136 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 1137 : PPC::ORI ); 1138 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8 1139 : PPC::ADDI ); 1140 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 1141 : PPC::ADD4 ); 1142 1143 int LROffset = getReturnSaveOffset(); 1144 1145 int FPOffset = 0; 1146 1147 // Using the same bool variable as below to supress compiler warnings. 1148 bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg, 1149 &TempReg); 1150 assert(SingleScratchReg && 1151 "Could not find an available scratch register"); 1152 1153 SingleScratchReg = ScratchReg == TempReg; 1154 1155 if (HasFP) { 1156 if (isSVR4ABI) { 1157 MachineFrameInfo *FFI = MF.getFrameInfo(); 1158 int FPIndex = FI->getFramePointerSaveIndex(); 1159 assert(FPIndex && "No Frame Pointer Save Slot!"); 1160 FPOffset = FFI->getObjectOffset(FPIndex); 1161 } else { 1162 FPOffset = getFramePointerSaveOffset(); 1163 } 1164 } 1165 1166 int BPOffset = 0; 1167 if (HasBP) { 1168 if (isSVR4ABI) { 1169 MachineFrameInfo *FFI = MF.getFrameInfo(); 1170 int BPIndex = FI->getBasePointerSaveIndex(); 1171 assert(BPIndex && "No Base Pointer Save Slot!"); 1172 BPOffset = FFI->getObjectOffset(BPIndex); 1173 } else { 1174 BPOffset = getBasePointerSaveOffset(); 1175 } 1176 } 1177 1178 int PBPOffset = 0; 1179 if (FI->usesPICBase()) { 1180 MachineFrameInfo *FFI = MF.getFrameInfo(); 1181 int PBPIndex = FI->getPICBasePointerSaveIndex(); 1182 assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 1183 PBPOffset = FFI->getObjectOffset(PBPIndex); 1184 } 1185 1186 bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn()); 1187 1188 if (IsReturnBlock) { 1189 unsigned RetOpcode = MBBI->getOpcode(); 1190 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1191 RetOpcode == PPC::TCRETURNdi || 1192 RetOpcode == PPC::TCRETURNai || 1193 RetOpcode == PPC::TCRETURNri8 || 1194 RetOpcode == PPC::TCRETURNdi8 || 1195 RetOpcode == PPC::TCRETURNai8; 1196 1197 if (UsesTCRet) { 1198 int MaxTCRetDelta = FI->getTailCallSPDelta(); 1199 MachineOperand &StackAdjust = MBBI->getOperand(1); 1200 assert(StackAdjust.isImm() && "Expecting immediate value."); 1201 // Adjust stack pointer. 1202 int StackAdj = StackAdjust.getImm(); 1203 int Delta = StackAdj - MaxTCRetDelta; 1204 assert((Delta >= 0) && "Delta must be positive"); 1205 if (MaxTCRetDelta>0) 1206 FrameSize += (StackAdj +Delta); 1207 else 1208 FrameSize += StackAdj; 1209 } 1210 } 1211 1212 // Frames of 32KB & larger require special handling because they cannot be 1213 // indexed into with a simple LD/LWZ immediate offset operand. 1214 bool isLargeFrame = !isInt<16>(FrameSize); 1215 1216 if (FrameSize) { 1217 // In the prologue, the loaded (or persistent) stack pointer value is offset 1218 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now. 1219 1220 // If this function contained a fastcc call and GuaranteedTailCallOpt is 1221 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1222 // call which invalidates the stack pointer value in SP(0). So we use the 1223 // value of R31 in this case. 1224 if (FI->hasFastCall()) { 1225 assert(HasFP && "Expecting a valid frame pointer."); 1226 if (!isLargeFrame) { 1227 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1228 .addReg(FPReg).addImm(FrameSize); 1229 } else { 1230 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1231 .addImm(FrameSize >> 16); 1232 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1233 .addReg(ScratchReg, RegState::Kill) 1234 .addImm(FrameSize & 0xFFFF); 1235 BuildMI(MBB, MBBI, dl, AddInst) 1236 .addReg(SPReg) 1237 .addReg(FPReg) 1238 .addReg(ScratchReg); 1239 } 1240 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) { 1241 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1242 .addReg(SPReg) 1243 .addImm(FrameSize); 1244 } else { 1245 BuildMI(MBB, MBBI, dl, LoadInst, SPReg) 1246 .addImm(0) 1247 .addReg(SPReg); 1248 } 1249 } 1250 1251 assert((isPPC64 || !MustSaveCR) && 1252 "Epilogue CR restoring supported only in 64-bit mode"); 1253 1254 // If we need to save both the LR and the CR and we only have one available 1255 // scratch register, we must do them one at a time. 1256 if (MustSaveCR && SingleScratchReg && MustSaveLR) { 1257 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 1258 .addImm(8) 1259 .addReg(SPReg); 1260 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1261 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1262 .addReg(TempReg, getKillRegState(i == e-1)); 1263 } 1264 1265 if (MustSaveLR) 1266 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) 1267 .addImm(LROffset) 1268 .addReg(SPReg); 1269 1270 if (MustSaveCR && 1271 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 1272 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 1273 .addImm(8) 1274 .addReg(SPReg); 1275 1276 if (HasFP) 1277 BuildMI(MBB, MBBI, dl, LoadInst, FPReg) 1278 .addImm(FPOffset) 1279 .addReg(SPReg); 1280 1281 if (FI->usesPICBase()) 1282 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 1283 BuildMI(MBB, MBBI, dl, LoadInst) 1284 .addReg(PPC::R30) 1285 .addImm(PBPOffset) 1286 .addReg(SPReg); 1287 1288 if (HasBP) 1289 BuildMI(MBB, MBBI, dl, LoadInst, BPReg) 1290 .addImm(BPOffset) 1291 .addReg(SPReg); 1292 1293 if (MustSaveCR && 1294 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 1295 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1296 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1297 .addReg(TempReg, getKillRegState(i == e-1)); 1298 1299 if (MustSaveLR) 1300 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg); 1301 1302 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1303 // call optimization 1304 if (IsReturnBlock) { 1305 unsigned RetOpcode = MBBI->getOpcode(); 1306 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1307 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) && 1308 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1309 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1310 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1311 1312 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 1313 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1314 .addReg(SPReg).addImm(CallerAllocatedAmt); 1315 } else { 1316 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1317 .addImm(CallerAllocatedAmt >> 16); 1318 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1319 .addReg(ScratchReg, RegState::Kill) 1320 .addImm(CallerAllocatedAmt & 0xFFFF); 1321 BuildMI(MBB, MBBI, dl, AddInst) 1322 .addReg(SPReg) 1323 .addReg(FPReg) 1324 .addReg(ScratchReg); 1325 } 1326 } else { 1327 createTailCallBranchInstr(MBB); 1328 } 1329 } 1330 } 1331 1332 void PPCFrameLowering::createTailCallBranchInstr(MachineBasicBlock &MBB) const { 1333 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 1334 DebugLoc dl; 1335 1336 if (MBBI != MBB.end()) 1337 dl = MBBI->getDebugLoc(); 1338 1339 const PPCInstrInfo &TII = 1340 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1341 1342 // Create branch instruction for pseudo tail call return instruction 1343 unsigned RetOpcode = MBBI->getOpcode(); 1344 if (RetOpcode == PPC::TCRETURNdi) { 1345 MBBI = MBB.getLastNonDebugInstr(); 1346 MachineOperand &JumpTarget = MBBI->getOperand(0); 1347 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1348 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1349 } else if (RetOpcode == PPC::TCRETURNri) { 1350 MBBI = MBB.getLastNonDebugInstr(); 1351 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1352 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1353 } else if (RetOpcode == PPC::TCRETURNai) { 1354 MBBI = MBB.getLastNonDebugInstr(); 1355 MachineOperand &JumpTarget = MBBI->getOperand(0); 1356 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1357 } else if (RetOpcode == PPC::TCRETURNdi8) { 1358 MBBI = MBB.getLastNonDebugInstr(); 1359 MachineOperand &JumpTarget = MBBI->getOperand(0); 1360 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1361 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1362 } else if (RetOpcode == PPC::TCRETURNri8) { 1363 MBBI = MBB.getLastNonDebugInstr(); 1364 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1365 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1366 } else if (RetOpcode == PPC::TCRETURNai8) { 1367 MBBI = MBB.getLastNonDebugInstr(); 1368 MachineOperand &JumpTarget = MBBI->getOperand(0); 1369 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1370 } 1371 } 1372 1373 void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF, 1374 BitVector &SavedRegs, 1375 RegScavenger *RS) const { 1376 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 1377 1378 const PPCRegisterInfo *RegInfo = 1379 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1380 1381 // Save and clear the LR state. 1382 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1383 unsigned LR = RegInfo->getRARegister(); 1384 FI->setMustSaveLR(MustSaveLR(MF, LR)); 1385 SavedRegs.reset(LR); 1386 1387 // Save R31 if necessary 1388 int FPSI = FI->getFramePointerSaveIndex(); 1389 bool isPPC64 = Subtarget.isPPC64(); 1390 bool isDarwinABI = Subtarget.isDarwinABI(); 1391 MachineFrameInfo *MFI = MF.getFrameInfo(); 1392 1393 // If the frame pointer save index hasn't been defined yet. 1394 if (!FPSI && needsFP(MF)) { 1395 // Find out what the fix offset of the frame pointer save area. 1396 int FPOffset = getFramePointerSaveOffset(); 1397 // Allocate the frame index for frame pointer save area. 1398 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 1399 // Save the result. 1400 FI->setFramePointerSaveIndex(FPSI); 1401 } 1402 1403 int BPSI = FI->getBasePointerSaveIndex(); 1404 if (!BPSI && RegInfo->hasBasePointer(MF)) { 1405 int BPOffset = getBasePointerSaveOffset(); 1406 // Allocate the frame index for the base pointer save area. 1407 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true); 1408 // Save the result. 1409 FI->setBasePointerSaveIndex(BPSI); 1410 } 1411 1412 // Reserve stack space for the PIC Base register (R30). 1413 // Only used in SVR4 32-bit. 1414 if (FI->usesPICBase()) { 1415 int PBPSI = MFI->CreateFixedObject(4, -8, true); 1416 FI->setPICBasePointerSaveIndex(PBPSI); 1417 } 1418 1419 // Reserve stack space to move the linkage area to in case of a tail call. 1420 int TCSPDelta = 0; 1421 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1422 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 1423 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 1424 } 1425 1426 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 1427 // function uses CR 2, 3, or 4. 1428 if (!isPPC64 && !isDarwinABI && 1429 (SavedRegs.test(PPC::CR2) || 1430 SavedRegs.test(PPC::CR3) || 1431 SavedRegs.test(PPC::CR4))) { 1432 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 1433 FI->setCRSpillFrameIndex(FrameIdx); 1434 } 1435 } 1436 1437 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 1438 RegScavenger *RS) const { 1439 // Early exit if not using the SVR4 ABI. 1440 if (!Subtarget.isSVR4ABI()) { 1441 addScavengingSpillSlot(MF, RS); 1442 return; 1443 } 1444 1445 // Get callee saved register information. 1446 MachineFrameInfo *FFI = MF.getFrameInfo(); 1447 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 1448 1449 // If the function is shrink-wrapped, and if the function has a tail call, the 1450 // tail call might not be in the new RestoreBlock, so real branch instruction 1451 // won't be generated by emitEpilogue(), because shrink-wrap has chosen new 1452 // RestoreBlock. So we handle this case here. 1453 if (FFI->getSavePoint() && FFI->hasTailCall()) { 1454 MachineBasicBlock *RestoreBlock = FFI->getRestorePoint(); 1455 for (MachineBasicBlock &MBB : MF) { 1456 if (MBB.isReturnBlock() && (&MBB) != RestoreBlock) 1457 createTailCallBranchInstr(MBB); 1458 } 1459 } 1460 1461 // Early exit if no callee saved registers are modified! 1462 if (CSI.empty() && !needsFP(MF)) { 1463 addScavengingSpillSlot(MF, RS); 1464 return; 1465 } 1466 1467 unsigned MinGPR = PPC::R31; 1468 unsigned MinG8R = PPC::X31; 1469 unsigned MinFPR = PPC::F31; 1470 unsigned MinVR = PPC::V31; 1471 1472 bool HasGPSaveArea = false; 1473 bool HasG8SaveArea = false; 1474 bool HasFPSaveArea = false; 1475 bool HasVRSAVESaveArea = false; 1476 bool HasVRSaveArea = false; 1477 1478 SmallVector<CalleeSavedInfo, 18> GPRegs; 1479 SmallVector<CalleeSavedInfo, 18> G8Regs; 1480 SmallVector<CalleeSavedInfo, 18> FPRegs; 1481 SmallVector<CalleeSavedInfo, 18> VRegs; 1482 1483 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1484 unsigned Reg = CSI[i].getReg(); 1485 if (PPC::GPRCRegClass.contains(Reg)) { 1486 HasGPSaveArea = true; 1487 1488 GPRegs.push_back(CSI[i]); 1489 1490 if (Reg < MinGPR) { 1491 MinGPR = Reg; 1492 } 1493 } else if (PPC::G8RCRegClass.contains(Reg)) { 1494 HasG8SaveArea = true; 1495 1496 G8Regs.push_back(CSI[i]); 1497 1498 if (Reg < MinG8R) { 1499 MinG8R = Reg; 1500 } 1501 } else if (PPC::F8RCRegClass.contains(Reg)) { 1502 HasFPSaveArea = true; 1503 1504 FPRegs.push_back(CSI[i]); 1505 1506 if (Reg < MinFPR) { 1507 MinFPR = Reg; 1508 } 1509 } else if (PPC::CRBITRCRegClass.contains(Reg) || 1510 PPC::CRRCRegClass.contains(Reg)) { 1511 ; // do nothing, as we already know whether CRs are spilled 1512 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 1513 HasVRSAVESaveArea = true; 1514 } else if (PPC::VRRCRegClass.contains(Reg)) { 1515 HasVRSaveArea = true; 1516 1517 VRegs.push_back(CSI[i]); 1518 1519 if (Reg < MinVR) { 1520 MinVR = Reg; 1521 } 1522 } else { 1523 llvm_unreachable("Unknown RegisterClass!"); 1524 } 1525 } 1526 1527 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1528 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1529 1530 int64_t LowerBound = 0; 1531 1532 // Take into account stack space reserved for tail calls. 1533 int TCSPDelta = 0; 1534 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1535 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1536 LowerBound = TCSPDelta; 1537 } 1538 1539 // The Floating-point register save area is right below the back chain word 1540 // of the previous stack frame. 1541 if (HasFPSaveArea) { 1542 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1543 int FI = FPRegs[i].getFrameIdx(); 1544 1545 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1546 } 1547 1548 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 1549 } 1550 1551 // Check whether the frame pointer register is allocated. If so, make sure it 1552 // is spilled to the correct offset. 1553 if (needsFP(MF)) { 1554 HasGPSaveArea = true; 1555 1556 int FI = PFI->getFramePointerSaveIndex(); 1557 assert(FI && "No Frame Pointer Save Slot!"); 1558 1559 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1560 } 1561 1562 if (PFI->usesPICBase()) { 1563 HasGPSaveArea = true; 1564 1565 int FI = PFI->getPICBasePointerSaveIndex(); 1566 assert(FI && "No PIC Base Pointer Save Slot!"); 1567 1568 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1569 } 1570 1571 const PPCRegisterInfo *RegInfo = 1572 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1573 if (RegInfo->hasBasePointer(MF)) { 1574 HasGPSaveArea = true; 1575 1576 int FI = PFI->getBasePointerSaveIndex(); 1577 assert(FI && "No Base Pointer Save Slot!"); 1578 1579 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1580 } 1581 1582 // General register save area starts right below the Floating-point 1583 // register save area. 1584 if (HasGPSaveArea || HasG8SaveArea) { 1585 // Move general register save area spill slots down, taking into account 1586 // the size of the Floating-point register save area. 1587 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1588 int FI = GPRegs[i].getFrameIdx(); 1589 1590 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1591 } 1592 1593 // Move general register save area spill slots down, taking into account 1594 // the size of the Floating-point register save area. 1595 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1596 int FI = G8Regs[i].getFrameIdx(); 1597 1598 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1599 } 1600 1601 unsigned MinReg = 1602 std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1603 TRI->getEncodingValue(MinG8R)); 1604 1605 if (Subtarget.isPPC64()) { 1606 LowerBound -= (31 - MinReg + 1) * 8; 1607 } else { 1608 LowerBound -= (31 - MinReg + 1) * 4; 1609 } 1610 } 1611 1612 // For 32-bit only, the CR save area is below the general register 1613 // save area. For 64-bit SVR4, the CR save area is addressed relative 1614 // to the stack pointer and hence does not need an adjustment here. 1615 // Only CR2 (the first nonvolatile spilled) has an associated frame 1616 // index so that we have a single uniform save area. 1617 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1618 // Adjust the frame index of the CR spill slot. 1619 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1620 unsigned Reg = CSI[i].getReg(); 1621 1622 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1623 // Leave Darwin logic as-is. 1624 || (!Subtarget.isSVR4ABI() && 1625 (PPC::CRBITRCRegClass.contains(Reg) || 1626 PPC::CRRCRegClass.contains(Reg)))) { 1627 int FI = CSI[i].getFrameIdx(); 1628 1629 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1630 } 1631 } 1632 1633 LowerBound -= 4; // The CR save area is always 4 bytes long. 1634 } 1635 1636 if (HasVRSAVESaveArea) { 1637 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1638 // which have the VRSAVE register class? 1639 // Adjust the frame index of the VRSAVE spill slot. 1640 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1641 unsigned Reg = CSI[i].getReg(); 1642 1643 if (PPC::VRSAVERCRegClass.contains(Reg)) { 1644 int FI = CSI[i].getFrameIdx(); 1645 1646 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1647 } 1648 } 1649 1650 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1651 } 1652 1653 if (HasVRSaveArea) { 1654 // Insert alignment padding, we need 16-byte alignment. 1655 LowerBound = (LowerBound - 15) & ~(15); 1656 1657 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1658 int FI = VRegs[i].getFrameIdx(); 1659 1660 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1661 } 1662 } 1663 1664 addScavengingSpillSlot(MF, RS); 1665 } 1666 1667 void 1668 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1669 RegScavenger *RS) const { 1670 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1671 // a large stack, which will require scavenging a register to materialize a 1672 // large offset. 1673 1674 // We need to have a scavenger spill slot for spills if the frame size is 1675 // large. In case there is no free register for large-offset addressing, 1676 // this slot is used for the necessary emergency spill. Also, we need the 1677 // slot for dynamic stack allocations. 1678 1679 // The scavenger might be invoked if the frame offset does not fit into 1680 // the 16-bit immediate. We don't know the complete frame size here 1681 // because we've not yet computed callee-saved register spills or the 1682 // needed alignment padding. 1683 unsigned StackSize = determineFrameLayout(MF, false, true); 1684 MachineFrameInfo *MFI = MF.getFrameInfo(); 1685 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1686 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1687 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1688 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1689 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1690 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1691 RC->getAlignment(), 1692 false)); 1693 1694 // Might we have over-aligned allocas? 1695 bool HasAlVars = MFI->hasVarSizedObjects() && 1696 MFI->getMaxAlignment() > getStackAlignment(); 1697 1698 // These kinds of spills might need two registers. 1699 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars) 1700 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1701 RC->getAlignment(), 1702 false)); 1703 1704 } 1705 } 1706 1707 bool 1708 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1709 MachineBasicBlock::iterator MI, 1710 const std::vector<CalleeSavedInfo> &CSI, 1711 const TargetRegisterInfo *TRI) const { 1712 1713 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1714 // Return false otherwise to maintain pre-existing behavior. 1715 if (!Subtarget.isSVR4ABI()) 1716 return false; 1717 1718 MachineFunction *MF = MBB.getParent(); 1719 const PPCInstrInfo &TII = 1720 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1721 DebugLoc DL; 1722 bool CRSpilled = false; 1723 MachineInstrBuilder CRMIB; 1724 1725 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1726 unsigned Reg = CSI[i].getReg(); 1727 // Only Darwin actually uses the VRSAVE register, but it can still appear 1728 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1729 // Darwin, ignore it. 1730 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1731 continue; 1732 1733 // CR2 through CR4 are the nonvolatile CR fields. 1734 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1735 1736 // Add the callee-saved register as live-in; it's killed at the spill. 1737 MBB.addLiveIn(Reg); 1738 1739 if (CRSpilled && IsCRField) { 1740 CRMIB.addReg(Reg, RegState::ImplicitKill); 1741 continue; 1742 } 1743 1744 // Insert the spill to the stack frame. 1745 if (IsCRField) { 1746 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1747 if (Subtarget.isPPC64()) { 1748 // The actual spill will happen at the start of the prologue. 1749 FuncInfo->addMustSaveCR(Reg); 1750 } else { 1751 CRSpilled = true; 1752 FuncInfo->setSpillsCR(); 1753 1754 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1755 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1756 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) 1757 .addReg(Reg, RegState::ImplicitKill); 1758 1759 MBB.insert(MI, CRMIB); 1760 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1761 .addReg(PPC::R12, 1762 getKillRegState(true)), 1763 CSI[i].getFrameIdx())); 1764 } 1765 } else { 1766 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1767 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1768 CSI[i].getFrameIdx(), RC, TRI); 1769 } 1770 } 1771 return true; 1772 } 1773 1774 static void 1775 restoreCRs(bool isPPC64, bool is31, 1776 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1777 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1778 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1779 1780 MachineFunction *MF = MBB.getParent(); 1781 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 1782 DebugLoc DL; 1783 unsigned RestoreOp, MoveReg; 1784 1785 if (isPPC64) 1786 // This is handled during epilogue generation. 1787 return; 1788 else { 1789 // 32-bit: FP-relative 1790 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1791 PPC::R12), 1792 CSI[CSIIndex].getFrameIdx())); 1793 RestoreOp = PPC::MTOCRF; 1794 MoveReg = PPC::R12; 1795 } 1796 1797 if (CR2Spilled) 1798 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1799 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1800 1801 if (CR3Spilled) 1802 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1803 .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1804 1805 if (CR4Spilled) 1806 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1807 .addReg(MoveReg, getKillRegState(true))); 1808 } 1809 1810 MachineBasicBlock::iterator PPCFrameLowering:: 1811 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1812 MachineBasicBlock::iterator I) const { 1813 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1814 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1815 I->getOpcode() == PPC::ADJCALLSTACKUP) { 1816 // Add (actually subtract) back the amount the callee popped on return. 1817 if (int CalleeAmt = I->getOperand(1).getImm()) { 1818 bool is64Bit = Subtarget.isPPC64(); 1819 CalleeAmt *= -1; 1820 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1821 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1822 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1823 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1824 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1825 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1826 MachineInstr *MI = I; 1827 DebugLoc dl = MI->getDebugLoc(); 1828 1829 if (isInt<16>(CalleeAmt)) { 1830 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1831 .addReg(StackReg, RegState::Kill) 1832 .addImm(CalleeAmt); 1833 } else { 1834 MachineBasicBlock::iterator MBBI = I; 1835 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1836 .addImm(CalleeAmt >> 16); 1837 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1838 .addReg(TmpReg, RegState::Kill) 1839 .addImm(CalleeAmt & 0xFFFF); 1840 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1841 .addReg(StackReg, RegState::Kill) 1842 .addReg(TmpReg); 1843 } 1844 } 1845 } 1846 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1847 return MBB.erase(I); 1848 } 1849 1850 bool 1851 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1852 MachineBasicBlock::iterator MI, 1853 const std::vector<CalleeSavedInfo> &CSI, 1854 const TargetRegisterInfo *TRI) const { 1855 1856 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1857 // Return false otherwise to maintain pre-existing behavior. 1858 if (!Subtarget.isSVR4ABI()) 1859 return false; 1860 1861 MachineFunction *MF = MBB.getParent(); 1862 const PPCInstrInfo &TII = 1863 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1864 bool CR2Spilled = false; 1865 bool CR3Spilled = false; 1866 bool CR4Spilled = false; 1867 unsigned CSIIndex = 0; 1868 1869 // Initialize insertion-point logic; we will be restoring in reverse 1870 // order of spill. 1871 MachineBasicBlock::iterator I = MI, BeforeI = I; 1872 bool AtStart = I == MBB.begin(); 1873 1874 if (!AtStart) 1875 --BeforeI; 1876 1877 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1878 unsigned Reg = CSI[i].getReg(); 1879 1880 // Only Darwin actually uses the VRSAVE register, but it can still appear 1881 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1882 // Darwin, ignore it. 1883 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1884 continue; 1885 1886 if (Reg == PPC::CR2) { 1887 CR2Spilled = true; 1888 // The spill slot is associated only with CR2, which is the 1889 // first nonvolatile spilled. Save it here. 1890 CSIIndex = i; 1891 continue; 1892 } else if (Reg == PPC::CR3) { 1893 CR3Spilled = true; 1894 continue; 1895 } else if (Reg == PPC::CR4) { 1896 CR4Spilled = true; 1897 continue; 1898 } else { 1899 // When we first encounter a non-CR register after seeing at 1900 // least one CR register, restore all spilled CRs together. 1901 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1902 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1903 bool is31 = needsFP(*MF); 1904 restoreCRs(Subtarget.isPPC64(), is31, 1905 CR2Spilled, CR3Spilled, CR4Spilled, 1906 MBB, I, CSI, CSIIndex); 1907 CR2Spilled = CR3Spilled = CR4Spilled = false; 1908 } 1909 1910 // Default behavior for non-CR saves. 1911 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1912 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1913 RC, TRI); 1914 assert(I != MBB.begin() && 1915 "loadRegFromStackSlot didn't insert any code!"); 1916 } 1917 1918 // Insert in reverse order. 1919 if (AtStart) 1920 I = MBB.begin(); 1921 else { 1922 I = BeforeI; 1923 ++I; 1924 } 1925 } 1926 1927 // If we haven't yet spilled the CRs, do so now. 1928 if (CR2Spilled || CR3Spilled || CR4Spilled) { 1929 bool is31 = needsFP(*MF); 1930 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1931 MBB, I, CSI, CSIIndex); 1932 } 1933 1934 return true; 1935 } 1936 1937 bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const { 1938 return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() && 1939 MF.getSubtarget<PPCSubtarget>().isPPC64()); 1940 } 1941