1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PPC implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCFrameLowering.h" 15 #include "PPCInstrBuilder.h" 16 #include "PPCInstrInfo.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCSubtarget.h" 19 #include "PPCTargetMachine.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/RegisterScavenging.h" 26 #include "llvm/IR/Function.h" 27 #include "llvm/Target/TargetOptions.h" 28 29 using namespace llvm; 30 31 /// VRRegNo - Map from a numbered VR register to its enum value. 32 /// 33 static const MCPhysReg VRRegNo[] = { 34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 38 }; 39 40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) { 41 if (STI.isDarwinABI()) 42 return STI.isPPC64() ? 16 : 8; 43 // SVR4 ABI: 44 return STI.isPPC64() ? 16 : 4; 45 } 46 47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) { 48 return STI.isELFv2ABI() ? 24 : 40; 49 } 50 51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) { 52 // For the Darwin ABI: 53 // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area 54 // for saving the frame pointer (if needed.) While the published ABI has 55 // not used this slot since at least MacOSX 10.2, there is older code 56 // around that does use it, and that needs to continue to work. 57 if (STI.isDarwinABI()) 58 return STI.isPPC64() ? -8U : -4U; 59 60 // SVR4 ABI: First slot in the general register save area. 61 return STI.isPPC64() ? -8U : -4U; 62 } 63 64 static unsigned computeLinkageSize(const PPCSubtarget &STI) { 65 if (STI.isDarwinABI() || STI.isPPC64()) 66 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4); 67 68 // SVR4 ABI: 69 return 8; 70 } 71 72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) { 73 if (STI.isDarwinABI()) 74 return STI.isPPC64() ? -16U : -8U; 75 76 // SVR4 ABI: First slot in the general register save area. 77 return STI.isPPC64() 78 ? -16U 79 : (STI.getTargetMachine().getRelocationModel() == Reloc::PIC_) 80 ? -12U 81 : -8U; 82 } 83 84 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI) 85 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 86 STI.getPlatformStackAlignment(), 0), 87 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), 88 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), 89 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), 90 LinkageSize(computeLinkageSize(Subtarget)), 91 BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {} 92 93 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. 94 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots( 95 unsigned &NumEntries) const { 96 if (Subtarget.isDarwinABI()) { 97 NumEntries = 1; 98 if (Subtarget.isPPC64()) { 99 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; 100 return &darwin64Offsets; 101 } else { 102 static const SpillSlot darwinOffsets = {PPC::R31, -4}; 103 return &darwinOffsets; 104 } 105 } 106 107 // Early exit if not using the SVR4 ABI. 108 if (!Subtarget.isSVR4ABI()) { 109 NumEntries = 0; 110 return nullptr; 111 } 112 113 // Note that the offsets here overlap, but this is fixed up in 114 // processFunctionBeforeFrameFinalized. 115 116 static const SpillSlot Offsets[] = { 117 // Floating-point register save area offsets. 118 {PPC::F31, -8}, 119 {PPC::F30, -16}, 120 {PPC::F29, -24}, 121 {PPC::F28, -32}, 122 {PPC::F27, -40}, 123 {PPC::F26, -48}, 124 {PPC::F25, -56}, 125 {PPC::F24, -64}, 126 {PPC::F23, -72}, 127 {PPC::F22, -80}, 128 {PPC::F21, -88}, 129 {PPC::F20, -96}, 130 {PPC::F19, -104}, 131 {PPC::F18, -112}, 132 {PPC::F17, -120}, 133 {PPC::F16, -128}, 134 {PPC::F15, -136}, 135 {PPC::F14, -144}, 136 137 // General register save area offsets. 138 {PPC::R31, -4}, 139 {PPC::R30, -8}, 140 {PPC::R29, -12}, 141 {PPC::R28, -16}, 142 {PPC::R27, -20}, 143 {PPC::R26, -24}, 144 {PPC::R25, -28}, 145 {PPC::R24, -32}, 146 {PPC::R23, -36}, 147 {PPC::R22, -40}, 148 {PPC::R21, -44}, 149 {PPC::R20, -48}, 150 {PPC::R19, -52}, 151 {PPC::R18, -56}, 152 {PPC::R17, -60}, 153 {PPC::R16, -64}, 154 {PPC::R15, -68}, 155 {PPC::R14, -72}, 156 157 // CR save area offset. We map each of the nonvolatile CR fields 158 // to the slot for CR2, which is the first of the nonvolatile CR 159 // fields to be assigned, so that we only allocate one save slot. 160 // See PPCRegisterInfo::hasReservedSpillSlot() for more information. 161 {PPC::CR2, -4}, 162 163 // VRSAVE save area offset. 164 {PPC::VRSAVE, -4}, 165 166 // Vector register save area 167 {PPC::V31, -16}, 168 {PPC::V30, -32}, 169 {PPC::V29, -48}, 170 {PPC::V28, -64}, 171 {PPC::V27, -80}, 172 {PPC::V26, -96}, 173 {PPC::V25, -112}, 174 {PPC::V24, -128}, 175 {PPC::V23, -144}, 176 {PPC::V22, -160}, 177 {PPC::V21, -176}, 178 {PPC::V20, -192}}; 179 180 static const SpillSlot Offsets64[] = { 181 // Floating-point register save area offsets. 182 {PPC::F31, -8}, 183 {PPC::F30, -16}, 184 {PPC::F29, -24}, 185 {PPC::F28, -32}, 186 {PPC::F27, -40}, 187 {PPC::F26, -48}, 188 {PPC::F25, -56}, 189 {PPC::F24, -64}, 190 {PPC::F23, -72}, 191 {PPC::F22, -80}, 192 {PPC::F21, -88}, 193 {PPC::F20, -96}, 194 {PPC::F19, -104}, 195 {PPC::F18, -112}, 196 {PPC::F17, -120}, 197 {PPC::F16, -128}, 198 {PPC::F15, -136}, 199 {PPC::F14, -144}, 200 201 // General register save area offsets. 202 {PPC::X31, -8}, 203 {PPC::X30, -16}, 204 {PPC::X29, -24}, 205 {PPC::X28, -32}, 206 {PPC::X27, -40}, 207 {PPC::X26, -48}, 208 {PPC::X25, -56}, 209 {PPC::X24, -64}, 210 {PPC::X23, -72}, 211 {PPC::X22, -80}, 212 {PPC::X21, -88}, 213 {PPC::X20, -96}, 214 {PPC::X19, -104}, 215 {PPC::X18, -112}, 216 {PPC::X17, -120}, 217 {PPC::X16, -128}, 218 {PPC::X15, -136}, 219 {PPC::X14, -144}, 220 221 // VRSAVE save area offset. 222 {PPC::VRSAVE, -4}, 223 224 // Vector register save area 225 {PPC::V31, -16}, 226 {PPC::V30, -32}, 227 {PPC::V29, -48}, 228 {PPC::V28, -64}, 229 {PPC::V27, -80}, 230 {PPC::V26, -96}, 231 {PPC::V25, -112}, 232 {PPC::V24, -128}, 233 {PPC::V23, -144}, 234 {PPC::V22, -160}, 235 {PPC::V21, -176}, 236 {PPC::V20, -192}}; 237 238 if (Subtarget.isPPC64()) { 239 NumEntries = array_lengthof(Offsets64); 240 241 return Offsets64; 242 } else { 243 NumEntries = array_lengthof(Offsets); 244 245 return Offsets; 246 } 247 } 248 249 /// RemoveVRSaveCode - We have found that this function does not need any code 250 /// to manipulate the VRSAVE register, even though it uses vector registers. 251 /// This can happen when the only registers used are known to be live in or out 252 /// of the function. Remove all of the VRSAVE related code from the function. 253 /// FIXME: The removal of the code results in a compile failure at -O0 when the 254 /// function contains a function call, as the GPR containing original VRSAVE 255 /// contents is spilled and reloaded around the call. Without the prolog code, 256 /// the spill instruction refers to an undefined register. This code needs 257 /// to account for all uses of that GPR. 258 static void RemoveVRSaveCode(MachineInstr *MI) { 259 MachineBasicBlock *Entry = MI->getParent(); 260 MachineFunction *MF = Entry->getParent(); 261 262 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 263 MachineBasicBlock::iterator MBBI = MI; 264 ++MBBI; 265 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 266 MBBI->eraseFromParent(); 267 268 bool RemovedAllMTVRSAVEs = true; 269 // See if we can find and remove the MTVRSAVE instruction from all of the 270 // epilog blocks. 271 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 272 // If last instruction is a return instruction, add an epilogue 273 if (I->isReturnBlock()) { 274 bool FoundIt = false; 275 for (MBBI = I->end(); MBBI != I->begin(); ) { 276 --MBBI; 277 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 278 MBBI->eraseFromParent(); // remove it. 279 FoundIt = true; 280 break; 281 } 282 } 283 RemovedAllMTVRSAVEs &= FoundIt; 284 } 285 } 286 287 // If we found and removed all MTVRSAVE instructions, remove the read of 288 // VRSAVE as well. 289 if (RemovedAllMTVRSAVEs) { 290 MBBI = MI; 291 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 292 --MBBI; 293 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 294 MBBI->eraseFromParent(); 295 } 296 297 // Finally, nuke the UPDATE_VRSAVE. 298 MI->eraseFromParent(); 299 } 300 301 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 302 // instruction selector. Based on the vector registers that have been used, 303 // transform this into the appropriate ORI instruction. 304 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 305 MachineFunction *MF = MI->getParent()->getParent(); 306 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 307 DebugLoc dl = MI->getDebugLoc(); 308 309 const MachineRegisterInfo &MRI = MF->getRegInfo(); 310 unsigned UsedRegMask = 0; 311 for (unsigned i = 0; i != 32; ++i) 312 if (MRI.isPhysRegModified(VRRegNo[i])) 313 UsedRegMask |= 1 << (31-i); 314 315 // Live in and live out values already must be in the mask, so don't bother 316 // marking them. 317 for (MachineRegisterInfo::livein_iterator 318 I = MF->getRegInfo().livein_begin(), 319 E = MF->getRegInfo().livein_end(); I != E; ++I) { 320 unsigned RegNo = TRI->getEncodingValue(I->first); 321 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 322 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 323 } 324 325 // Live out registers appear as use operands on return instructions. 326 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 327 UsedRegMask != 0 && BI != BE; ++BI) { 328 const MachineBasicBlock &MBB = *BI; 329 if (!MBB.isReturnBlock()) 330 continue; 331 const MachineInstr &Ret = MBB.back(); 332 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 333 const MachineOperand &MO = Ret.getOperand(I); 334 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 335 continue; 336 unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 337 UsedRegMask &= ~(1 << (31-RegNo)); 338 } 339 } 340 341 // If no registers are used, turn this into a copy. 342 if (UsedRegMask == 0) { 343 // Remove all VRSAVE code. 344 RemoveVRSaveCode(MI); 345 return; 346 } 347 348 unsigned SrcReg = MI->getOperand(1).getReg(); 349 unsigned DstReg = MI->getOperand(0).getReg(); 350 351 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 352 if (DstReg != SrcReg) 353 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 354 .addReg(SrcReg) 355 .addImm(UsedRegMask); 356 else 357 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 358 .addReg(SrcReg, RegState::Kill) 359 .addImm(UsedRegMask); 360 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 361 if (DstReg != SrcReg) 362 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 363 .addReg(SrcReg) 364 .addImm(UsedRegMask >> 16); 365 else 366 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 367 .addReg(SrcReg, RegState::Kill) 368 .addImm(UsedRegMask >> 16); 369 } else { 370 if (DstReg != SrcReg) 371 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 372 .addReg(SrcReg) 373 .addImm(UsedRegMask >> 16); 374 else 375 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 376 .addReg(SrcReg, RegState::Kill) 377 .addImm(UsedRegMask >> 16); 378 379 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 380 .addReg(DstReg, RegState::Kill) 381 .addImm(UsedRegMask & 0xFFFF); 382 } 383 384 // Remove the old UPDATE_VRSAVE instruction. 385 MI->eraseFromParent(); 386 } 387 388 static bool spillsCR(const MachineFunction &MF) { 389 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 390 return FuncInfo->isCRSpilled(); 391 } 392 393 static bool spillsVRSAVE(const MachineFunction &MF) { 394 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 395 return FuncInfo->isVRSAVESpilled(); 396 } 397 398 static bool hasSpills(const MachineFunction &MF) { 399 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 400 return FuncInfo->hasSpills(); 401 } 402 403 static bool hasNonRISpills(const MachineFunction &MF) { 404 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 405 return FuncInfo->hasNonRISpills(); 406 } 407 408 /// MustSaveLR - Return true if this function requires that we save the LR 409 /// register onto the stack in the prolog and restore it in the epilog of the 410 /// function. 411 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 412 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 413 414 // We need a save/restore of LR if there is any def of LR (which is 415 // defined by calls, including the PIC setup sequence), or if there is 416 // some use of the LR stack slot (e.g. for builtin_return_address). 417 // (LR comes in 32 and 64 bit versions.) 418 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 419 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 420 } 421 422 /// determineFrameLayout - Determine the size of the frame and maximum call 423 /// frame size. 424 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 425 bool UpdateMF, 426 bool UseEstimate) const { 427 MachineFrameInfo *MFI = MF.getFrameInfo(); 428 429 // Get the number of bytes to allocate from the FrameInfo 430 unsigned FrameSize = 431 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 432 433 // Get stack alignments. The frame must be aligned to the greatest of these: 434 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI 435 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame 436 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1; 437 438 const PPCRegisterInfo *RegInfo = 439 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 440 441 // If we are a leaf function, and use up to 224 bytes of stack space, 442 // don't have a frame pointer, calls, or dynamic alloca then we do not need 443 // to adjust the stack pointer (we fit in the Red Zone). 444 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 445 // stackless code if all local vars are reg-allocated. 446 bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone); 447 unsigned LR = RegInfo->getRARegister(); 448 if (!DisableRedZone && 449 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 450 !Subtarget.isSVR4ABI() || // allocated locals. 451 FrameSize == 0) && 452 FrameSize <= 224 && // Fits in red zone. 453 !MFI->hasVarSizedObjects() && // No dynamic alloca. 454 !MFI->adjustsStack() && // No calls. 455 !MustSaveLR(MF, LR) && 456 !RegInfo->hasBasePointer(MF)) { // No special alignment. 457 // No need for frame 458 if (UpdateMF) 459 MFI->setStackSize(0); 460 return 0; 461 } 462 463 // Get the maximum call frame size of all the calls. 464 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 465 466 // Maximum call frame needs to be at least big enough for linkage area. 467 unsigned minCallFrameSize = getLinkageSize(); 468 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 469 470 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 471 // that allocations will be aligned. 472 if (MFI->hasVarSizedObjects()) 473 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 474 475 // Update maximum call frame size. 476 if (UpdateMF) 477 MFI->setMaxCallFrameSize(maxCallFrameSize); 478 479 // Include call frame size in total. 480 FrameSize += maxCallFrameSize; 481 482 // Make sure the frame is aligned. 483 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 484 485 // Update frame info. 486 if (UpdateMF) 487 MFI->setStackSize(FrameSize); 488 489 return FrameSize; 490 } 491 492 // hasFP - Return true if the specified function actually has a dedicated frame 493 // pointer register. 494 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 495 const MachineFrameInfo *MFI = MF.getFrameInfo(); 496 // FIXME: This is pretty much broken by design: hasFP() might be called really 497 // early, before the stack layout was calculated and thus hasFP() might return 498 // true or false here depending on the time of call. 499 return (MFI->getStackSize()) && needsFP(MF); 500 } 501 502 // needsFP - Return true if the specified function should have a dedicated frame 503 // pointer register. This is true if the function has variable sized allocas or 504 // if frame pointer elimination is disabled. 505 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 506 const MachineFrameInfo *MFI = MF.getFrameInfo(); 507 508 // Naked functions have no stack frame pushed, so we don't have a frame 509 // pointer. 510 if (MF.getFunction()->hasFnAttribute(Attribute::Naked)) 511 return false; 512 513 return MF.getTarget().Options.DisableFramePointerElim(MF) || 514 MFI->hasVarSizedObjects() || 515 MFI->hasStackMap() || MFI->hasPatchPoint() || 516 (MF.getTarget().Options.GuaranteedTailCallOpt && 517 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 518 } 519 520 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 521 bool is31 = needsFP(MF); 522 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 523 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 524 525 const PPCRegisterInfo *RegInfo = 526 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 527 bool HasBP = RegInfo->hasBasePointer(MF); 528 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; 529 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg; 530 531 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 532 BI != BE; ++BI) 533 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 534 --MBBI; 535 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 536 MachineOperand &MO = MBBI->getOperand(I); 537 if (!MO.isReg()) 538 continue; 539 540 switch (MO.getReg()) { 541 case PPC::FP: 542 MO.setReg(FPReg); 543 break; 544 case PPC::FP8: 545 MO.setReg(FP8Reg); 546 break; 547 case PPC::BP: 548 MO.setReg(BPReg); 549 break; 550 case PPC::BP8: 551 MO.setReg(BP8Reg); 552 break; 553 554 } 555 } 556 } 557 } 558 559 /* This function will do the following: 560 - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12 561 respectively (defaults recommended by the ABI) and return true 562 - If MBB is not an entry block, initialize the register scavenger and look 563 for available registers. 564 - If the defaults (R0/R12) are available, return true 565 - If TwoUniqueRegsRequired is set to true, it looks for two unique 566 registers. Otherwise, look for a single available register. 567 - If the required registers are found, set SR1 and SR2 and return true. 568 - If the required registers are not found, set SR2 or both SR1 and SR2 to 569 PPC::NoRegister and return false. 570 571 Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired 572 is not set, this function will attempt to find two different registers, but 573 still return true if only one register is available (and set SR1 == SR2). 574 */ 575 bool 576 PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, 577 bool UseAtEnd, 578 bool TwoUniqueRegsRequired, 579 unsigned *SR1, 580 unsigned *SR2) const { 581 RegScavenger RS; 582 unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0; 583 unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; 584 585 // Set the defaults for the two scratch registers. 586 if (SR1) 587 *SR1 = R0; 588 589 if (SR2) { 590 assert (SR1 && "Asking for the second scratch register but not the first?"); 591 *SR2 = R12; 592 } 593 594 // If MBB is an entry or exit block, use R0 and R12 as the scratch registers. 595 if ((UseAtEnd && MBB->isReturnBlock()) || 596 (!UseAtEnd && (&MBB->getParent()->front() == MBB))) 597 return true; 598 599 RS.enterBasicBlock(*MBB); 600 601 if (UseAtEnd && !MBB->empty()) { 602 // The scratch register will be used at the end of the block, so must 603 // consider all registers used within the block 604 605 MachineBasicBlock::iterator MBBI = MBB->getFirstTerminator(); 606 // If no terminator, back iterator up to previous instruction. 607 if (MBBI == MBB->end()) 608 MBBI = std::prev(MBBI); 609 610 if (MBBI != MBB->begin()) 611 RS.forward(MBBI); 612 } 613 614 // If the two registers are available, we're all good. 615 // Note that we only return here if both R0 and R12 are available because 616 // although the function may not require two unique registers, it may benefit 617 // from having two so we should try to provide them. 618 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) 619 return true; 620 621 // Get the list of callee-saved registers for the target. 622 const PPCRegisterInfo *RegInfo = 623 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 624 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); 625 626 // Get all the available registers in the block. 627 BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass : 628 &PPC::GPRCRegClass); 629 630 // We shouldn't use callee-saved registers as scratch registers as they may be 631 // available when looking for a candidate block for shrink wrapping but not 632 // available when the actual prologue/epilogue is being emitted because they 633 // were added as live-in to the prologue block by PrologueEpilogueInserter. 634 for (int i = 0; CSRegs[i]; ++i) 635 BV.reset(CSRegs[i]); 636 637 // Set the first scratch register to the first available one. 638 if (SR1) { 639 int FirstScratchReg = BV.find_first(); 640 *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg; 641 } 642 643 // If there is another one available, set the second scratch register to that. 644 // Otherwise, set it to either PPC::NoRegister if this function requires two 645 // or to whatever SR1 is set to if this function doesn't require two. 646 if (SR2) { 647 int SecondScratchReg = BV.find_next(*SR1); 648 if (SecondScratchReg != -1) 649 *SR2 = SecondScratchReg; 650 else 651 *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1; 652 } 653 654 // Now that we've done our best to provide both registers, double check 655 // whether we were unable to provide enough. 656 if (BV.count() < (TwoUniqueRegsRequired ? 2U : 1U)) 657 return false; 658 659 return true; 660 } 661 662 // We need a scratch register for spilling LR and for spilling CR. By default, 663 // we use two scratch registers to hide latency. However, if only one scratch 664 // register is available, we can adjust for that by not overlapping the spill 665 // code. However, if we need to realign the stack (i.e. have a base pointer) 666 // and the stack frame is large, we need two scratch registers. 667 bool 668 PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const { 669 const PPCRegisterInfo *RegInfo = 670 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 671 MachineFunction &MF = *(MBB->getParent()); 672 bool HasBP = RegInfo->hasBasePointer(MF); 673 unsigned FrameSize = determineFrameLayout(MF, false); 674 int NegFrameSize = -FrameSize; 675 bool IsLargeFrame = !isInt<16>(NegFrameSize); 676 MachineFrameInfo *MFI = MF.getFrameInfo(); 677 unsigned MaxAlign = MFI->getMaxAlignment(); 678 679 return IsLargeFrame && HasBP && MaxAlign > 1; 680 } 681 682 bool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { 683 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 684 685 return findScratchRegister(TmpMBB, false, 686 twoUniqueScratchRegsRequired(TmpMBB)); 687 } 688 689 bool PPCFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { 690 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 691 692 return findScratchRegister(TmpMBB, true); 693 } 694 695 void PPCFrameLowering::emitPrologue(MachineFunction &MF, 696 MachineBasicBlock &MBB) const { 697 MachineBasicBlock::iterator MBBI = MBB.begin(); 698 MachineFrameInfo *MFI = MF.getFrameInfo(); 699 const PPCInstrInfo &TII = 700 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 701 const PPCRegisterInfo *RegInfo = 702 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 703 704 MachineModuleInfo &MMI = MF.getMMI(); 705 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 706 DebugLoc dl; 707 bool needsCFI = MMI.hasDebugInfo() || 708 MF.getFunction()->needsUnwindTableEntry(); 709 710 // Get processor type. 711 bool isPPC64 = Subtarget.isPPC64(); 712 // Get the ABI. 713 bool isSVR4ABI = Subtarget.isSVR4ABI(); 714 bool isELFv2ABI = Subtarget.isELFv2ABI(); 715 assert((Subtarget.isDarwinABI() || isSVR4ABI) && 716 "Currently only Darwin and SVR4 ABIs are supported for PowerPC."); 717 718 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 719 // process it. 720 if (!isSVR4ABI) 721 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 722 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 723 HandleVRSaveUpdate(MBBI, TII); 724 break; 725 } 726 } 727 728 // Move MBBI back to the beginning of the prologue block. 729 MBBI = MBB.begin(); 730 731 // Work out frame sizes. 732 unsigned FrameSize = determineFrameLayout(MF); 733 int NegFrameSize = -FrameSize; 734 if (!isInt<32>(NegFrameSize)) 735 llvm_unreachable("Unhandled stack size!"); 736 737 if (MFI->isFrameAddressTaken()) 738 replaceFPWithRealFP(MF); 739 740 // Check if the link register (LR) must be saved. 741 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 742 bool MustSaveLR = FI->mustSaveLR(); 743 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 744 bool MustSaveCR = !MustSaveCRs.empty(); 745 // Do we have a frame pointer and/or base pointer for this function? 746 bool HasFP = hasFP(MF); 747 bool HasBP = RegInfo->hasBasePointer(MF); 748 749 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 750 unsigned BPReg = RegInfo->getBaseRegister(MF); 751 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 752 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR; 753 unsigned ScratchReg = 0; 754 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 755 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.) 756 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 757 : PPC::MFLR ); 758 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD 759 : PPC::STW ); 760 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU 761 : PPC::STWU ); 762 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX 763 : PPC::STWUX); 764 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8 765 : PPC::LIS ); 766 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 767 : PPC::ORI ); 768 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 769 : PPC::OR ); 770 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8 771 : PPC::SUBFC); 772 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8 773 : PPC::SUBFIC); 774 775 // Regarding this assert: Even though LR is saved in the caller's frame (i.e., 776 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no 777 // Red Zone, an asynchronous event (a form of "callee") could claim a frame & 778 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR. 779 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && 780 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); 781 782 // Using the same bool variable as below to supress compiler warnings. 783 bool SingleScratchReg = 784 findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB), 785 &ScratchReg, &TempReg); 786 assert(SingleScratchReg && 787 "Required number of registers not available in this block"); 788 789 SingleScratchReg = ScratchReg == TempReg; 790 791 int LROffset = getReturnSaveOffset(); 792 793 int FPOffset = 0; 794 if (HasFP) { 795 if (isSVR4ABI) { 796 MachineFrameInfo *FFI = MF.getFrameInfo(); 797 int FPIndex = FI->getFramePointerSaveIndex(); 798 assert(FPIndex && "No Frame Pointer Save Slot!"); 799 FPOffset = FFI->getObjectOffset(FPIndex); 800 } else { 801 FPOffset = getFramePointerSaveOffset(); 802 } 803 } 804 805 int BPOffset = 0; 806 if (HasBP) { 807 if (isSVR4ABI) { 808 MachineFrameInfo *FFI = MF.getFrameInfo(); 809 int BPIndex = FI->getBasePointerSaveIndex(); 810 assert(BPIndex && "No Base Pointer Save Slot!"); 811 BPOffset = FFI->getObjectOffset(BPIndex); 812 } else { 813 BPOffset = getBasePointerSaveOffset(); 814 } 815 } 816 817 int PBPOffset = 0; 818 if (FI->usesPICBase()) { 819 MachineFrameInfo *FFI = MF.getFrameInfo(); 820 int PBPIndex = FI->getPICBasePointerSaveIndex(); 821 assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 822 PBPOffset = FFI->getObjectOffset(PBPIndex); 823 } 824 825 // Get stack alignments. 826 unsigned MaxAlign = MFI->getMaxAlignment(); 827 if (HasBP && MaxAlign > 1) 828 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 829 "Invalid alignment!"); 830 831 // Frames of 32KB & larger require special handling because they cannot be 832 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand. 833 bool isLargeFrame = !isInt<16>(NegFrameSize); 834 835 assert((isPPC64 || !MustSaveCR) && 836 "Prologue CR saving supported only in 64-bit mode"); 837 838 // If we need to spill the CR and the LR but we don't have two separate 839 // registers available, we must spill them one at a time 840 if (MustSaveCR && SingleScratchReg && MustSaveLR) { 841 // In the ELFv2 ABI, we are not required to save all CR fields. 842 // If only one or two CR fields are clobbered, it is more efficient to use 843 // mfocrf to selectively save just those fields, because mfocrf has short 844 // latency compares to mfcr. 845 unsigned MfcrOpcode = PPC::MFCR8; 846 unsigned CrState = RegState::ImplicitKill; 847 if (isELFv2ABI && MustSaveCRs.size() == 1) { 848 MfcrOpcode = PPC::MFOCRF8; 849 CrState = RegState::Kill; 850 } 851 MachineInstrBuilder MIB = 852 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg); 853 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 854 MIB.addReg(MustSaveCRs[i], CrState); 855 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 856 .addReg(TempReg, getKillRegState(true)) 857 .addImm(8) 858 .addReg(SPReg); 859 } 860 861 if (MustSaveLR) 862 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); 863 864 if (MustSaveCR && 865 !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64 866 // In the ELFv2 ABI, we are not required to save all CR fields. 867 // If only one or two CR fields are clobbered, it is more efficient to use 868 // mfocrf to selectively save just those fields, because mfocrf has short 869 // latency compares to mfcr. 870 unsigned MfcrOpcode = PPC::MFCR8; 871 unsigned CrState = RegState::ImplicitKill; 872 if (isELFv2ABI && MustSaveCRs.size() == 1) { 873 MfcrOpcode = PPC::MFOCRF8; 874 CrState = RegState::Kill; 875 } 876 MachineInstrBuilder MIB = 877 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg); 878 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 879 MIB.addReg(MustSaveCRs[i], CrState); 880 } 881 882 if (HasFP) 883 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 884 BuildMI(MBB, MBBI, dl, StoreInst) 885 .addReg(FPReg) 886 .addImm(FPOffset) 887 .addReg(SPReg); 888 889 if (FI->usesPICBase()) 890 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 891 BuildMI(MBB, MBBI, dl, StoreInst) 892 .addReg(PPC::R30) 893 .addImm(PBPOffset) 894 .addReg(SPReg); 895 896 if (HasBP) 897 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 898 BuildMI(MBB, MBBI, dl, StoreInst) 899 .addReg(BPReg) 900 .addImm(BPOffset) 901 .addReg(SPReg); 902 903 if (MustSaveLR) 904 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 905 BuildMI(MBB, MBBI, dl, StoreInst) 906 .addReg(ScratchReg) 907 .addImm(LROffset) 908 .addReg(SPReg); 909 910 if (MustSaveCR && 911 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 912 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 913 .addReg(TempReg, getKillRegState(true)) 914 .addImm(8) 915 .addReg(SPReg); 916 917 // Skip the rest if this is a leaf function & all spills fit in the Red Zone. 918 if (!FrameSize) return; 919 920 // Adjust stack pointer: r1 += NegFrameSize. 921 // If there is a preferred stack alignment, align R1 now 922 923 if (HasBP) { 924 // Save a copy of r1 as the base pointer. 925 BuildMI(MBB, MBBI, dl, OrInst, BPReg) 926 .addReg(SPReg) 927 .addReg(SPReg); 928 } 929 930 // This condition must be kept in sync with canUseAsPrologue. 931 if (HasBP && MaxAlign > 1) { 932 if (isPPC64) 933 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) 934 .addReg(SPReg) 935 .addImm(0) 936 .addImm(64 - Log2_32(MaxAlign)); 937 else // PPC32... 938 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg) 939 .addReg(SPReg) 940 .addImm(0) 941 .addImm(32 - Log2_32(MaxAlign)) 942 .addImm(31); 943 if (!isLargeFrame) { 944 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg) 945 .addReg(ScratchReg, RegState::Kill) 946 .addImm(NegFrameSize); 947 } else { 948 assert(!SingleScratchReg && "Only a single scratch reg available"); 949 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) 950 .addImm(NegFrameSize >> 16); 951 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg) 952 .addReg(TempReg, RegState::Kill) 953 .addImm(NegFrameSize & 0xFFFF); 954 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg) 955 .addReg(ScratchReg, RegState::Kill) 956 .addReg(TempReg, RegState::Kill); 957 } 958 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 959 .addReg(SPReg, RegState::Kill) 960 .addReg(SPReg) 961 .addReg(ScratchReg); 962 963 } else if (!isLargeFrame) { 964 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg) 965 .addReg(SPReg) 966 .addImm(NegFrameSize) 967 .addReg(SPReg); 968 969 } else { 970 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 971 .addImm(NegFrameSize >> 16); 972 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 973 .addReg(ScratchReg, RegState::Kill) 974 .addImm(NegFrameSize & 0xFFFF); 975 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 976 .addReg(SPReg, RegState::Kill) 977 .addReg(SPReg) 978 .addReg(ScratchReg); 979 } 980 981 // Add Call Frame Information for the instructions we generated above. 982 if (needsCFI) { 983 unsigned CFIIndex; 984 985 if (HasBP) { 986 // Define CFA in terms of BP. Do this in preference to using FP/SP, 987 // because if the stack needed aligning then CFA won't be at a fixed 988 // offset from FP/SP. 989 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 990 CFIIndex = MMI.addFrameInst( 991 MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 992 } else { 993 // Adjust the definition of CFA to account for the change in SP. 994 assert(NegFrameSize); 995 CFIIndex = MMI.addFrameInst( 996 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize)); 997 } 998 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 999 .addCFIIndex(CFIIndex); 1000 1001 if (HasFP) { 1002 // Describe where FP was saved, at a fixed offset from CFA. 1003 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 1004 CFIIndex = MMI.addFrameInst( 1005 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset)); 1006 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1007 .addCFIIndex(CFIIndex); 1008 } 1009 1010 if (FI->usesPICBase()) { 1011 // Describe where FP was saved, at a fixed offset from CFA. 1012 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true); 1013 CFIIndex = MMI.addFrameInst( 1014 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset)); 1015 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1016 .addCFIIndex(CFIIndex); 1017 } 1018 1019 if (HasBP) { 1020 // Describe where BP was saved, at a fixed offset from CFA. 1021 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 1022 CFIIndex = MMI.addFrameInst( 1023 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset)); 1024 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1025 .addCFIIndex(CFIIndex); 1026 } 1027 1028 if (MustSaveLR) { 1029 // Describe where LR was saved, at a fixed offset from CFA. 1030 unsigned Reg = MRI->getDwarfRegNum(LRReg, true); 1031 CFIIndex = MMI.addFrameInst( 1032 MCCFIInstruction::createOffset(nullptr, Reg, LROffset)); 1033 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1034 .addCFIIndex(CFIIndex); 1035 } 1036 } 1037 1038 // If there is a frame pointer, copy R1 into R31 1039 if (HasFP) { 1040 BuildMI(MBB, MBBI, dl, OrInst, FPReg) 1041 .addReg(SPReg) 1042 .addReg(SPReg); 1043 1044 if (!HasBP && needsCFI) { 1045 // Change the definition of CFA from SP+offset to FP+offset, because SP 1046 // will change at every alloca. 1047 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 1048 unsigned CFIIndex = MMI.addFrameInst( 1049 MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 1050 1051 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1052 .addCFIIndex(CFIIndex); 1053 } 1054 } 1055 1056 if (needsCFI) { 1057 // Describe where callee saved registers were saved, at fixed offsets from 1058 // CFA. 1059 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1060 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1061 unsigned Reg = CSI[I].getReg(); 1062 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 1063 1064 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 1065 // subregisters of CR2. We just need to emit a move of CR2. 1066 if (PPC::CRBITRCRegClass.contains(Reg)) 1067 continue; 1068 1069 // For SVR4, don't emit a move for the CR spill slot if we haven't 1070 // spilled CRs. 1071 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 1072 && !MustSaveCR) 1073 continue; 1074 1075 // For 64-bit SVR4 when we have spilled CRs, the spill location 1076 // is SP+8, not a frame-relative slot. 1077 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1078 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for 1079 // the whole CR word. In the ELFv2 ABI, every CR that was 1080 // actually saved gets its own CFI record. 1081 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2; 1082 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1083 nullptr, MRI->getDwarfRegNum(CRReg, true), 8)); 1084 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1085 .addCFIIndex(CFIIndex); 1086 continue; 1087 } 1088 1089 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1090 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1091 nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); 1092 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1093 .addCFIIndex(CFIIndex); 1094 } 1095 } 1096 } 1097 1098 void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 1099 MachineBasicBlock &MBB) const { 1100 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 1101 DebugLoc dl; 1102 1103 if (MBBI != MBB.end()) 1104 dl = MBBI->getDebugLoc(); 1105 1106 const PPCInstrInfo &TII = 1107 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1108 const PPCRegisterInfo *RegInfo = 1109 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1110 1111 // Get alignment info so we know how to restore the SP. 1112 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1113 1114 // Get the number of bytes allocated from the FrameInfo. 1115 int FrameSize = MFI->getStackSize(); 1116 1117 // Get processor type. 1118 bool isPPC64 = Subtarget.isPPC64(); 1119 // Get the ABI. 1120 bool isSVR4ABI = Subtarget.isSVR4ABI(); 1121 1122 // Check if the link register (LR) has been saved. 1123 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1124 bool MustSaveLR = FI->mustSaveLR(); 1125 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 1126 bool MustSaveCR = !MustSaveCRs.empty(); 1127 // Do we have a frame pointer and/or base pointer for this function? 1128 bool HasFP = hasFP(MF); 1129 bool HasBP = RegInfo->hasBasePointer(MF); 1130 1131 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 1132 unsigned BPReg = RegInfo->getBaseRegister(MF); 1133 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 1134 unsigned ScratchReg = 0; 1135 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 1136 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 1137 : PPC::MTLR ); 1138 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD 1139 : PPC::LWZ ); 1140 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8 1141 : PPC::LIS ); 1142 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 1143 : PPC::ORI ); 1144 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8 1145 : PPC::ADDI ); 1146 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 1147 : PPC::ADD4 ); 1148 1149 int LROffset = getReturnSaveOffset(); 1150 1151 int FPOffset = 0; 1152 1153 // Using the same bool variable as below to supress compiler warnings. 1154 bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg, 1155 &TempReg); 1156 assert(SingleScratchReg && 1157 "Could not find an available scratch register"); 1158 1159 SingleScratchReg = ScratchReg == TempReg; 1160 1161 if (HasFP) { 1162 if (isSVR4ABI) { 1163 MachineFrameInfo *FFI = MF.getFrameInfo(); 1164 int FPIndex = FI->getFramePointerSaveIndex(); 1165 assert(FPIndex && "No Frame Pointer Save Slot!"); 1166 FPOffset = FFI->getObjectOffset(FPIndex); 1167 } else { 1168 FPOffset = getFramePointerSaveOffset(); 1169 } 1170 } 1171 1172 int BPOffset = 0; 1173 if (HasBP) { 1174 if (isSVR4ABI) { 1175 MachineFrameInfo *FFI = MF.getFrameInfo(); 1176 int BPIndex = FI->getBasePointerSaveIndex(); 1177 assert(BPIndex && "No Base Pointer Save Slot!"); 1178 BPOffset = FFI->getObjectOffset(BPIndex); 1179 } else { 1180 BPOffset = getBasePointerSaveOffset(); 1181 } 1182 } 1183 1184 int PBPOffset = 0; 1185 if (FI->usesPICBase()) { 1186 MachineFrameInfo *FFI = MF.getFrameInfo(); 1187 int PBPIndex = FI->getPICBasePointerSaveIndex(); 1188 assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 1189 PBPOffset = FFI->getObjectOffset(PBPIndex); 1190 } 1191 1192 bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn()); 1193 1194 if (IsReturnBlock) { 1195 unsigned RetOpcode = MBBI->getOpcode(); 1196 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1197 RetOpcode == PPC::TCRETURNdi || 1198 RetOpcode == PPC::TCRETURNai || 1199 RetOpcode == PPC::TCRETURNri8 || 1200 RetOpcode == PPC::TCRETURNdi8 || 1201 RetOpcode == PPC::TCRETURNai8; 1202 1203 if (UsesTCRet) { 1204 int MaxTCRetDelta = FI->getTailCallSPDelta(); 1205 MachineOperand &StackAdjust = MBBI->getOperand(1); 1206 assert(StackAdjust.isImm() && "Expecting immediate value."); 1207 // Adjust stack pointer. 1208 int StackAdj = StackAdjust.getImm(); 1209 int Delta = StackAdj - MaxTCRetDelta; 1210 assert((Delta >= 0) && "Delta must be positive"); 1211 if (MaxTCRetDelta>0) 1212 FrameSize += (StackAdj +Delta); 1213 else 1214 FrameSize += StackAdj; 1215 } 1216 } 1217 1218 // Frames of 32KB & larger require special handling because they cannot be 1219 // indexed into with a simple LD/LWZ immediate offset operand. 1220 bool isLargeFrame = !isInt<16>(FrameSize); 1221 1222 if (FrameSize) { 1223 // In the prologue, the loaded (or persistent) stack pointer value is offset 1224 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now. 1225 1226 // If this function contained a fastcc call and GuaranteedTailCallOpt is 1227 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1228 // call which invalidates the stack pointer value in SP(0). So we use the 1229 // value of R31 in this case. 1230 if (FI->hasFastCall()) { 1231 assert(HasFP && "Expecting a valid frame pointer."); 1232 if (!isLargeFrame) { 1233 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1234 .addReg(FPReg).addImm(FrameSize); 1235 } else { 1236 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1237 .addImm(FrameSize >> 16); 1238 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1239 .addReg(ScratchReg, RegState::Kill) 1240 .addImm(FrameSize & 0xFFFF); 1241 BuildMI(MBB, MBBI, dl, AddInst) 1242 .addReg(SPReg) 1243 .addReg(FPReg) 1244 .addReg(ScratchReg); 1245 } 1246 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) { 1247 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1248 .addReg(SPReg) 1249 .addImm(FrameSize); 1250 } else { 1251 BuildMI(MBB, MBBI, dl, LoadInst, SPReg) 1252 .addImm(0) 1253 .addReg(SPReg); 1254 } 1255 } 1256 1257 assert((isPPC64 || !MustSaveCR) && 1258 "Epilogue CR restoring supported only in 64-bit mode"); 1259 1260 // If we need to save both the LR and the CR and we only have one available 1261 // scratch register, we must do them one at a time. 1262 if (MustSaveCR && SingleScratchReg && MustSaveLR) { 1263 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 1264 .addImm(8) 1265 .addReg(SPReg); 1266 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1267 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1268 .addReg(TempReg, getKillRegState(i == e-1)); 1269 } 1270 1271 if (MustSaveLR) 1272 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) 1273 .addImm(LROffset) 1274 .addReg(SPReg); 1275 1276 if (MustSaveCR && 1277 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 1278 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 1279 .addImm(8) 1280 .addReg(SPReg); 1281 1282 if (HasFP) 1283 BuildMI(MBB, MBBI, dl, LoadInst, FPReg) 1284 .addImm(FPOffset) 1285 .addReg(SPReg); 1286 1287 if (FI->usesPICBase()) 1288 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 1289 BuildMI(MBB, MBBI, dl, LoadInst) 1290 .addReg(PPC::R30) 1291 .addImm(PBPOffset) 1292 .addReg(SPReg); 1293 1294 if (HasBP) 1295 BuildMI(MBB, MBBI, dl, LoadInst, BPReg) 1296 .addImm(BPOffset) 1297 .addReg(SPReg); 1298 1299 if (MustSaveCR && 1300 !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 1301 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1302 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1303 .addReg(TempReg, getKillRegState(i == e-1)); 1304 1305 if (MustSaveLR) 1306 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg); 1307 1308 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1309 // call optimization 1310 if (IsReturnBlock) { 1311 unsigned RetOpcode = MBBI->getOpcode(); 1312 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1313 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) && 1314 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1315 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1316 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1317 1318 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 1319 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1320 .addReg(SPReg).addImm(CallerAllocatedAmt); 1321 } else { 1322 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1323 .addImm(CallerAllocatedAmt >> 16); 1324 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1325 .addReg(ScratchReg, RegState::Kill) 1326 .addImm(CallerAllocatedAmt & 0xFFFF); 1327 BuildMI(MBB, MBBI, dl, AddInst) 1328 .addReg(SPReg) 1329 .addReg(FPReg) 1330 .addReg(ScratchReg); 1331 } 1332 } else { 1333 createTailCallBranchInstr(MBB); 1334 } 1335 } 1336 } 1337 1338 void PPCFrameLowering::createTailCallBranchInstr(MachineBasicBlock &MBB) const { 1339 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 1340 DebugLoc dl; 1341 1342 if (MBBI != MBB.end()) 1343 dl = MBBI->getDebugLoc(); 1344 1345 const PPCInstrInfo &TII = 1346 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1347 1348 // Create branch instruction for pseudo tail call return instruction 1349 unsigned RetOpcode = MBBI->getOpcode(); 1350 if (RetOpcode == PPC::TCRETURNdi) { 1351 MBBI = MBB.getLastNonDebugInstr(); 1352 MachineOperand &JumpTarget = MBBI->getOperand(0); 1353 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1354 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1355 } else if (RetOpcode == PPC::TCRETURNri) { 1356 MBBI = MBB.getLastNonDebugInstr(); 1357 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1358 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1359 } else if (RetOpcode == PPC::TCRETURNai) { 1360 MBBI = MBB.getLastNonDebugInstr(); 1361 MachineOperand &JumpTarget = MBBI->getOperand(0); 1362 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1363 } else if (RetOpcode == PPC::TCRETURNdi8) { 1364 MBBI = MBB.getLastNonDebugInstr(); 1365 MachineOperand &JumpTarget = MBBI->getOperand(0); 1366 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1367 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1368 } else if (RetOpcode == PPC::TCRETURNri8) { 1369 MBBI = MBB.getLastNonDebugInstr(); 1370 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1371 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1372 } else if (RetOpcode == PPC::TCRETURNai8) { 1373 MBBI = MBB.getLastNonDebugInstr(); 1374 MachineOperand &JumpTarget = MBBI->getOperand(0); 1375 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1376 } 1377 } 1378 1379 void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF, 1380 BitVector &SavedRegs, 1381 RegScavenger *RS) const { 1382 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 1383 1384 const PPCRegisterInfo *RegInfo = 1385 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1386 1387 // Save and clear the LR state. 1388 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1389 unsigned LR = RegInfo->getRARegister(); 1390 FI->setMustSaveLR(MustSaveLR(MF, LR)); 1391 SavedRegs.reset(LR); 1392 1393 // Save R31 if necessary 1394 int FPSI = FI->getFramePointerSaveIndex(); 1395 bool isPPC64 = Subtarget.isPPC64(); 1396 bool isDarwinABI = Subtarget.isDarwinABI(); 1397 MachineFrameInfo *MFI = MF.getFrameInfo(); 1398 1399 // If the frame pointer save index hasn't been defined yet. 1400 if (!FPSI && needsFP(MF)) { 1401 // Find out what the fix offset of the frame pointer save area. 1402 int FPOffset = getFramePointerSaveOffset(); 1403 // Allocate the frame index for frame pointer save area. 1404 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 1405 // Save the result. 1406 FI->setFramePointerSaveIndex(FPSI); 1407 } 1408 1409 int BPSI = FI->getBasePointerSaveIndex(); 1410 if (!BPSI && RegInfo->hasBasePointer(MF)) { 1411 int BPOffset = getBasePointerSaveOffset(); 1412 // Allocate the frame index for the base pointer save area. 1413 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true); 1414 // Save the result. 1415 FI->setBasePointerSaveIndex(BPSI); 1416 } 1417 1418 // Reserve stack space for the PIC Base register (R30). 1419 // Only used in SVR4 32-bit. 1420 if (FI->usesPICBase()) { 1421 int PBPSI = MFI->CreateFixedObject(4, -8, true); 1422 FI->setPICBasePointerSaveIndex(PBPSI); 1423 } 1424 1425 // Reserve stack space to move the linkage area to in case of a tail call. 1426 int TCSPDelta = 0; 1427 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1428 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 1429 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 1430 } 1431 1432 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 1433 // function uses CR 2, 3, or 4. 1434 if (!isPPC64 && !isDarwinABI && 1435 (SavedRegs.test(PPC::CR2) || 1436 SavedRegs.test(PPC::CR3) || 1437 SavedRegs.test(PPC::CR4))) { 1438 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 1439 FI->setCRSpillFrameIndex(FrameIdx); 1440 } 1441 } 1442 1443 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 1444 RegScavenger *RS) const { 1445 // Early exit if not using the SVR4 ABI. 1446 if (!Subtarget.isSVR4ABI()) { 1447 addScavengingSpillSlot(MF, RS); 1448 return; 1449 } 1450 1451 // Get callee saved register information. 1452 MachineFrameInfo *FFI = MF.getFrameInfo(); 1453 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 1454 1455 // If the function is shrink-wrapped, and if the function has a tail call, the 1456 // tail call might not be in the new RestoreBlock, so real branch instruction 1457 // won't be generated by emitEpilogue(), because shrink-wrap has chosen new 1458 // RestoreBlock. So we handle this case here. 1459 if (FFI->getSavePoint() && FFI->hasTailCall()) { 1460 MachineBasicBlock *RestoreBlock = FFI->getRestorePoint(); 1461 for (MachineBasicBlock &MBB : MF) { 1462 if (MBB.isReturnBlock() && (&MBB) != RestoreBlock) 1463 createTailCallBranchInstr(MBB); 1464 } 1465 } 1466 1467 // Early exit if no callee saved registers are modified! 1468 if (CSI.empty() && !needsFP(MF)) { 1469 addScavengingSpillSlot(MF, RS); 1470 return; 1471 } 1472 1473 unsigned MinGPR = PPC::R31; 1474 unsigned MinG8R = PPC::X31; 1475 unsigned MinFPR = PPC::F31; 1476 unsigned MinVR = PPC::V31; 1477 1478 bool HasGPSaveArea = false; 1479 bool HasG8SaveArea = false; 1480 bool HasFPSaveArea = false; 1481 bool HasVRSAVESaveArea = false; 1482 bool HasVRSaveArea = false; 1483 1484 SmallVector<CalleeSavedInfo, 18> GPRegs; 1485 SmallVector<CalleeSavedInfo, 18> G8Regs; 1486 SmallVector<CalleeSavedInfo, 18> FPRegs; 1487 SmallVector<CalleeSavedInfo, 18> VRegs; 1488 1489 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1490 unsigned Reg = CSI[i].getReg(); 1491 if (PPC::GPRCRegClass.contains(Reg)) { 1492 HasGPSaveArea = true; 1493 1494 GPRegs.push_back(CSI[i]); 1495 1496 if (Reg < MinGPR) { 1497 MinGPR = Reg; 1498 } 1499 } else if (PPC::G8RCRegClass.contains(Reg)) { 1500 HasG8SaveArea = true; 1501 1502 G8Regs.push_back(CSI[i]); 1503 1504 if (Reg < MinG8R) { 1505 MinG8R = Reg; 1506 } 1507 } else if (PPC::F8RCRegClass.contains(Reg)) { 1508 HasFPSaveArea = true; 1509 1510 FPRegs.push_back(CSI[i]); 1511 1512 if (Reg < MinFPR) { 1513 MinFPR = Reg; 1514 } 1515 } else if (PPC::CRBITRCRegClass.contains(Reg) || 1516 PPC::CRRCRegClass.contains(Reg)) { 1517 ; // do nothing, as we already know whether CRs are spilled 1518 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 1519 HasVRSAVESaveArea = true; 1520 } else if (PPC::VRRCRegClass.contains(Reg)) { 1521 HasVRSaveArea = true; 1522 1523 VRegs.push_back(CSI[i]); 1524 1525 if (Reg < MinVR) { 1526 MinVR = Reg; 1527 } 1528 } else { 1529 llvm_unreachable("Unknown RegisterClass!"); 1530 } 1531 } 1532 1533 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1534 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1535 1536 int64_t LowerBound = 0; 1537 1538 // Take into account stack space reserved for tail calls. 1539 int TCSPDelta = 0; 1540 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1541 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1542 LowerBound = TCSPDelta; 1543 } 1544 1545 // The Floating-point register save area is right below the back chain word 1546 // of the previous stack frame. 1547 if (HasFPSaveArea) { 1548 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1549 int FI = FPRegs[i].getFrameIdx(); 1550 1551 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1552 } 1553 1554 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 1555 } 1556 1557 // Check whether the frame pointer register is allocated. If so, make sure it 1558 // is spilled to the correct offset. 1559 if (needsFP(MF)) { 1560 HasGPSaveArea = true; 1561 1562 int FI = PFI->getFramePointerSaveIndex(); 1563 assert(FI && "No Frame Pointer Save Slot!"); 1564 1565 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1566 } 1567 1568 if (PFI->usesPICBase()) { 1569 HasGPSaveArea = true; 1570 1571 int FI = PFI->getPICBasePointerSaveIndex(); 1572 assert(FI && "No PIC Base Pointer Save Slot!"); 1573 1574 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1575 } 1576 1577 const PPCRegisterInfo *RegInfo = 1578 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1579 if (RegInfo->hasBasePointer(MF)) { 1580 HasGPSaveArea = true; 1581 1582 int FI = PFI->getBasePointerSaveIndex(); 1583 assert(FI && "No Base Pointer Save Slot!"); 1584 1585 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1586 } 1587 1588 // General register save area starts right below the Floating-point 1589 // register save area. 1590 if (HasGPSaveArea || HasG8SaveArea) { 1591 // Move general register save area spill slots down, taking into account 1592 // the size of the Floating-point register save area. 1593 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1594 int FI = GPRegs[i].getFrameIdx(); 1595 1596 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1597 } 1598 1599 // Move general register save area spill slots down, taking into account 1600 // the size of the Floating-point register save area. 1601 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1602 int FI = G8Regs[i].getFrameIdx(); 1603 1604 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1605 } 1606 1607 unsigned MinReg = 1608 std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1609 TRI->getEncodingValue(MinG8R)); 1610 1611 if (Subtarget.isPPC64()) { 1612 LowerBound -= (31 - MinReg + 1) * 8; 1613 } else { 1614 LowerBound -= (31 - MinReg + 1) * 4; 1615 } 1616 } 1617 1618 // For 32-bit only, the CR save area is below the general register 1619 // save area. For 64-bit SVR4, the CR save area is addressed relative 1620 // to the stack pointer and hence does not need an adjustment here. 1621 // Only CR2 (the first nonvolatile spilled) has an associated frame 1622 // index so that we have a single uniform save area. 1623 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1624 // Adjust the frame index of the CR spill slot. 1625 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1626 unsigned Reg = CSI[i].getReg(); 1627 1628 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1629 // Leave Darwin logic as-is. 1630 || (!Subtarget.isSVR4ABI() && 1631 (PPC::CRBITRCRegClass.contains(Reg) || 1632 PPC::CRRCRegClass.contains(Reg)))) { 1633 int FI = CSI[i].getFrameIdx(); 1634 1635 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1636 } 1637 } 1638 1639 LowerBound -= 4; // The CR save area is always 4 bytes long. 1640 } 1641 1642 if (HasVRSAVESaveArea) { 1643 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1644 // which have the VRSAVE register class? 1645 // Adjust the frame index of the VRSAVE spill slot. 1646 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1647 unsigned Reg = CSI[i].getReg(); 1648 1649 if (PPC::VRSAVERCRegClass.contains(Reg)) { 1650 int FI = CSI[i].getFrameIdx(); 1651 1652 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1653 } 1654 } 1655 1656 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1657 } 1658 1659 if (HasVRSaveArea) { 1660 // Insert alignment padding, we need 16-byte alignment. 1661 LowerBound = (LowerBound - 15) & ~(15); 1662 1663 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1664 int FI = VRegs[i].getFrameIdx(); 1665 1666 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1667 } 1668 } 1669 1670 addScavengingSpillSlot(MF, RS); 1671 } 1672 1673 void 1674 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1675 RegScavenger *RS) const { 1676 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1677 // a large stack, which will require scavenging a register to materialize a 1678 // large offset. 1679 1680 // We need to have a scavenger spill slot for spills if the frame size is 1681 // large. In case there is no free register for large-offset addressing, 1682 // this slot is used for the necessary emergency spill. Also, we need the 1683 // slot for dynamic stack allocations. 1684 1685 // The scavenger might be invoked if the frame offset does not fit into 1686 // the 16-bit immediate. We don't know the complete frame size here 1687 // because we've not yet computed callee-saved register spills or the 1688 // needed alignment padding. 1689 unsigned StackSize = determineFrameLayout(MF, false, true); 1690 MachineFrameInfo *MFI = MF.getFrameInfo(); 1691 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1692 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1693 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1694 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1695 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1696 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1697 RC->getAlignment(), 1698 false)); 1699 1700 // Might we have over-aligned allocas? 1701 bool HasAlVars = MFI->hasVarSizedObjects() && 1702 MFI->getMaxAlignment() > getStackAlignment(); 1703 1704 // These kinds of spills might need two registers. 1705 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars) 1706 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1707 RC->getAlignment(), 1708 false)); 1709 1710 } 1711 } 1712 1713 bool 1714 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1715 MachineBasicBlock::iterator MI, 1716 const std::vector<CalleeSavedInfo> &CSI, 1717 const TargetRegisterInfo *TRI) const { 1718 1719 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1720 // Return false otherwise to maintain pre-existing behavior. 1721 if (!Subtarget.isSVR4ABI()) 1722 return false; 1723 1724 MachineFunction *MF = MBB.getParent(); 1725 const PPCInstrInfo &TII = 1726 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1727 DebugLoc DL; 1728 bool CRSpilled = false; 1729 MachineInstrBuilder CRMIB; 1730 1731 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1732 unsigned Reg = CSI[i].getReg(); 1733 // Only Darwin actually uses the VRSAVE register, but it can still appear 1734 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1735 // Darwin, ignore it. 1736 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1737 continue; 1738 1739 // CR2 through CR4 are the nonvolatile CR fields. 1740 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1741 1742 // Add the callee-saved register as live-in; it's killed at the spill. 1743 MBB.addLiveIn(Reg); 1744 1745 if (CRSpilled && IsCRField) { 1746 CRMIB.addReg(Reg, RegState::ImplicitKill); 1747 continue; 1748 } 1749 1750 // Insert the spill to the stack frame. 1751 if (IsCRField) { 1752 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1753 if (Subtarget.isPPC64()) { 1754 // The actual spill will happen at the start of the prologue. 1755 FuncInfo->addMustSaveCR(Reg); 1756 } else { 1757 CRSpilled = true; 1758 FuncInfo->setSpillsCR(); 1759 1760 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1761 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1762 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) 1763 .addReg(Reg, RegState::ImplicitKill); 1764 1765 MBB.insert(MI, CRMIB); 1766 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1767 .addReg(PPC::R12, 1768 getKillRegState(true)), 1769 CSI[i].getFrameIdx())); 1770 } 1771 } else { 1772 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1773 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1774 CSI[i].getFrameIdx(), RC, TRI); 1775 } 1776 } 1777 return true; 1778 } 1779 1780 static void 1781 restoreCRs(bool isPPC64, bool is31, 1782 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1783 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1784 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1785 1786 MachineFunction *MF = MBB.getParent(); 1787 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 1788 DebugLoc DL; 1789 unsigned RestoreOp, MoveReg; 1790 1791 if (isPPC64) 1792 // This is handled during epilogue generation. 1793 return; 1794 else { 1795 // 32-bit: FP-relative 1796 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1797 PPC::R12), 1798 CSI[CSIIndex].getFrameIdx())); 1799 RestoreOp = PPC::MTOCRF; 1800 MoveReg = PPC::R12; 1801 } 1802 1803 if (CR2Spilled) 1804 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1805 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1806 1807 if (CR3Spilled) 1808 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1809 .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1810 1811 if (CR4Spilled) 1812 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1813 .addReg(MoveReg, getKillRegState(true))); 1814 } 1815 1816 MachineBasicBlock::iterator PPCFrameLowering:: 1817 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1818 MachineBasicBlock::iterator I) const { 1819 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1820 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1821 I->getOpcode() == PPC::ADJCALLSTACKUP) { 1822 // Add (actually subtract) back the amount the callee popped on return. 1823 if (int CalleeAmt = I->getOperand(1).getImm()) { 1824 bool is64Bit = Subtarget.isPPC64(); 1825 CalleeAmt *= -1; 1826 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1827 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1828 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1829 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1830 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1831 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1832 MachineInstr *MI = I; 1833 const DebugLoc &dl = MI->getDebugLoc(); 1834 1835 if (isInt<16>(CalleeAmt)) { 1836 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1837 .addReg(StackReg, RegState::Kill) 1838 .addImm(CalleeAmt); 1839 } else { 1840 MachineBasicBlock::iterator MBBI = I; 1841 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1842 .addImm(CalleeAmt >> 16); 1843 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1844 .addReg(TmpReg, RegState::Kill) 1845 .addImm(CalleeAmt & 0xFFFF); 1846 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1847 .addReg(StackReg, RegState::Kill) 1848 .addReg(TmpReg); 1849 } 1850 } 1851 } 1852 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1853 return MBB.erase(I); 1854 } 1855 1856 bool 1857 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1858 MachineBasicBlock::iterator MI, 1859 const std::vector<CalleeSavedInfo> &CSI, 1860 const TargetRegisterInfo *TRI) const { 1861 1862 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1863 // Return false otherwise to maintain pre-existing behavior. 1864 if (!Subtarget.isSVR4ABI()) 1865 return false; 1866 1867 MachineFunction *MF = MBB.getParent(); 1868 const PPCInstrInfo &TII = 1869 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1870 bool CR2Spilled = false; 1871 bool CR3Spilled = false; 1872 bool CR4Spilled = false; 1873 unsigned CSIIndex = 0; 1874 1875 // Initialize insertion-point logic; we will be restoring in reverse 1876 // order of spill. 1877 MachineBasicBlock::iterator I = MI, BeforeI = I; 1878 bool AtStart = I == MBB.begin(); 1879 1880 if (!AtStart) 1881 --BeforeI; 1882 1883 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1884 unsigned Reg = CSI[i].getReg(); 1885 1886 // Only Darwin actually uses the VRSAVE register, but it can still appear 1887 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1888 // Darwin, ignore it. 1889 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1890 continue; 1891 1892 if (Reg == PPC::CR2) { 1893 CR2Spilled = true; 1894 // The spill slot is associated only with CR2, which is the 1895 // first nonvolatile spilled. Save it here. 1896 CSIIndex = i; 1897 continue; 1898 } else if (Reg == PPC::CR3) { 1899 CR3Spilled = true; 1900 continue; 1901 } else if (Reg == PPC::CR4) { 1902 CR4Spilled = true; 1903 continue; 1904 } else { 1905 // When we first encounter a non-CR register after seeing at 1906 // least one CR register, restore all spilled CRs together. 1907 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1908 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1909 bool is31 = needsFP(*MF); 1910 restoreCRs(Subtarget.isPPC64(), is31, 1911 CR2Spilled, CR3Spilled, CR4Spilled, 1912 MBB, I, CSI, CSIIndex); 1913 CR2Spilled = CR3Spilled = CR4Spilled = false; 1914 } 1915 1916 // Default behavior for non-CR saves. 1917 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1918 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1919 RC, TRI); 1920 assert(I != MBB.begin() && 1921 "loadRegFromStackSlot didn't insert any code!"); 1922 } 1923 1924 // Insert in reverse order. 1925 if (AtStart) 1926 I = MBB.begin(); 1927 else { 1928 I = BeforeI; 1929 ++I; 1930 } 1931 } 1932 1933 // If we haven't yet spilled the CRs, do so now. 1934 if (CR2Spilled || CR3Spilled || CR4Spilled) { 1935 bool is31 = needsFP(*MF); 1936 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1937 MBB, I, CSI, CSIIndex); 1938 } 1939 1940 return true; 1941 } 1942 1943 bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const { 1944 return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() && 1945 MF.getSubtarget<PPCSubtarget>().isPPC64()); 1946 } 1947