1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCTargetDesc.h" 10 #include "TargetInfo/PowerPCTargetInfo.h" 11 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 12 #include "llvm/MC/MCFixedLenDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/Support/Endian.h" 16 #include "llvm/Support/TargetRegistry.h" 17 18 using namespace llvm; 19 20 DEFINE_PPC_REGCLASSES; 21 22 #define DEBUG_TYPE "ppc-disassembler" 23 24 typedef MCDisassembler::DecodeStatus DecodeStatus; 25 26 namespace { 27 class PPCDisassembler : public MCDisassembler { 28 bool IsLittleEndian; 29 30 public: 31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 32 bool IsLittleEndian) 33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 34 35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 36 ArrayRef<uint8_t> Bytes, uint64_t Address, 37 raw_ostream &VStream, 38 raw_ostream &CStream) const override; 39 }; 40 } // end anonymous namespace 41 42 static MCDisassembler *createPPCDisassembler(const Target &T, 43 const MCSubtargetInfo &STI, 44 MCContext &Ctx) { 45 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 46 } 47 48 static MCDisassembler *createPPCLEDisassembler(const Target &T, 49 const MCSubtargetInfo &STI, 50 MCContext &Ctx) { 51 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 52 } 53 54 extern "C" void LLVMInitializePowerPCDisassembler() { 55 // Register the disassembler for each target. 56 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), 57 createPPCDisassembler); 58 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), 59 createPPCDisassembler); 60 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), 61 createPPCLEDisassembler); 62 } 63 64 static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm, 65 uint64_t Addr, 66 const void *Decoder) { 67 int32_t Offset = SignExtend32<24>(Imm); 68 Inst.addOperand(MCOperand::createImm(Offset)); 69 return MCDisassembler::Success; 70 } 71 72 // FIXME: These can be generated by TableGen from the existing register 73 // encoding values! 74 75 template <std::size_t N> 76 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 77 const MCPhysReg (&Regs)[N]) { 78 assert(RegNo < N && "Invalid register number"); 79 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 80 return MCDisassembler::Success; 81 } 82 83 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 84 uint64_t Address, 85 const void *Decoder) { 86 return decodeRegisterClass(Inst, RegNo, CRRegs); 87 } 88 89 static DecodeStatus DecodeCRRC0RegisterClass(MCInst &Inst, uint64_t RegNo, 90 uint64_t Address, 91 const void *Decoder) { 92 return decodeRegisterClass(Inst, RegNo, CRRegs); 93 } 94 95 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 96 uint64_t Address, 97 const void *Decoder) { 98 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 99 } 100 101 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 102 uint64_t Address, 103 const void *Decoder) { 104 return decodeRegisterClass(Inst, RegNo, FRegs); 105 } 106 107 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 108 uint64_t Address, 109 const void *Decoder) { 110 return decodeRegisterClass(Inst, RegNo, FRegs); 111 } 112 113 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 114 uint64_t Address, 115 const void *Decoder) { 116 return decodeRegisterClass(Inst, RegNo, VFRegs); 117 } 118 119 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 120 uint64_t Address, 121 const void *Decoder) { 122 return decodeRegisterClass(Inst, RegNo, VRegs); 123 } 124 125 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 126 uint64_t Address, 127 const void *Decoder) { 128 return decodeRegisterClass(Inst, RegNo, VSRegs); 129 } 130 131 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 132 uint64_t Address, 133 const void *Decoder) { 134 return decodeRegisterClass(Inst, RegNo, VSFRegs); 135 } 136 137 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 138 uint64_t Address, 139 const void *Decoder) { 140 return decodeRegisterClass(Inst, RegNo, VSSRegs); 141 } 142 143 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 144 uint64_t Address, 145 const void *Decoder) { 146 return decodeRegisterClass(Inst, RegNo, RRegs); 147 } 148 149 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 150 uint64_t Address, 151 const void *Decoder) { 152 return decodeRegisterClass(Inst, RegNo, RRegsNoR0); 153 } 154 155 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 156 uint64_t Address, 157 const void *Decoder) { 158 return decodeRegisterClass(Inst, RegNo, XRegs); 159 } 160 161 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, 162 uint64_t Address, 163 const void *Decoder) { 164 return decodeRegisterClass(Inst, RegNo, XRegsNoX0); 165 } 166 167 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 168 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 169 170 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 171 uint64_t Address, 172 const void *Decoder) { 173 return decodeRegisterClass(Inst, RegNo, QFRegs); 174 } 175 176 static DecodeStatus DecodeSPE4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 177 uint64_t Address, 178 const void *Decoder) { 179 return decodeRegisterClass(Inst, RegNo, RRegs); 180 } 181 182 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, 183 uint64_t Address, 184 const void *Decoder) { 185 return decodeRegisterClass(Inst, RegNo, SPERegs); 186 } 187 188 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 189 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 190 191 template<unsigned N> 192 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 193 int64_t Address, const void *Decoder) { 194 assert(isUInt<N>(Imm) && "Invalid immediate"); 195 Inst.addOperand(MCOperand::createImm(Imm)); 196 return MCDisassembler::Success; 197 } 198 199 template<unsigned N> 200 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 201 int64_t Address, const void *Decoder) { 202 assert(isUInt<N>(Imm) && "Invalid immediate"); 203 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 204 return MCDisassembler::Success; 205 } 206 207 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 208 int64_t Address, const void *Decoder) { 209 // Decode the memri field (imm, reg), which has the low 16-bits as the 210 // displacement and the next 5 bits as the register #. 211 212 uint64_t Base = Imm >> 16; 213 uint64_t Disp = Imm & 0xFFFF; 214 215 assert(Base < 32 && "Invalid base register"); 216 217 switch (Inst.getOpcode()) { 218 default: break; 219 case PPC::LBZU: 220 case PPC::LHAU: 221 case PPC::LHZU: 222 case PPC::LWZU: 223 case PPC::LFSU: 224 case PPC::LFDU: 225 // Add the tied output operand. 226 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 227 break; 228 case PPC::STBU: 229 case PPC::STHU: 230 case PPC::STWU: 231 case PPC::STFSU: 232 case PPC::STFDU: 233 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 234 break; 235 } 236 237 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 238 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 239 return MCDisassembler::Success; 240 } 241 242 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 243 int64_t Address, const void *Decoder) { 244 // Decode the memrix field (imm, reg), which has the low 14-bits as the 245 // displacement and the next 5 bits as the register #. 246 247 uint64_t Base = Imm >> 14; 248 uint64_t Disp = Imm & 0x3FFF; 249 250 assert(Base < 32 && "Invalid base register"); 251 252 if (Inst.getOpcode() == PPC::LDU) 253 // Add the tied output operand. 254 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 255 else if (Inst.getOpcode() == PPC::STDU) 256 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 257 258 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 259 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 260 return MCDisassembler::Success; 261 } 262 263 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 264 int64_t Address, const void *Decoder) { 265 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 266 // displacement with 16-byte aligned, and the next 5 bits as the register #. 267 268 uint64_t Base = Imm >> 12; 269 uint64_t Disp = Imm & 0xFFF; 270 271 assert(Base < 32 && "Invalid base register"); 272 273 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 274 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 275 return MCDisassembler::Success; 276 } 277 278 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, 279 int64_t Address, const void *Decoder) { 280 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the 281 // displacement with 8-byte aligned, and the next 5 bits as the register #. 282 283 uint64_t Base = Imm >> 5; 284 uint64_t Disp = Imm & 0x1F; 285 286 assert(Base < 32 && "Invalid base register"); 287 288 Inst.addOperand(MCOperand::createImm(Disp << 3)); 289 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 290 return MCDisassembler::Success; 291 } 292 293 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, 294 int64_t Address, const void *Decoder) { 295 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the 296 // displacement with 4-byte aligned, and the next 5 bits as the register #. 297 298 uint64_t Base = Imm >> 5; 299 uint64_t Disp = Imm & 0x1F; 300 301 assert(Base < 32 && "Invalid base register"); 302 303 Inst.addOperand(MCOperand::createImm(Disp << 2)); 304 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 305 return MCDisassembler::Success; 306 } 307 308 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, 309 int64_t Address, const void *Decoder) { 310 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the 311 // displacement with 2-byte aligned, and the next 5 bits as the register #. 312 313 uint64_t Base = Imm >> 5; 314 uint64_t Disp = Imm & 0x1F; 315 316 assert(Base < 32 && "Invalid base register"); 317 318 Inst.addOperand(MCOperand::createImm(Disp << 1)); 319 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 320 return MCDisassembler::Success; 321 } 322 323 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 324 int64_t Address, const void *Decoder) { 325 // The cr bit encoding is 0x80 >> cr_reg_num. 326 327 unsigned Zeros = countTrailingZeros(Imm); 328 assert(Zeros < 8 && "Invalid CR bit value"); 329 330 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 331 return MCDisassembler::Success; 332 } 333 334 #include "PPCGenDisassemblerTables.inc" 335 336 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 337 ArrayRef<uint8_t> Bytes, 338 uint64_t Address, raw_ostream &OS, 339 raw_ostream &CS) const { 340 // Get the four bytes of the instruction. 341 Size = 4; 342 if (Bytes.size() < 4) { 343 Size = 0; 344 return MCDisassembler::Fail; 345 } 346 347 // Read the instruction in the proper endianness. 348 uint32_t Inst = IsLittleEndian ? support::endian::read32le(Bytes.data()) 349 : support::endian::read32be(Bytes.data()); 350 351 if (STI.getFeatureBits()[PPC::FeatureQPX]) { 352 DecodeStatus result = 353 decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI); 354 if (result != MCDisassembler::Fail) 355 return result; 356 } else if (STI.getFeatureBits()[PPC::FeatureSPE]) { 357 DecodeStatus result = 358 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI); 359 if (result != MCDisassembler::Fail) 360 return result; 361 } 362 363 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 364 } 365 366