1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCTargetDesc.h" 10 #include "TargetInfo/PowerPCTargetInfo.h" 11 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 12 #include "llvm/MC/MCFixedLenDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/Support/Endian.h" 16 #include "llvm/Support/TargetRegistry.h" 17 18 using namespace llvm; 19 20 DEFINE_PPC_REGCLASSES; 21 22 #define DEBUG_TYPE "ppc-disassembler" 23 24 typedef MCDisassembler::DecodeStatus DecodeStatus; 25 26 namespace { 27 class PPCDisassembler : public MCDisassembler { 28 bool IsLittleEndian; 29 30 public: 31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 32 bool IsLittleEndian) 33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 34 35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 36 ArrayRef<uint8_t> Bytes, uint64_t Address, 37 raw_ostream &CStream) const override; 38 }; 39 } // end anonymous namespace 40 41 static MCDisassembler *createPPCDisassembler(const Target &T, 42 const MCSubtargetInfo &STI, 43 MCContext &Ctx) { 44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 45 } 46 47 static MCDisassembler *createPPCLEDisassembler(const Target &T, 48 const MCSubtargetInfo &STI, 49 MCContext &Ctx) { 50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 51 } 52 53 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() { 54 // Register the disassembler for each target. 55 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), 56 createPPCDisassembler); 57 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), 58 createPPCDisassembler); 59 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), 60 createPPCLEDisassembler); 61 } 62 63 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, 64 uint64_t /*Address*/, 65 const void * /*Decoder*/) { 66 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); 67 return MCDisassembler::Success; 68 } 69 70 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, 71 uint64_t /*Address*/, 72 const void * /*Decoder*/) { 73 int32_t Offset = SignExtend32<24>(Imm); 74 Inst.addOperand(MCOperand::createImm(Offset)); 75 return MCDisassembler::Success; 76 } 77 78 // FIXME: These can be generated by TableGen from the existing register 79 // encoding values! 80 81 template <std::size_t N> 82 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 83 const MCPhysReg (&Regs)[N]) { 84 assert(RegNo < N && "Invalid register number"); 85 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 86 return MCDisassembler::Success; 87 } 88 89 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 90 uint64_t Address, 91 const void *Decoder) { 92 return decodeRegisterClass(Inst, RegNo, CRRegs); 93 } 94 95 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 96 uint64_t Address, 97 const void *Decoder) { 98 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 99 } 100 101 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 102 uint64_t Address, 103 const void *Decoder) { 104 return decodeRegisterClass(Inst, RegNo, FRegs); 105 } 106 107 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 108 uint64_t Address, 109 const void *Decoder) { 110 return decodeRegisterClass(Inst, RegNo, FRegs); 111 } 112 113 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 114 uint64_t Address, 115 const void *Decoder) { 116 return decodeRegisterClass(Inst, RegNo, VFRegs); 117 } 118 119 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 120 uint64_t Address, 121 const void *Decoder) { 122 return decodeRegisterClass(Inst, RegNo, VRegs); 123 } 124 125 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 126 uint64_t Address, 127 const void *Decoder) { 128 return decodeRegisterClass(Inst, RegNo, VSRegs); 129 } 130 131 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 132 uint64_t Address, 133 const void *Decoder) { 134 return decodeRegisterClass(Inst, RegNo, VSFRegs); 135 } 136 137 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 138 uint64_t Address, 139 const void *Decoder) { 140 return decodeRegisterClass(Inst, RegNo, VSSRegs); 141 } 142 143 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 144 uint64_t Address, 145 const void *Decoder) { 146 return decodeRegisterClass(Inst, RegNo, RRegs); 147 } 148 149 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 150 uint64_t Address, 151 const void *Decoder) { 152 return decodeRegisterClass(Inst, RegNo, RRegsNoR0); 153 } 154 155 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 156 uint64_t Address, 157 const void *Decoder) { 158 return decodeRegisterClass(Inst, RegNo, XRegs); 159 } 160 161 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, 162 uint64_t Address, 163 const void *Decoder) { 164 return decodeRegisterClass(Inst, RegNo, XRegsNoX0); 165 } 166 167 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 168 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 169 170 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, 171 uint64_t Address, 172 const void *Decoder) { 173 return decodeRegisterClass(Inst, RegNo, SPERegs); 174 } 175 176 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 177 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 178 179 template<unsigned N> 180 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 181 int64_t Address, const void *Decoder) { 182 assert(isUInt<N>(Imm) && "Invalid immediate"); 183 Inst.addOperand(MCOperand::createImm(Imm)); 184 return MCDisassembler::Success; 185 } 186 187 template<unsigned N> 188 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 189 int64_t Address, const void *Decoder) { 190 assert(isUInt<N>(Imm) && "Invalid immediate"); 191 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 192 return MCDisassembler::Success; 193 } 194 195 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, 196 int64_t Address, const void *Decoder) { 197 if (Imm != 0) 198 return MCDisassembler::Fail; 199 Inst.addOperand(MCOperand::createImm(Imm)); 200 return MCDisassembler::Success; 201 } 202 203 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 204 int64_t Address, const void *Decoder) { 205 // Decode the memri field (imm, reg), which has the low 16-bits as the 206 // displacement and the next 5 bits as the register #. 207 208 uint64_t Base = Imm >> 16; 209 uint64_t Disp = Imm & 0xFFFF; 210 211 assert(Base < 32 && "Invalid base register"); 212 213 switch (Inst.getOpcode()) { 214 default: break; 215 case PPC::LBZU: 216 case PPC::LHAU: 217 case PPC::LHZU: 218 case PPC::LWZU: 219 case PPC::LFSU: 220 case PPC::LFDU: 221 // Add the tied output operand. 222 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 223 break; 224 case PPC::STBU: 225 case PPC::STHU: 226 case PPC::STWU: 227 case PPC::STFSU: 228 case PPC::STFDU: 229 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 230 break; 231 } 232 233 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 234 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 235 return MCDisassembler::Success; 236 } 237 238 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 239 int64_t Address, const void *Decoder) { 240 // Decode the memrix field (imm, reg), which has the low 14-bits as the 241 // displacement and the next 5 bits as the register #. 242 243 uint64_t Base = Imm >> 14; 244 uint64_t Disp = Imm & 0x3FFF; 245 246 assert(Base < 32 && "Invalid base register"); 247 248 if (Inst.getOpcode() == PPC::LDU) 249 // Add the tied output operand. 250 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 251 else if (Inst.getOpcode() == PPC::STDU) 252 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 253 254 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 255 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 256 return MCDisassembler::Success; 257 } 258 259 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 260 int64_t Address, const void *Decoder) { 261 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 262 // displacement with 16-byte aligned, and the next 5 bits as the register #. 263 264 uint64_t Base = Imm >> 12; 265 uint64_t Disp = Imm & 0xFFF; 266 267 assert(Base < 32 && "Invalid base register"); 268 269 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 270 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 271 return MCDisassembler::Success; 272 } 273 274 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm, 275 int64_t Address, 276 const void *Decoder) { 277 // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the 278 // displacement, and the next 5 bits as an immediate 0. 279 uint64_t Base = Imm >> 34; 280 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 281 282 assert(Base < 32 && "Invalid base register"); 283 284 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 285 return decodeImmZeroOperand(Inst, Base, Address, Decoder); 286 } 287 288 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm, 289 int64_t Address, 290 const void *Decoder) { 291 // Decode the memri34 field (imm, reg), which has the low 34-bits as the 292 // displacement, and the next 5 bits as the register #. 293 uint64_t Base = Imm >> 34; 294 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 295 296 assert(Base < 32 && "Invalid base register"); 297 298 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 299 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 300 return MCDisassembler::Success; 301 } 302 303 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, 304 int64_t Address, const void *Decoder) { 305 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the 306 // displacement with 8-byte aligned, and the next 5 bits as the register #. 307 308 uint64_t Base = Imm >> 5; 309 uint64_t Disp = Imm & 0x1F; 310 311 assert(Base < 32 && "Invalid base register"); 312 313 Inst.addOperand(MCOperand::createImm(Disp << 3)); 314 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 315 return MCDisassembler::Success; 316 } 317 318 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, 319 int64_t Address, const void *Decoder) { 320 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the 321 // displacement with 4-byte aligned, and the next 5 bits as the register #. 322 323 uint64_t Base = Imm >> 5; 324 uint64_t Disp = Imm & 0x1F; 325 326 assert(Base < 32 && "Invalid base register"); 327 328 Inst.addOperand(MCOperand::createImm(Disp << 2)); 329 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 330 return MCDisassembler::Success; 331 } 332 333 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, 334 int64_t Address, const void *Decoder) { 335 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the 336 // displacement with 2-byte aligned, and the next 5 bits as the register #. 337 338 uint64_t Base = Imm >> 5; 339 uint64_t Disp = Imm & 0x1F; 340 341 assert(Base < 32 && "Invalid base register"); 342 343 Inst.addOperand(MCOperand::createImm(Disp << 1)); 344 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 345 return MCDisassembler::Success; 346 } 347 348 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 349 int64_t Address, const void *Decoder) { 350 // The cr bit encoding is 0x80 >> cr_reg_num. 351 352 unsigned Zeros = countTrailingZeros(Imm); 353 assert(Zeros < 8 && "Invalid CR bit value"); 354 355 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 356 return MCDisassembler::Success; 357 } 358 359 #include "PPCGenDisassemblerTables.inc" 360 361 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 362 ArrayRef<uint8_t> Bytes, 363 uint64_t Address, 364 raw_ostream &CS) const { 365 auto *ReadFunc = IsLittleEndian ? support::endian::read32le 366 : support::endian::read32be; 367 368 // If this is an 8-byte prefixed instruction, handle it here. 369 // Note: prefixed instructions aren't technically 8-byte entities - the prefix 370 // appears in memory at an address 4 bytes prior to that of the base 371 // instruction regardless of endianness. So we read the two pieces and 372 // rebuild the 8-byte instruction. 373 // TODO: In this function we call decodeInstruction several times with 374 // different decoder tables. It may be possible to only call once by 375 // looking at the top 6 bits of the instruction. 376 if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) { 377 uint32_t Prefix = ReadFunc(Bytes.data()); 378 uint32_t BaseInst = ReadFunc(Bytes.data() + 4); 379 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32; 380 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address, 381 this, STI); 382 if (result != MCDisassembler::Fail) { 383 Size = 8; 384 return result; 385 } 386 } 387 388 // Get the four bytes of the instruction. 389 Size = 4; 390 if (Bytes.size() < 4) { 391 Size = 0; 392 return MCDisassembler::Fail; 393 } 394 395 // Read the instruction in the proper endianness. 396 uint64_t Inst = ReadFunc(Bytes.data()); 397 398 if (STI.getFeatureBits()[PPC::FeatureSPE]) { 399 DecodeStatus result = 400 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI); 401 if (result != MCDisassembler::Fail) 402 return result; 403 } 404 405 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 406 } 407