1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCTargetDesc.h" 10 #include "TargetInfo/PowerPCTargetInfo.h" 11 #include "llvm/MC/MCDecoderOps.h" 12 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/MC/TargetRegistry.h" 16 #include "llvm/Support/Endian.h" 17 18 using namespace llvm; 19 20 DEFINE_PPC_REGCLASSES 21 22 #define DEBUG_TYPE "ppc-disassembler" 23 24 typedef MCDisassembler::DecodeStatus DecodeStatus; 25 26 namespace { 27 class PPCDisassembler : public MCDisassembler { 28 bool IsLittleEndian; 29 30 public: 31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 32 bool IsLittleEndian) 33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 34 35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 36 ArrayRef<uint8_t> Bytes, uint64_t Address, 37 raw_ostream &CStream) const override; 38 }; 39 } // end anonymous namespace 40 41 static MCDisassembler *createPPCDisassembler(const Target &T, 42 const MCSubtargetInfo &STI, 43 MCContext &Ctx) { 44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 45 } 46 47 static MCDisassembler *createPPCLEDisassembler(const Target &T, 48 const MCSubtargetInfo &STI, 49 MCContext &Ctx) { 50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 51 } 52 53 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() { 54 // Register the disassembler for each target. 55 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), 56 createPPCDisassembler); 57 TargetRegistry::RegisterMCDisassembler(getThePPC32LETarget(), 58 createPPCLEDisassembler); 59 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), 60 createPPCDisassembler); 61 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), 62 createPPCLEDisassembler); 63 } 64 65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, 66 uint64_t /*Address*/, 67 const MCDisassembler * /*Decoder*/) { 68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); 69 return MCDisassembler::Success; 70 } 71 72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, 73 uint64_t /*Address*/, 74 const MCDisassembler * /*Decoder*/) { 75 int32_t Offset = SignExtend32<24>(Imm); 76 Inst.addOperand(MCOperand::createImm(Offset)); 77 return MCDisassembler::Success; 78 } 79 80 // FIXME: These can be generated by TableGen from the existing register 81 // encoding values! 82 83 template <std::size_t N> 84 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 85 const MCPhysReg (&Regs)[N]) { 86 assert(RegNo < N && "Invalid register number"); 87 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 88 return MCDisassembler::Success; 89 } 90 91 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 92 uint64_t Address, 93 const MCDisassembler *Decoder) { 94 return decodeRegisterClass(Inst, RegNo, CRRegs); 95 } 96 97 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 98 uint64_t Address, 99 const MCDisassembler *Decoder) { 100 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 101 } 102 103 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 104 uint64_t Address, 105 const MCDisassembler *Decoder) { 106 return decodeRegisterClass(Inst, RegNo, FRegs); 107 } 108 109 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 110 uint64_t Address, 111 const MCDisassembler *Decoder) { 112 return decodeRegisterClass(Inst, RegNo, FRegs); 113 } 114 115 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 116 uint64_t Address, 117 const MCDisassembler *Decoder) { 118 return decodeRegisterClass(Inst, RegNo, VFRegs); 119 } 120 121 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 122 uint64_t Address, 123 const MCDisassembler *Decoder) { 124 return decodeRegisterClass(Inst, RegNo, VRegs); 125 } 126 127 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 128 uint64_t Address, 129 const MCDisassembler *Decoder) { 130 return decodeRegisterClass(Inst, RegNo, VSRegs); 131 } 132 133 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 134 uint64_t Address, 135 const MCDisassembler *Decoder) { 136 return decodeRegisterClass(Inst, RegNo, VSFRegs); 137 } 138 139 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 140 uint64_t Address, 141 const MCDisassembler *Decoder) { 142 return decodeRegisterClass(Inst, RegNo, VSSRegs); 143 } 144 145 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 146 uint64_t Address, 147 const MCDisassembler *Decoder) { 148 return decodeRegisterClass(Inst, RegNo, RRegs); 149 } 150 151 static DecodeStatus 152 DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, 153 const MCDisassembler *Decoder) { 154 return decodeRegisterClass(Inst, RegNo, RRegsNoR0); 155 } 156 157 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 158 uint64_t Address, 159 const MCDisassembler *Decoder) { 160 return decodeRegisterClass(Inst, RegNo, XRegs); 161 } 162 163 static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, 164 uint64_t Address, 165 const MCDisassembler *Decoder) { 166 return decodeRegisterClass(Inst, RegNo, XRegs); 167 } 168 169 static DecodeStatus 170 DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, 171 const MCDisassembler *Decoder) { 172 return decodeRegisterClass(Inst, RegNo, XRegsNoX0); 173 } 174 175 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 176 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 177 178 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, 179 uint64_t Address, 180 const MCDisassembler *Decoder) { 181 return decodeRegisterClass(Inst, RegNo, SPERegs); 182 } 183 184 static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, 185 uint64_t Address, 186 const MCDisassembler *Decoder) { 187 return decodeRegisterClass(Inst, RegNo, ACCRegs); 188 } 189 190 static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, 191 uint64_t Address, 192 const void *Decoder) { 193 return decodeRegisterClass(Inst, RegNo, WACCRegs); 194 } 195 196 static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo, 197 uint64_t Address, 198 const void *Decoder) { 199 return decodeRegisterClass(Inst, RegNo, WACC_HIRegs); 200 } 201 202 // TODO: Make this function static when the register class is used by a new 203 // instruction. 204 DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo, 205 uint64_t Address, 206 const void *Decoder) { 207 return decodeRegisterClass(Inst, RegNo, DMRROWRegs); 208 } 209 210 static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo, 211 uint64_t Address, 212 const void *Decoder) { 213 return decodeRegisterClass(Inst, RegNo, DMRROWpRegs); 214 } 215 216 static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 217 uint64_t Address, 218 const void *Decoder) { 219 return decodeRegisterClass(Inst, RegNo, DMRRegs); 220 } 221 222 // TODO: Make this function static when the register class is used by a new 223 // instruction. 224 DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, 225 uint64_t Address, const void *Decoder) { 226 return decodeRegisterClass(Inst, RegNo, DMRpRegs); 227 } 228 229 static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, 230 uint64_t Address, 231 const MCDisassembler *Decoder) { 232 return decodeRegisterClass(Inst, RegNo, VSRpRegs); 233 } 234 235 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 236 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 237 238 template <unsigned N> 239 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 240 int64_t Address, 241 const MCDisassembler *Decoder) { 242 if (!isUInt<N>(Imm)) 243 return MCDisassembler::Fail; 244 Inst.addOperand(MCOperand::createImm(Imm)); 245 return MCDisassembler::Success; 246 } 247 248 template <unsigned N> 249 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 250 int64_t Address, 251 const MCDisassembler *Decoder) { 252 if (!isUInt<N>(Imm)) 253 return MCDisassembler::Fail; 254 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 255 return MCDisassembler::Success; 256 } 257 258 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, 259 int64_t Address, 260 const MCDisassembler *Decoder) { 261 if (Imm != 0) 262 return MCDisassembler::Fail; 263 Inst.addOperand(MCOperand::createImm(Imm)); 264 return MCDisassembler::Success; 265 } 266 267 static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, 268 uint64_t Address, 269 const MCDisassembler *Decoder) { 270 if (RegNo & 1) 271 return MCDisassembler::Fail; 272 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1])); 273 return MCDisassembler::Success; 274 } 275 276 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 277 int64_t Address, 278 const MCDisassembler *Decoder) { 279 // Decode the memri field (imm, reg), which has the low 16-bits as the 280 // displacement and the next 5 bits as the register #. 281 282 uint64_t Base = Imm >> 16; 283 uint64_t Disp = Imm & 0xFFFF; 284 285 assert(Base < 32 && "Invalid base register"); 286 287 switch (Inst.getOpcode()) { 288 default: break; 289 case PPC::LBZU: 290 case PPC::LHAU: 291 case PPC::LHZU: 292 case PPC::LWZU: 293 case PPC::LFSU: 294 case PPC::LFDU: 295 // Add the tied output operand. 296 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 297 break; 298 case PPC::STBU: 299 case PPC::STHU: 300 case PPC::STWU: 301 case PPC::STFSU: 302 case PPC::STFDU: 303 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 304 break; 305 } 306 307 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 308 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 309 return MCDisassembler::Success; 310 } 311 312 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 313 int64_t Address, 314 const MCDisassembler *Decoder) { 315 // Decode the memrix field (imm, reg), which has the low 14-bits as the 316 // displacement and the next 5 bits as the register #. 317 318 uint64_t Base = Imm >> 14; 319 uint64_t Disp = Imm & 0x3FFF; 320 321 assert(Base < 32 && "Invalid base register"); 322 323 if (Inst.getOpcode() == PPC::LDU) 324 // Add the tied output operand. 325 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 326 else if (Inst.getOpcode() == PPC::STDU) 327 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 328 329 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 330 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 331 return MCDisassembler::Success; 332 } 333 334 static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm, 335 int64_t Address, 336 const MCDisassembler *Decoder) { 337 // Decode the memrix field for a hash store or hash check operation. 338 // The field is composed of a register and an immediate value that is 6 bits 339 // and covers the range -8 to -512. The immediate is always negative and 2s 340 // complement which is why we sign extend a 7 bit value. 341 const uint64_t Base = Imm >> 6; 342 const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8; 343 344 assert(Base < 32 && "Invalid base register"); 345 346 Inst.addOperand(MCOperand::createImm(Disp)); 347 Inst.addOperand(MCOperand::createReg(RRegs[Base])); 348 return MCDisassembler::Success; 349 } 350 351 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 352 int64_t Address, 353 const MCDisassembler *Decoder) { 354 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 355 // displacement with 16-byte aligned, and the next 5 bits as the register #. 356 357 uint64_t Base = Imm >> 12; 358 uint64_t Disp = Imm & 0xFFF; 359 360 assert(Base < 32 && "Invalid base register"); 361 362 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 363 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 364 return MCDisassembler::Success; 365 } 366 367 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm, 368 int64_t Address, 369 const MCDisassembler *Decoder) { 370 // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the 371 // displacement, and the next 5 bits as an immediate 0. 372 uint64_t Base = Imm >> 34; 373 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 374 375 assert(Base < 32 && "Invalid base register"); 376 377 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 378 return decodeImmZeroOperand(Inst, Base, Address, Decoder); 379 } 380 381 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm, 382 int64_t Address, 383 const MCDisassembler *Decoder) { 384 // Decode the memri34 field (imm, reg), which has the low 34-bits as the 385 // displacement, and the next 5 bits as the register #. 386 uint64_t Base = Imm >> 34; 387 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 388 389 assert(Base < 32 && "Invalid base register"); 390 391 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 392 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 393 return MCDisassembler::Success; 394 } 395 396 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, 397 int64_t Address, 398 const MCDisassembler *Decoder) { 399 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the 400 // displacement with 8-byte aligned, and the next 5 bits as the register #. 401 402 uint64_t Base = Imm >> 5; 403 uint64_t Disp = Imm & 0x1F; 404 405 assert(Base < 32 && "Invalid base register"); 406 407 Inst.addOperand(MCOperand::createImm(Disp << 3)); 408 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 409 return MCDisassembler::Success; 410 } 411 412 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, 413 int64_t Address, 414 const MCDisassembler *Decoder) { 415 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the 416 // displacement with 4-byte aligned, and the next 5 bits as the register #. 417 418 uint64_t Base = Imm >> 5; 419 uint64_t Disp = Imm & 0x1F; 420 421 assert(Base < 32 && "Invalid base register"); 422 423 Inst.addOperand(MCOperand::createImm(Disp << 2)); 424 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 425 return MCDisassembler::Success; 426 } 427 428 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, 429 int64_t Address, 430 const MCDisassembler *Decoder) { 431 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the 432 // displacement with 2-byte aligned, and the next 5 bits as the register #. 433 434 uint64_t Base = Imm >> 5; 435 uint64_t Disp = Imm & 0x1F; 436 437 assert(Base < 32 && "Invalid base register"); 438 439 Inst.addOperand(MCOperand::createImm(Disp << 1)); 440 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 441 return MCDisassembler::Success; 442 } 443 444 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 445 int64_t Address, 446 const MCDisassembler *Decoder) { 447 // The cr bit encoding is 0x80 >> cr_reg_num. 448 449 unsigned Zeros = llvm::countr_zero(Imm); 450 assert(Zeros < 8 && "Invalid CR bit value"); 451 452 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 453 return MCDisassembler::Success; 454 } 455 456 #include "PPCGenDisassemblerTables.inc" 457 458 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 459 ArrayRef<uint8_t> Bytes, 460 uint64_t Address, 461 raw_ostream &CS) const { 462 auto *ReadFunc = IsLittleEndian ? support::endian::read32le 463 : support::endian::read32be; 464 465 // If this is an 8-byte prefixed instruction, handle it here. 466 // Note: prefixed instructions aren't technically 8-byte entities - the prefix 467 // appears in memory at an address 4 bytes prior to that of the base 468 // instruction regardless of endianness. So we read the two pieces and 469 // rebuild the 8-byte instruction. 470 // TODO: In this function we call decodeInstruction several times with 471 // different decoder tables. It may be possible to only call once by 472 // looking at the top 6 bits of the instruction. 473 if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) { 474 uint32_t Prefix = ReadFunc(Bytes.data()); 475 uint32_t BaseInst = ReadFunc(Bytes.data() + 4); 476 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32; 477 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address, 478 this, STI); 479 if (result != MCDisassembler::Fail) { 480 Size = 8; 481 return result; 482 } 483 } 484 485 // Get the four bytes of the instruction. 486 Size = 4; 487 if (Bytes.size() < 4) { 488 Size = 0; 489 return MCDisassembler::Fail; 490 } 491 492 // Read the instruction in the proper endianness. 493 uint64_t Inst = ReadFunc(Bytes.data()); 494 495 if (STI.getFeatureBits()[PPC::FeatureSPE]) { 496 DecodeStatus result = 497 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI); 498 if (result != MCDisassembler::Fail) 499 return result; 500 } 501 502 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 503 } 504