1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "PPC.h" 11 #include "llvm/MC/MCDisassembler.h" 12 #include "llvm/MC/MCFixedLenDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/Support/TargetRegistry.h" 16 17 using namespace llvm; 18 19 #define DEBUG_TYPE "ppc-disassembler" 20 21 typedef MCDisassembler::DecodeStatus DecodeStatus; 22 23 namespace { 24 class PPCDisassembler : public MCDisassembler { 25 public: 26 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 27 : MCDisassembler(STI, Ctx) {} 28 virtual ~PPCDisassembler() {} 29 30 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 31 ArrayRef<uint8_t> Bytes, uint64_t Address, 32 raw_ostream &VStream, 33 raw_ostream &CStream) const override; 34 }; 35 } // end anonymous namespace 36 37 static MCDisassembler *createPPCDisassembler(const Target &T, 38 const MCSubtargetInfo &STI, 39 MCContext &Ctx) { 40 return new PPCDisassembler(STI, Ctx); 41 } 42 43 extern "C" void LLVMInitializePowerPCDisassembler() { 44 // Register the disassembler for each target. 45 TargetRegistry::RegisterMCDisassembler(ThePPC32Target, 46 createPPCDisassembler); 47 TargetRegistry::RegisterMCDisassembler(ThePPC64Target, 48 createPPCDisassembler); 49 TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget, 50 createPPCDisassembler); 51 } 52 53 // FIXME: These can be generated by TableGen from the existing register 54 // encoding values! 55 56 static const unsigned CRRegs[] = { 57 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 58 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 59 }; 60 61 static const unsigned CRBITRegs[] = { 62 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 63 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 64 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 65 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 66 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 67 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 68 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 69 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN 70 }; 71 72 static const unsigned FRegs[] = { 73 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 74 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 75 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 76 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 77 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 78 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 79 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 80 PPC::F28, PPC::F29, PPC::F30, PPC::F31 81 }; 82 83 static const unsigned VRegs[] = { 84 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 85 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 86 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 87 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 88 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 89 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 90 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 91 PPC::V28, PPC::V29, PPC::V30, PPC::V31 92 }; 93 94 static const unsigned VSRegs[] = { 95 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, 96 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, 97 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, 98 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, 99 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 100 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, 101 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, 102 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 103 104 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3, 105 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, 106 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11, 107 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15, 108 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19, 109 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23, 110 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27, 111 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31 112 }; 113 114 static const unsigned VSFRegs[] = { 115 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 116 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 117 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 118 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 119 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 120 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 121 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 122 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 123 124 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 125 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 126 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 127 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 128 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 129 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 130 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 131 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 132 }; 133 134 static const unsigned GPRegs[] = { 135 PPC::R0, PPC::R1, PPC::R2, PPC::R3, 136 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 137 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 138 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 139 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 140 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 141 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 142 PPC::R28, PPC::R29, PPC::R30, PPC::R31 143 }; 144 145 static const unsigned GP0Regs[] = { 146 PPC::ZERO, PPC::R1, PPC::R2, PPC::R3, 147 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 148 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 149 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 150 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 151 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 152 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 153 PPC::R28, PPC::R29, PPC::R30, PPC::R31 154 }; 155 156 static const unsigned G8Regs[] = { 157 PPC::X0, PPC::X1, PPC::X2, PPC::X3, 158 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 159 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 160 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 161 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 162 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 163 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 164 PPC::X28, PPC::X29, PPC::X30, PPC::X31 165 }; 166 167 template <std::size_t N> 168 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 169 const unsigned (&Regs)[N]) { 170 assert(RegNo < N && "Invalid register number"); 171 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo])); 172 return MCDisassembler::Success; 173 } 174 175 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 176 uint64_t Address, 177 const void *Decoder) { 178 return decodeRegisterClass(Inst, RegNo, CRRegs); 179 } 180 181 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 182 uint64_t Address, 183 const void *Decoder) { 184 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 185 } 186 187 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 188 uint64_t Address, 189 const void *Decoder) { 190 return decodeRegisterClass(Inst, RegNo, FRegs); 191 } 192 193 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 194 uint64_t Address, 195 const void *Decoder) { 196 return decodeRegisterClass(Inst, RegNo, FRegs); 197 } 198 199 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 200 uint64_t Address, 201 const void *Decoder) { 202 return decodeRegisterClass(Inst, RegNo, VRegs); 203 } 204 205 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 206 uint64_t Address, 207 const void *Decoder) { 208 return decodeRegisterClass(Inst, RegNo, VSRegs); 209 } 210 211 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 212 uint64_t Address, 213 const void *Decoder) { 214 return decodeRegisterClass(Inst, RegNo, VSFRegs); 215 } 216 217 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 218 uint64_t Address, 219 const void *Decoder) { 220 return decodeRegisterClass(Inst, RegNo, GPRegs); 221 } 222 223 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 224 uint64_t Address, 225 const void *Decoder) { 226 return decodeRegisterClass(Inst, RegNo, GP0Regs); 227 } 228 229 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 230 uint64_t Address, 231 const void *Decoder) { 232 return decodeRegisterClass(Inst, RegNo, G8Regs); 233 } 234 235 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 236 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 237 238 template<unsigned N> 239 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 240 int64_t Address, const void *Decoder) { 241 assert(isUInt<N>(Imm) && "Invalid immediate"); 242 Inst.addOperand(MCOperand::CreateImm(Imm)); 243 return MCDisassembler::Success; 244 } 245 246 template<unsigned N> 247 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 248 int64_t Address, const void *Decoder) { 249 assert(isUInt<N>(Imm) && "Invalid immediate"); 250 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm))); 251 return MCDisassembler::Success; 252 } 253 254 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 255 int64_t Address, const void *Decoder) { 256 // Decode the memri field (imm, reg), which has the low 16-bits as the 257 // displacement and the next 5 bits as the register #. 258 259 uint64_t Base = Imm >> 16; 260 uint64_t Disp = Imm & 0xFFFF; 261 262 assert(Base < 32 && "Invalid base register"); 263 264 switch (Inst.getOpcode()) { 265 default: break; 266 case PPC::LBZU: 267 case PPC::LHAU: 268 case PPC::LHZU: 269 case PPC::LWZU: 270 case PPC::LFSU: 271 case PPC::LFDU: 272 // Add the tied output operand. 273 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); 274 break; 275 case PPC::STBU: 276 case PPC::STHU: 277 case PPC::STWU: 278 case PPC::STFSU: 279 case PPC::STFDU: 280 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base])); 281 break; 282 } 283 284 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp))); 285 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); 286 return MCDisassembler::Success; 287 } 288 289 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 290 int64_t Address, const void *Decoder) { 291 // Decode the memrix field (imm, reg), which has the low 14-bits as the 292 // displacement and the next 5 bits as the register #. 293 294 uint64_t Base = Imm >> 14; 295 uint64_t Disp = Imm & 0x3FFF; 296 297 assert(Base < 32 && "Invalid base register"); 298 299 if (Inst.getOpcode() == PPC::LDU) 300 // Add the tied output operand. 301 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); 302 else if (Inst.getOpcode() == PPC::STDU) 303 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base])); 304 305 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2))); 306 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); 307 return MCDisassembler::Success; 308 } 309 310 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 311 int64_t Address, const void *Decoder) { 312 // The cr bit encoding is 0x80 >> cr_reg_num. 313 314 unsigned Zeros = countTrailingZeros(Imm); 315 assert(Zeros < 8 && "Invalid CR bit value"); 316 317 Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros])); 318 return MCDisassembler::Success; 319 } 320 321 #include "PPCGenDisassemblerTables.inc" 322 323 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 324 ArrayRef<uint8_t> Bytes, 325 uint64_t Address, raw_ostream &OS, 326 raw_ostream &CS) const { 327 // Get the four bytes of the instruction. 328 Size = 4; 329 if (Bytes.size() < 4) { 330 Size = 0; 331 return MCDisassembler::Fail; 332 } 333 334 // The instruction is big-endian encoded. 335 uint32_t Inst = 336 (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0); 337 338 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 339 } 340 341