1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCTargetDesc.h" 10 #include "TargetInfo/PowerPCTargetInfo.h" 11 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 12 #include "llvm/MC/MCFixedLenDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/Support/Endian.h" 16 #include "llvm/Support/TargetRegistry.h" 17 18 using namespace llvm; 19 20 DEFINE_PPC_REGCLASSES; 21 22 #define DEBUG_TYPE "ppc-disassembler" 23 24 typedef MCDisassembler::DecodeStatus DecodeStatus; 25 26 namespace { 27 class PPCDisassembler : public MCDisassembler { 28 bool IsLittleEndian; 29 30 public: 31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 32 bool IsLittleEndian) 33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 34 35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 36 ArrayRef<uint8_t> Bytes, uint64_t Address, 37 raw_ostream &CStream) const override; 38 }; 39 } // end anonymous namespace 40 41 static MCDisassembler *createPPCDisassembler(const Target &T, 42 const MCSubtargetInfo &STI, 43 MCContext &Ctx) { 44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 45 } 46 47 static MCDisassembler *createPPCLEDisassembler(const Target &T, 48 const MCSubtargetInfo &STI, 49 MCContext &Ctx) { 50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 51 } 52 53 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() { 54 // Register the disassembler for each target. 55 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), 56 createPPCDisassembler); 57 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), 58 createPPCDisassembler); 59 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), 60 createPPCLEDisassembler); 61 } 62 63 static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm, 64 uint64_t Addr, 65 const void *Decoder) { 66 int32_t Offset = SignExtend32<24>(Imm); 67 Inst.addOperand(MCOperand::createImm(Offset)); 68 return MCDisassembler::Success; 69 } 70 71 // FIXME: These can be generated by TableGen from the existing register 72 // encoding values! 73 74 template <std::size_t N> 75 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 76 const MCPhysReg (&Regs)[N]) { 77 assert(RegNo < N && "Invalid register number"); 78 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 79 return MCDisassembler::Success; 80 } 81 82 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 83 uint64_t Address, 84 const void *Decoder) { 85 return decodeRegisterClass(Inst, RegNo, CRRegs); 86 } 87 88 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 89 uint64_t Address, 90 const void *Decoder) { 91 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 92 } 93 94 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 95 uint64_t Address, 96 const void *Decoder) { 97 return decodeRegisterClass(Inst, RegNo, FRegs); 98 } 99 100 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 101 uint64_t Address, 102 const void *Decoder) { 103 return decodeRegisterClass(Inst, RegNo, FRegs); 104 } 105 106 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 107 uint64_t Address, 108 const void *Decoder) { 109 return decodeRegisterClass(Inst, RegNo, VFRegs); 110 } 111 112 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 113 uint64_t Address, 114 const void *Decoder) { 115 return decodeRegisterClass(Inst, RegNo, VRegs); 116 } 117 118 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 119 uint64_t Address, 120 const void *Decoder) { 121 return decodeRegisterClass(Inst, RegNo, VSRegs); 122 } 123 124 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 125 uint64_t Address, 126 const void *Decoder) { 127 return decodeRegisterClass(Inst, RegNo, VSFRegs); 128 } 129 130 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 131 uint64_t Address, 132 const void *Decoder) { 133 return decodeRegisterClass(Inst, RegNo, VSSRegs); 134 } 135 136 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 137 uint64_t Address, 138 const void *Decoder) { 139 return decodeRegisterClass(Inst, RegNo, RRegs); 140 } 141 142 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 143 uint64_t Address, 144 const void *Decoder) { 145 return decodeRegisterClass(Inst, RegNo, RRegsNoR0); 146 } 147 148 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 149 uint64_t Address, 150 const void *Decoder) { 151 return decodeRegisterClass(Inst, RegNo, XRegs); 152 } 153 154 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, 155 uint64_t Address, 156 const void *Decoder) { 157 return decodeRegisterClass(Inst, RegNo, XRegsNoX0); 158 } 159 160 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 161 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 162 163 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 164 uint64_t Address, 165 const void *Decoder) { 166 return decodeRegisterClass(Inst, RegNo, QFRegs); 167 } 168 169 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, 170 uint64_t Address, 171 const void *Decoder) { 172 return decodeRegisterClass(Inst, RegNo, SPERegs); 173 } 174 175 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 176 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 177 178 template<unsigned N> 179 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 180 int64_t Address, const void *Decoder) { 181 assert(isUInt<N>(Imm) && "Invalid immediate"); 182 Inst.addOperand(MCOperand::createImm(Imm)); 183 return MCDisassembler::Success; 184 } 185 186 template<unsigned N> 187 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 188 int64_t Address, const void *Decoder) { 189 assert(isUInt<N>(Imm) && "Invalid immediate"); 190 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 191 return MCDisassembler::Success; 192 } 193 194 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, 195 int64_t Address, const void *Decoder) { 196 if (Imm != 0) 197 return MCDisassembler::Fail; 198 Inst.addOperand(MCOperand::createImm(Imm)); 199 return MCDisassembler::Success; 200 } 201 202 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 203 int64_t Address, const void *Decoder) { 204 // Decode the memri field (imm, reg), which has the low 16-bits as the 205 // displacement and the next 5 bits as the register #. 206 207 uint64_t Base = Imm >> 16; 208 uint64_t Disp = Imm & 0xFFFF; 209 210 assert(Base < 32 && "Invalid base register"); 211 212 switch (Inst.getOpcode()) { 213 default: break; 214 case PPC::LBZU: 215 case PPC::LHAU: 216 case PPC::LHZU: 217 case PPC::LWZU: 218 case PPC::LFSU: 219 case PPC::LFDU: 220 // Add the tied output operand. 221 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 222 break; 223 case PPC::STBU: 224 case PPC::STHU: 225 case PPC::STWU: 226 case PPC::STFSU: 227 case PPC::STFDU: 228 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 229 break; 230 } 231 232 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 233 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 234 return MCDisassembler::Success; 235 } 236 237 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 238 int64_t Address, const void *Decoder) { 239 // Decode the memrix field (imm, reg), which has the low 14-bits as the 240 // displacement and the next 5 bits as the register #. 241 242 uint64_t Base = Imm >> 14; 243 uint64_t Disp = Imm & 0x3FFF; 244 245 assert(Base < 32 && "Invalid base register"); 246 247 if (Inst.getOpcode() == PPC::LDU) 248 // Add the tied output operand. 249 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 250 else if (Inst.getOpcode() == PPC::STDU) 251 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 252 253 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 254 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 255 return MCDisassembler::Success; 256 } 257 258 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 259 int64_t Address, const void *Decoder) { 260 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 261 // displacement with 16-byte aligned, and the next 5 bits as the register #. 262 263 uint64_t Base = Imm >> 12; 264 uint64_t Disp = Imm & 0xFFF; 265 266 assert(Base < 32 && "Invalid base register"); 267 268 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 269 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 270 return MCDisassembler::Success; 271 } 272 273 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm, 274 int64_t Address, 275 const void *Decoder) { 276 // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the 277 // displacement, and the next 5 bits as an immediate 0. 278 uint64_t Base = Imm >> 34; 279 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 280 281 assert(Base < 32 && "Invalid base register"); 282 283 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 284 return decodeImmZeroOperand(Inst, Base, Address, Decoder); 285 } 286 287 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm, 288 int64_t Address, 289 const void *Decoder) { 290 // Decode the memri34 field (imm, reg), which has the low 34-bits as the 291 // displacement, and the next 5 bits as the register #. 292 uint64_t Base = Imm >> 34; 293 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 294 295 assert(Base < 32 && "Invalid base register"); 296 297 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 298 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 299 return MCDisassembler::Success; 300 } 301 302 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, 303 int64_t Address, const void *Decoder) { 304 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the 305 // displacement with 8-byte aligned, and the next 5 bits as the register #. 306 307 uint64_t Base = Imm >> 5; 308 uint64_t Disp = Imm & 0x1F; 309 310 assert(Base < 32 && "Invalid base register"); 311 312 Inst.addOperand(MCOperand::createImm(Disp << 3)); 313 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 314 return MCDisassembler::Success; 315 } 316 317 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, 318 int64_t Address, const void *Decoder) { 319 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the 320 // displacement with 4-byte aligned, and the next 5 bits as the register #. 321 322 uint64_t Base = Imm >> 5; 323 uint64_t Disp = Imm & 0x1F; 324 325 assert(Base < 32 && "Invalid base register"); 326 327 Inst.addOperand(MCOperand::createImm(Disp << 2)); 328 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 329 return MCDisassembler::Success; 330 } 331 332 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, 333 int64_t Address, const void *Decoder) { 334 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the 335 // displacement with 2-byte aligned, and the next 5 bits as the register #. 336 337 uint64_t Base = Imm >> 5; 338 uint64_t Disp = Imm & 0x1F; 339 340 assert(Base < 32 && "Invalid base register"); 341 342 Inst.addOperand(MCOperand::createImm(Disp << 1)); 343 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 344 return MCDisassembler::Success; 345 } 346 347 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 348 int64_t Address, const void *Decoder) { 349 // The cr bit encoding is 0x80 >> cr_reg_num. 350 351 unsigned Zeros = countTrailingZeros(Imm); 352 assert(Zeros < 8 && "Invalid CR bit value"); 353 354 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 355 return MCDisassembler::Success; 356 } 357 358 #include "PPCGenDisassemblerTables.inc" 359 360 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 361 ArrayRef<uint8_t> Bytes, 362 uint64_t Address, 363 raw_ostream &CS) const { 364 auto *ReadFunc = IsLittleEndian ? support::endian::read32le 365 : support::endian::read32be; 366 367 // If this is an 8-byte prefixed instruction, handle it here. 368 // Note: prefixed instructions aren't technically 8-byte entities - the prefix 369 // appears in memory at an address 4 bytes prior to that of the base 370 // instruction regardless of endianness. So we read the two pieces and 371 // rebuild the 8-byte instruction. 372 // TODO: In this function we call decodeInstruction several times with 373 // different decoder tables. It may be possible to only call once by 374 // looking at the top 6 bits of the instruction. 375 if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) { 376 uint32_t Prefix = ReadFunc(Bytes.data()); 377 uint32_t BaseInst = ReadFunc(Bytes.data() + 4); 378 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32; 379 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address, 380 this, STI); 381 if (result != MCDisassembler::Fail) { 382 Size = 8; 383 return result; 384 } 385 } 386 387 // Get the four bytes of the instruction. 388 Size = 4; 389 if (Bytes.size() < 4) { 390 Size = 0; 391 return MCDisassembler::Fail; 392 } 393 394 // Read the instruction in the proper endianness. 395 uint64_t Inst = ReadFunc(Bytes.data()); 396 397 if (STI.getFeatureBits()[PPC::FeatureQPX]) { 398 DecodeStatus result = 399 decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI); 400 if (result != MCDisassembler::Fail) 401 return result; 402 } else if (STI.getFeatureBits()[PPC::FeatureSPE]) { 403 DecodeStatus result = 404 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI); 405 if (result != MCDisassembler::Fail) 406 return result; 407 } 408 409 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 410 } 411