1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "PPC.h" 11 #include "llvm/MC/MCDisassembler.h" 12 #include "llvm/MC/MCFixedLenDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/Support/MemoryObject.h" 16 #include "llvm/Support/TargetRegistry.h" 17 18 using namespace llvm; 19 20 typedef MCDisassembler::DecodeStatus DecodeStatus; 21 22 namespace { 23 class PPCDisassembler : public MCDisassembler { 24 public: 25 PPCDisassembler(const MCSubtargetInfo &STI) 26 : MCDisassembler(STI) {} 27 virtual ~PPCDisassembler() {} 28 29 // Override MCDisassembler. 30 virtual DecodeStatus getInstruction(MCInst &instr, 31 uint64_t &size, 32 const MemoryObject ®ion, 33 uint64_t address, 34 raw_ostream &vStream, 35 raw_ostream &cStream) const override; 36 }; 37 } // end anonymous namespace 38 39 static MCDisassembler *createPPCDisassembler(const Target &T, 40 const MCSubtargetInfo &STI) { 41 return new PPCDisassembler(STI); 42 } 43 44 extern "C" void LLVMInitializePowerPCDisassembler() { 45 // Register the disassembler for each target. 46 TargetRegistry::RegisterMCDisassembler(ThePPC32Target, 47 createPPCDisassembler); 48 TargetRegistry::RegisterMCDisassembler(ThePPC64Target, 49 createPPCDisassembler); 50 TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget, 51 createPPCDisassembler); 52 } 53 54 // FIXME: These can be generated by TableGen from the existing register 55 // encoding values! 56 57 static const unsigned CRRegs[] = { 58 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 59 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 60 }; 61 62 static const unsigned CRBITRegs[] = { 63 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 64 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 65 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 66 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 67 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 68 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 69 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 70 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN 71 }; 72 73 static const unsigned FRegs[] = { 74 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 75 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 76 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 77 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 78 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 79 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 80 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 81 PPC::F28, PPC::F29, PPC::F30, PPC::F31 82 }; 83 84 static const unsigned VRegs[] = { 85 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 86 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 87 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 88 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 89 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 90 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 91 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 92 PPC::V28, PPC::V29, PPC::V30, PPC::V31 93 }; 94 95 static const unsigned VSRegs[] = { 96 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, 97 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, 98 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, 99 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, 100 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 101 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, 102 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, 103 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 104 105 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3, 106 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, 107 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11, 108 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15, 109 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19, 110 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23, 111 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27, 112 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31 113 }; 114 115 static const unsigned GPRegs[] = { 116 PPC::R0, PPC::R1, PPC::R2, PPC::R3, 117 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 118 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 119 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 120 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 121 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 122 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 123 PPC::R28, PPC::R29, PPC::R30, PPC::R31 124 }; 125 126 static const unsigned GP0Regs[] = { 127 PPC::ZERO, PPC::R1, PPC::R2, PPC::R3, 128 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 129 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 130 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 131 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 132 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 133 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 134 PPC::R28, PPC::R29, PPC::R30, PPC::R31 135 }; 136 137 static const unsigned G8Regs[] = { 138 PPC::X0, PPC::X1, PPC::X2, PPC::X3, 139 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 140 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 141 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 142 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 143 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 144 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 145 PPC::X28, PPC::X29, PPC::X30, PPC::X31 146 }; 147 148 template <std::size_t N> 149 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 150 const unsigned (&Regs)[N]) { 151 assert(RegNo < N && "Invalid register number"); 152 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo])); 153 return MCDisassembler::Success; 154 } 155 156 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 157 uint64_t Address, 158 const void *Decoder) { 159 return decodeRegisterClass(Inst, RegNo, CRRegs); 160 } 161 162 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 163 uint64_t Address, 164 const void *Decoder) { 165 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 166 } 167 168 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 169 uint64_t Address, 170 const void *Decoder) { 171 return decodeRegisterClass(Inst, RegNo, FRegs); 172 } 173 174 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 175 uint64_t Address, 176 const void *Decoder) { 177 return decodeRegisterClass(Inst, RegNo, FRegs); 178 } 179 180 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 181 uint64_t Address, 182 const void *Decoder) { 183 return decodeRegisterClass(Inst, RegNo, VRegs); 184 } 185 186 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 187 uint64_t Address, 188 const void *Decoder) { 189 return decodeRegisterClass(Inst, RegNo, VSRegs); 190 } 191 192 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 193 uint64_t Address, 194 const void *Decoder) { 195 return decodeRegisterClass(Inst, RegNo, GPRegs); 196 } 197 198 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 199 uint64_t Address, 200 const void *Decoder) { 201 return decodeRegisterClass(Inst, RegNo, GP0Regs); 202 } 203 204 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 205 uint64_t Address, 206 const void *Decoder) { 207 return decodeRegisterClass(Inst, RegNo, G8Regs); 208 } 209 210 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 211 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 212 213 template<unsigned N> 214 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 215 int64_t Address, const void *Decoder) { 216 assert(isUInt<N>(Imm) && "Invalid immediate"); 217 Inst.addOperand(MCOperand::CreateImm(Imm)); 218 return MCDisassembler::Success; 219 } 220 221 template<unsigned N> 222 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 223 int64_t Address, const void *Decoder) { 224 assert(isUInt<N>(Imm) && "Invalid immediate"); 225 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm))); 226 return MCDisassembler::Success; 227 } 228 229 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 230 int64_t Address, const void *Decoder) { 231 // Decode the memri field (imm, reg), which has the low 16-bits as the 232 // displacement and the next 5 bits as the register #. 233 234 uint64_t Base = Imm >> 16; 235 uint64_t Disp = Imm & 0xFFFF; 236 237 assert(Base < 32 && "Invalid base register"); 238 239 switch (Inst.getOpcode()) { 240 default: break; 241 case PPC::LBZU: 242 case PPC::LHAU: 243 case PPC::LHZU: 244 case PPC::LWZU: 245 case PPC::LFSU: 246 case PPC::LFDU: 247 // Add the tied output operand. 248 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); 249 break; 250 case PPC::STBU: 251 case PPC::STHU: 252 case PPC::STWU: 253 case PPC::STFSU: 254 case PPC::STFDU: 255 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base])); 256 break; 257 } 258 259 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp))); 260 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); 261 return MCDisassembler::Success; 262 } 263 264 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 265 int64_t Address, const void *Decoder) { 266 // Decode the memrix field (imm, reg), which has the low 14-bits as the 267 // displacement and the next 5 bits as the register #. 268 269 uint64_t Base = Imm >> 14; 270 uint64_t Disp = Imm & 0x3FFF; 271 272 assert(Base < 32 && "Invalid base register"); 273 274 if (Inst.getOpcode() == PPC::LDU) 275 // Add the tied output operand. 276 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); 277 else if (Inst.getOpcode() == PPC::STDU) 278 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base])); 279 280 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2))); 281 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base])); 282 return MCDisassembler::Success; 283 } 284 285 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 286 int64_t Address, const void *Decoder) { 287 // The cr bit encoding is 0x80 >> cr_reg_num. 288 289 unsigned Zeros = countTrailingZeros(Imm); 290 assert(Zeros < 8 && "Invalid CR bit value"); 291 292 Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros])); 293 return MCDisassembler::Success; 294 } 295 296 #include "PPCGenDisassemblerTables.inc" 297 298 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 299 const MemoryObject &Region, 300 uint64_t Address, 301 raw_ostream &os, 302 raw_ostream &cs) const { 303 // Get the four bytes of the instruction. 304 uint8_t Bytes[4]; 305 Size = 4; 306 if (Region.readBytes(Address, Size, Bytes) == -1) { 307 Size = 0; 308 return MCDisassembler::Fail; 309 } 310 311 // The instruction is big-endian encoded. 312 uint32_t Inst = (Bytes[0] << 24) | 313 (Bytes[1] << 16) | 314 (Bytes[2] << 8) | 315 (Bytes[3] << 0); 316 317 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 318 } 319 320