1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "PPC.h" 11 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 12 #include "llvm/MC/MCFixedLenDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/Support/Endian.h" 16 #include "llvm/Support/TargetRegistry.h" 17 18 using namespace llvm; 19 20 #define DEBUG_TYPE "ppc-disassembler" 21 22 typedef MCDisassembler::DecodeStatus DecodeStatus; 23 24 namespace { 25 class PPCDisassembler : public MCDisassembler { 26 bool IsLittleEndian; 27 28 public: 29 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 30 bool IsLittleEndian) 31 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 32 33 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 34 ArrayRef<uint8_t> Bytes, uint64_t Address, 35 raw_ostream &VStream, 36 raw_ostream &CStream) const override; 37 }; 38 } // end anonymous namespace 39 40 static MCDisassembler *createPPCDisassembler(const Target &T, 41 const MCSubtargetInfo &STI, 42 MCContext &Ctx) { 43 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 44 } 45 46 static MCDisassembler *createPPCLEDisassembler(const Target &T, 47 const MCSubtargetInfo &STI, 48 MCContext &Ctx) { 49 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 50 } 51 52 extern "C" void LLVMInitializePowerPCDisassembler() { 53 // Register the disassembler for each target. 54 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), 55 createPPCDisassembler); 56 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), 57 createPPCDisassembler); 58 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), 59 createPPCLEDisassembler); 60 } 61 62 // FIXME: These can be generated by TableGen from the existing register 63 // encoding values! 64 65 static const unsigned CRRegs[] = { 66 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 67 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 68 }; 69 70 static const unsigned CRBITRegs[] = { 71 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 72 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 73 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 74 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 75 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 76 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 77 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 78 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN 79 }; 80 81 static const unsigned FRegs[] = { 82 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 83 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 84 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 85 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 86 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 87 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 88 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 89 PPC::F28, PPC::F29, PPC::F30, PPC::F31 90 }; 91 92 static const unsigned VFRegs[] = { 93 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 94 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 95 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 96 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 97 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 98 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 99 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 100 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 101 }; 102 103 static const unsigned VRegs[] = { 104 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 105 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 106 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 107 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 108 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 109 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 110 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 111 PPC::V28, PPC::V29, PPC::V30, PPC::V31 112 }; 113 114 static const unsigned VSRegs[] = { 115 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, 116 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, 117 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, 118 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, 119 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 120 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, 121 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, 122 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 123 124 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 125 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 126 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 127 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 128 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 129 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 130 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 131 PPC::V28, PPC::V29, PPC::V30, PPC::V31 132 }; 133 134 static const unsigned VSFRegs[] = { 135 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 136 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 137 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 138 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 139 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 140 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 141 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 142 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 143 144 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 145 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 146 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 147 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 148 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 149 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 150 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 151 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 152 }; 153 154 static const unsigned VSSRegs[] = { 155 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 156 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 157 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 158 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 159 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 160 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 161 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 162 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 163 164 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 165 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 166 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 167 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 168 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 169 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 170 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 171 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 172 }; 173 174 static const unsigned GPRegs[] = { 175 PPC::R0, PPC::R1, PPC::R2, PPC::R3, 176 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 177 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 178 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 179 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 180 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 181 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 182 PPC::R28, PPC::R29, PPC::R30, PPC::R31 183 }; 184 185 static const unsigned GP0Regs[] = { 186 PPC::ZERO, PPC::R1, PPC::R2, PPC::R3, 187 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 188 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 189 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 190 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 191 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 192 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 193 PPC::R28, PPC::R29, PPC::R30, PPC::R31 194 }; 195 196 static const unsigned G8Regs[] = { 197 PPC::X0, PPC::X1, PPC::X2, PPC::X3, 198 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 199 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 200 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 201 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 202 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 203 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 204 PPC::X28, PPC::X29, PPC::X30, PPC::X31 205 }; 206 207 static const unsigned G80Regs[] = { 208 PPC::ZERO8, PPC::X1, PPC::X2, PPC::X3, 209 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 210 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 211 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 212 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 213 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 214 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 215 PPC::X28, PPC::X29, PPC::X30, PPC::X31 216 }; 217 218 static const unsigned QFRegs[] = { 219 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3, 220 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7, 221 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, 222 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15, 223 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19, 224 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23, 225 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27, 226 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31 227 }; 228 229 template <std::size_t N> 230 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 231 const unsigned (&Regs)[N]) { 232 assert(RegNo < N && "Invalid register number"); 233 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 234 return MCDisassembler::Success; 235 } 236 237 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 238 uint64_t Address, 239 const void *Decoder) { 240 return decodeRegisterClass(Inst, RegNo, CRRegs); 241 } 242 243 static DecodeStatus DecodeCRRC0RegisterClass(MCInst &Inst, uint64_t RegNo, 244 uint64_t Address, 245 const void *Decoder) { 246 return decodeRegisterClass(Inst, RegNo, CRRegs); 247 } 248 249 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 250 uint64_t Address, 251 const void *Decoder) { 252 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 253 } 254 255 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 256 uint64_t Address, 257 const void *Decoder) { 258 return decodeRegisterClass(Inst, RegNo, FRegs); 259 } 260 261 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 262 uint64_t Address, 263 const void *Decoder) { 264 return decodeRegisterClass(Inst, RegNo, FRegs); 265 } 266 267 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 268 uint64_t Address, 269 const void *Decoder) { 270 return decodeRegisterClass(Inst, RegNo, VFRegs); 271 } 272 273 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 274 uint64_t Address, 275 const void *Decoder) { 276 return decodeRegisterClass(Inst, RegNo, VRegs); 277 } 278 279 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 280 uint64_t Address, 281 const void *Decoder) { 282 return decodeRegisterClass(Inst, RegNo, VSRegs); 283 } 284 285 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 286 uint64_t Address, 287 const void *Decoder) { 288 return decodeRegisterClass(Inst, RegNo, VSFRegs); 289 } 290 291 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 292 uint64_t Address, 293 const void *Decoder) { 294 return decodeRegisterClass(Inst, RegNo, VSSRegs); 295 } 296 297 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 298 uint64_t Address, 299 const void *Decoder) { 300 return decodeRegisterClass(Inst, RegNo, GPRegs); 301 } 302 303 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 304 uint64_t Address, 305 const void *Decoder) { 306 return decodeRegisterClass(Inst, RegNo, GP0Regs); 307 } 308 309 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 310 uint64_t Address, 311 const void *Decoder) { 312 return decodeRegisterClass(Inst, RegNo, G8Regs); 313 } 314 315 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, 316 uint64_t Address, 317 const void *Decoder) { 318 return decodeRegisterClass(Inst, RegNo, G80Regs); 319 } 320 321 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 322 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 323 324 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 325 uint64_t Address, 326 const void *Decoder) { 327 return decodeRegisterClass(Inst, RegNo, QFRegs); 328 } 329 330 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 331 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 332 333 template<unsigned N> 334 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 335 int64_t Address, const void *Decoder) { 336 assert(isUInt<N>(Imm) && "Invalid immediate"); 337 Inst.addOperand(MCOperand::createImm(Imm)); 338 return MCDisassembler::Success; 339 } 340 341 template<unsigned N> 342 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 343 int64_t Address, const void *Decoder) { 344 assert(isUInt<N>(Imm) && "Invalid immediate"); 345 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 346 return MCDisassembler::Success; 347 } 348 349 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 350 int64_t Address, const void *Decoder) { 351 // Decode the memri field (imm, reg), which has the low 16-bits as the 352 // displacement and the next 5 bits as the register #. 353 354 uint64_t Base = Imm >> 16; 355 uint64_t Disp = Imm & 0xFFFF; 356 357 assert(Base < 32 && "Invalid base register"); 358 359 switch (Inst.getOpcode()) { 360 default: break; 361 case PPC::LBZU: 362 case PPC::LHAU: 363 case PPC::LHZU: 364 case PPC::LWZU: 365 case PPC::LFSU: 366 case PPC::LFDU: 367 // Add the tied output operand. 368 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); 369 break; 370 case PPC::STBU: 371 case PPC::STHU: 372 case PPC::STWU: 373 case PPC::STFSU: 374 case PPC::STFDU: 375 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base])); 376 break; 377 } 378 379 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 380 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); 381 return MCDisassembler::Success; 382 } 383 384 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 385 int64_t Address, const void *Decoder) { 386 // Decode the memrix field (imm, reg), which has the low 14-bits as the 387 // displacement and the next 5 bits as the register #. 388 389 uint64_t Base = Imm >> 14; 390 uint64_t Disp = Imm & 0x3FFF; 391 392 assert(Base < 32 && "Invalid base register"); 393 394 if (Inst.getOpcode() == PPC::LDU) 395 // Add the tied output operand. 396 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); 397 else if (Inst.getOpcode() == PPC::STDU) 398 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base])); 399 400 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 401 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); 402 return MCDisassembler::Success; 403 } 404 405 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 406 int64_t Address, const void *Decoder) { 407 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 408 // displacement with 16-byte aligned, and the next 5 bits as the register #. 409 410 uint64_t Base = Imm >> 12; 411 uint64_t Disp = Imm & 0xFFF; 412 413 assert(Base < 32 && "Invalid base register"); 414 415 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 416 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); 417 return MCDisassembler::Success; 418 } 419 420 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 421 int64_t Address, const void *Decoder) { 422 // The cr bit encoding is 0x80 >> cr_reg_num. 423 424 unsigned Zeros = countTrailingZeros(Imm); 425 assert(Zeros < 8 && "Invalid CR bit value"); 426 427 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 428 return MCDisassembler::Success; 429 } 430 431 #include "PPCGenDisassemblerTables.inc" 432 433 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 434 ArrayRef<uint8_t> Bytes, 435 uint64_t Address, raw_ostream &OS, 436 raw_ostream &CS) const { 437 // Get the four bytes of the instruction. 438 Size = 4; 439 if (Bytes.size() < 4) { 440 Size = 0; 441 return MCDisassembler::Fail; 442 } 443 444 // Read the instruction in the proper endianness. 445 uint32_t Inst = IsLittleEndian ? support::endian::read32le(Bytes.data()) 446 : support::endian::read32be(Bytes.data()); 447 448 if (STI.getFeatureBits()[PPC::FeatureQPX]) { 449 DecodeStatus result = 450 decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI); 451 if (result != MCDisassembler::Fail) 452 return result; 453 } 454 455 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 456 } 457 458